JPH04352518A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To execute a viterbi signal processing at high speed with a little memory capacity by adding a little hardwares at a digital signal processor. CONSTITUTION:A comparator 14 compares an added result by an arithmetic means 12 with an added result temporarily stored in a first register 13 beforehand, and an inverter circuit 9 and the arithmetic means 12 performs arithmetic and logic operation between a result of shifting and outputting a constant outputted from a constant circuit 3 by a barrel shifter 5 and the storage destination data of a path select signal. In this arithmetic and logic operation, the arithmetic means 12 is operated corresponding to a select control signal 15 outputted from the comparator 14 and the select control signal 15 is stored in the prescribed bit position of the storage destination data for the unit of a bit so as to execute the adding, comparing and selecting operations of the cumulative amount of a remaining path in viterbi decoding and to store a path select signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit within a digital signal processor that performs Viterbi decoding of convolutional codes for error correction.

0002

[Prior Art] In recent years, digital signal processing processors (
DSP (hereinafter abbreviated as "DSP") is attracting attention as a processor for use in devices such as mobile phones, in line with the trend of introducing digital systems into the mobile communication field. In a DSP for realizing such a voice encoding device for digital mobile communication, it is necessary to perform error correction processing in addition to operations such as voice encoding processing. Some error correction techniques use Viterbi decoding.

The Viterbi algorithm realizes maximum likelihood decoding of convolutional codes by repeating simple processes of addition, comparison, and selection. In this Viterbi decoding, each time encoded data (received sequence) corresponding to one information bit is obtained, the metric of the surviving path in each state at that time is calculated and updated. In a convolutional encoder with constraint length k, FIG.
It shows that two paths representing state transitions extend from 1. a and b are Hamming distances (branch metrics) between the output symbol of the path input to state Sn and the received sequence. To select a path, first calculate the overall metric of each path by adding the above branch metric to the metric value of each surviving path from the previous point in time from a table of metrics for each branch calculated in advance. . The metrics of the two paths input to state S2n are compared, and the path with the smaller total Hamming distance is retained, and the others are discarded. As described above, decoding of convolutional codes using the Viterbi algorithm involves adding the branch metric and the path metric for the input up to the previous point, comparing the metrics, and selecting the optimal path. It is necessary to perform the addition comparison selection operation and storage of path metrics for 2k-1 states for each time series.

FIG. 2 shows a block diagram of a conventional arithmetic unit. In Figure 2, 1 is the metric (cumulative metric) of the path of each state in processor instruction words and Viterbi decoding, and the branch metric taken by each path for the value of encoded data (received sequence) corresponding to 1 information bit. 2 is a bus connected to the main memory 1 and supplies data and stores calculation results. 12 is a bus that performs arithmetic and logical operations. It is an arithmetic logic operation circuit. 10 is a latch circuit that temporarily stores the value of the left input of the logic operation circuit 12, 6 is a latch circuit that temporarily stores the value of the right input, and 18 and 19 are registers that temporarily store the calculation results.

[0005] Regarding the arithmetic unit configured as described above, the operation of the Viterbi decoding addition/comparison selection operation performed on one received sequence and the storage of the path selection signal will be explained in the following six steps. .

(1) First addition step of path metric and branch metric The value of the path metric in state Sn shown in FIG. 3 is stored in the latch circuit 10 from the main storage unit 1 via the bus 2,
Similarly, the value of the branch metric a is stored in the latch circuit 6 from the main storage section 1 via the bus 2. The arithmetic and logic operation circuit 12 adds the contents of the latch circuits 10 and 6 and stores it in the register 18.

(2) Second addition step of path metric and branch metric The value of the path metric in state Sn+2k-1 shown in FIG.
Similarly, the value of the branch metric b is stored in the latch circuit 6 from the main memory section 1 via the bus 2. The arithmetic and logic operation circuit 12 adds the contents of the latch circuits 10 and 6 and stores it in the register 19.

(3) Subtraction of two addition results (comparison of size)
The contents of step registers 18 and 19 are stored in latch circuits 10 and 6, respectively. The arithmetic logic operation circuit 12 is the latch circuit 10
and subtract 6. Results are not stored.

(4) Sign determination (selection) step control unit (not shown) of the operation result determines the sign of the subtraction result in (3) and performs program control (branching) of the following steps (5) and (6). I do.

(5) Storing the addition result determined to be small (updating the path metric) If the subtraction result in (3) is negative as a result of step (4), the contents of the register 18 are stored in the main memory 1. Store in. If the subtraction result in (3) is positive, the contents of the register 19 are stored in the main memory section 1.

(6) Path selection signal storage step (4)
If the result of subtraction in (3) is negative, the value is "0".
is stored in the main storage unit 1. If the subtraction result in (3) is positive, the value "1" is stored in the main storage unit 1.

[0012] As described above, in the conventional arithmetic device described above, the arithmetic and logic operation circuit performs addition and comparison in Viterbi decoding, and program control is performed based on the results of this comparison, thereby making it possible to perform Viterbi decoding processing.

[0013]

[Problems to be Solved by the Invention] However, in the conventional arithmetic device described above, the number of arithmetic steps required for one addition, comparison and selection operation is large, and the amount of memory is large because one bit of the path selection signal is stored in one word of the memory. The problem was that it required .

The present invention solves these conventional problems, and aims to provide an excellent arithmetic device that can perform Viterbi decoding with a small number of arithmetic steps and a small amount of memory. be.

[0015]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an arithmetic device that performs processing such as Viterbi decoding.
a calculation means for adding data in a first memory member for storing data; a first register for temporarily storing the output of the calculation means; and a magnitude comparison between the output of the first register and the output of the calculation means. a comparator that outputs a selection control signal; a second memory member that stores the smaller output of the first register output and the arithmetic means output; and constant output means that outputs a predetermined constant. a shifter for shifting the output of the constant output means; a shift bit number output means for outputting the number of shift bits necessary for the shift operation of the shifter; and a selection control signal from the comparison circuit to control the calculation mode of the calculation means. and an arithmetic control means for causing the arithmetic means to perform addition of data stored in the first memory and arithmetic and logical operations on the output of the shifter through arithmetic mode control by the arithmetic control means. The gist is that.

[0016]

[Operation] Therefore, according to the present invention, the comparator compares the addition result by the adder with the addition result temporarily stored in the first register in advance, and the addition result determined by the comparator to be small is used as the first addition result. The arithmetic and logic operation circuit performs an arithmetic and logic operation on the result of the shifter outputting the constant stored in the memory No. 2 and outputted by the constant output means by n bits to the left and the storage destination data of the selection control signal, By storing the selection control signal output by the comparator in the n-th bit position of the storage destination data, the addition and comparison selection operation of the cumulative metric of the surviving paths in Viterbi decoding and the storage of the path selection signal can be performed in a small number of steps. This has the advantage that it can be performed with a small amount of memory.

[0017]

[Embodiment] Below, regarding an arithmetic device according to an embodiment of the present invention,
This will be explained with reference to the drawings.

FIG. 1 shows a block diagram of an arithmetic unit in an embodiment of the present invention. In FIG. 1, numeral 1 indicates the first
The main memory section 1 is a main memory section that serves as a memory component of the processor, and the main memory section 1 stores instruction words of the processor, path metrics (cumulative metrics) of each state in Viterbi decoding, and encoded data (received sequence information) corresponding to one information bit. ), a table of branch metric values taken by each path with respect to the value of , a selection result of a surviving path in each state, etc. are stored.

2 is a bus connected to the main storage unit 1 for supplying data and storing calculation results; 3 is a constant circuit for outputting a constant whose least significant bit is 1 and all other bits are 0; 4 is a register that temporarily stores the number of shift bits output from the instruction decoding unit (not shown) of the processor connected to bus 2 and outputs it to bus 2, etc.; 5 is an input for the output of constant circuit 3 or register 4; , a barrel shifter that shifts the number of shift bits indicated by the register 4 or outputs the output without shifting, 6 a latch circuit that latches the output of the barrel shifter 5, and 9 an exclusive OR gate that outputs the output of the latch circuit 6. 10 is a latch circuit that latches the data bus output.

Further, 7 is an operation for outputting a control signal 8 instructing the inverting circuit 9 to perform an inverting operation or not, and a control signal 11 instructing the logical operation circuit 12 to perform an OR or an AND. 12 is an arithmetic logic operation circuit as a calculation means for performing arithmetic and logic operations using the outputs of the latch circuit 10 and the inversion circuit 9 as inputs; 13 is a register that temporarily stores the output of the arithmetic logic operation circuit 12; 14 is a register 13; A comparator 16 compares the contents of the register 13 with the output of the arithmetic logic circuit 12 and outputs a selection control signal 15 to the arithmetic control section 7 and the selector 16. A selector 17 selects the smaller one of the outputs of the circuit 12, and a register 17 serves as a second memory member that stores the selector output.

Regarding the arithmetic device configured in this way,
The operation will be explained below. First (Table 1) is the selection control signal 15.
The relationship between the value of and the operation contents of the inverting circuit 9 and the arithmetic and logic operation circuit 12 is shown.

[0022]

[Table 1]

The arithmetic control section 7 controls the inverting circuit 9 and the logical arithmetic circuit 12 according to the relationship shown in Table 1. That is, when the selection control signal 15 is "0" (register 1
(If the value of 3 is small) The inversion circuit 9 performs an inversion operation, while the arithmetic logic operation circuit 12 calculates a logical product. On the other hand, when the selection control signal 15 is "1" (when the addition result is small), the inversion circuit 9 performs a non-inversion operation, while the arithmetic logic operation circuit 12 calculates a logical sum.

Hereinafter, with reference to FIG. 3, we will explain the addition, comparison and selection operation of Viterbi decoding performed for one state of the convolutional encoder and the storage of the path selection signal. (2) the step of second addition and comparison selection; and (3) the step of bit transfer of the path selection signal.

(1) First addition step of path metric and branch metric The value of the path metric in state Sn shown in FIG. 3 is stored in the latch circuit 10 from the main storage unit 1 via the bus 2,
Similarly, the value of the branch metric a is stored in the latch circuit 6 from the main storage section 1 via the bus 2. At this time, the barrel shifter 6 does not perform a shift operation. Arithmetic logic circuit 1
2 adds the contents of the latch circuits 10 and 6 and stores the result in the register 13. Further, the value of the path metric temporarily stored in the register 17 and updated by the addition comparison selection operation one cycle before is stored in the main storage unit 1.

(2) Second addition and comparison selection step The value of the path metric in the state Sn+2k-1 shown in FIG. Similarly, the value of main memory 1
The data is stored in the latch circuit 6 via the bus 2. At this time, the barrel shifter 6 does not perform a shifting operation. The arithmetic and logic operation circuit 12 adds the contents of the latch circuits 10 and 6 and outputs the result to the comparator 14. The comparator 14 compares the addition result with the value of the register 13, and outputs a 1-bit selection control signal 15 of "0" if the value of the register 13 is small, and "1" if the addition result is small. It is output to the selector 16 and the calculation control section 7. The selector 16 selects the value of the register 13 when the selection control signal 15 is "0", and selects the arithmetic logic circuit output when the selection control signal 15 is "1", and stores it in the register 17.

(3) Step of Bit Transfer of Path Selection Signal First, the destination word storing the path selection signal in the main memory section 1 is latched into the latch circuit 10 via the bus 2. At the same time, the barrel shifter 5 shifts the constant (00000001) input from the constant circuit 3 to the left by the value n stored in the register 4 from the instruction decoding section, outputs it, and latches it into the latch circuit 6. Next, as shown in Table 1, the inverting circuit 9 inverts the contents of the latch circuit 6 when the selection control signal 15 input to the arithmetic control section in step (2) is "0". , "1", the output is non-inverted to the arithmetic and logic operation circuit 12. The arithmetic logic operation circuit 12 performs a logical operation on the destination word stored in the latch circuit 10 and the output of the inversion circuit 9, and performs an AND operation when the selection control signal 15 is "0" as shown in (Table 1). ,″
1'', calculates the logical sum, outputs it to bus 2, and stores it in main memory 1.This allows the path selection signal (selection control signal 15) to be placed in any bit position in main memory 1 in 1-bit units. Can be stored.

As described above, according to this embodiment, the addition result by the arithmetic and logic operation circuit 12 in step (2) is compared in magnitude with the addition result temporarily stored in the register 12 in advance in step (1). The selector 16 selects the addition result determined by the comparator 14 to be small and temporarily stores it in the register 17, and the barrel shifter 5 shifts the constant output by the constant circuit 3 to the left by n bits and outputs it. The inverting circuit 9 and the arithmetic logic operation circuit 12 perform a logical operation on the result and the storage destination data of the selection control signal according to the control rules shown in (Table 1), and the selection control signal 15 output from the comparator 14 is transferred to the storage destination. By storing 1-bit units in the n-th bit position of the data, the addition, comparison, and selection operation of the cumulative metric of the surviving paths in Viterbi decoding and the storage of the path selection signal can be performed in fewer steps than in the conventional method, making it even smaller. This has the advantage that it can be performed using only a small amount of memory.

Furthermore, by shifting the constant outputted by the constant circuit 3, in which only the least significant bit is 1 and all other bits are 0, the bits necessary for updating the bits of the path selection signal storage destination data are shifted by the barrel shifter 5. Instead of storing bit pattern data (16 bits in case of 16 bit data width) in the instruction word of the processor, the number of shift bits (data width Since it is necessary to hold only 4 bits (in the case of 16 bits), Viterbi decoding processing can be performed using a short instruction word. Furthermore, the barrel shifter 5, inverting circuit 9, arithmetic logic circuit 12, etc., which are the components of this embodiment, are usually installed in advance in digital signal processing processors etc. for numerical calculations, so only a small amount of hardware is required. It also has the effect that an arithmetic device can be realized only by adding hardware.

In the embodiment, the value of the constant circuit 3 is such that only the least significant bit is set to 1 and the other bits are set to 0. However, only the most significant bit may be set to 1 and shifted to the right by the barrel shifter 5. Only bits are 0, other bits are 1
As shown in Table 1, the inversion and non-inversion control of the inversion circuit 9 may be reversed.

[0031]

Effects of the Invention As is clear from the above embodiments, the present invention has a comparator that compares the addition result by the arithmetic means with the addition result temporarily stored in the first register in advance.
A second memory stores the addition result determined by the comparator to be small, and performs an arithmetic and logic operation on the result obtained by shifting the constant output by the constant output means and output by the shifter and the storage destination data of the selection control signal. , the calculation means performs and stores the selection control signal output by the comparator in a predetermined bit position of the storage destination data, so that the addition comparison selection calculation of the cumulative metric of the surviving path in Viterbi decoding and the storage of the path selection signal are performed. This has the advantage that it can be performed with a small number of steps and with a smaller amount of memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an arithmetic device in an embodiment of the present invention.

[Fig. 2] Block diagram showing the schematic configuration of a conventional arithmetic unit

[
FIG. 3 is a diagram showing state transition paths of a convolutional encoder in Viterbi decoding to explain the operation of the arithmetic unit.

[Explanation of symbols]

1 Main memory section (first memory member) 2 Bus 3 Constant circuit 4 Register 5 Barrel shifter 6 Latch circuit 7 Arithmetic control section 8 Control signal 9 Inversion circuit 10 Latch circuit 11 Control signal 12 Arithmetic logic circuit (arithmetic means) 13 Register 14 Comparator 15 Selection control signal 16 Selector

Claims (2)

[Claims] 1. A first memory member for storing data, a calculation means for adding data stored in the first memory member, and a first memory member for temporarily storing the output of the calculation means.
a comparator that compares the output of the first register with the output of the calculation means and outputs a selection control signal; a second memory member that stores the output determined to be smaller; a constant output means that outputs a predetermined constant; a shifter that shifts the output of the constant output means; and a shifter that is necessary for the shift operation of the shifter. shift bit number output means for outputting a shift bit number; and arithmetic control means for controlling the arithmetic mode of the arithmetic means by the selection control signal from the comparator circuit, By controlling the calculation mode by
An arithmetic device that performs addition of data stored in the first memory member and arithmetic and logical operations on the output of the shifter. 2. The constant output means outputs a constant in which a bit at a predetermined bit position is 1 and all other bits are 0, or the complement of this constant, and the shift bit number output means outputs a constant in which a bit at a predetermined bit position is 1 and all other bits are 0, and the shift bit number output means outputs a constant whose bit is 1 at a predetermined bit position and all other bits are 0. 2. The arithmetic device according to claim 1, wherein the number of shift bits required to shift the bit at the bit position of the bit position to the bit position of a destination bit is output to the shifter.