JP3996858B2 - Arithmetic processing unit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an arithmetic processing apparatus incorporated in a mobile communication device or the like, and more particularly to a technique that enables efficient processing of ACS (addition, comparison, selection) operation of Viterbi decoding.
[0002]
[Prior art]
2. Description of the Related Art In recent years, digital signal processors (hereinafter referred to as DSPs) are frequently used as, for example, devices embedded in mobile phones in accordance with the trend of digitization in the mobile communication field. In data communication in a mobile radio communication line, bit errors frequently occur, so it is necessary to perform error correction processing. As an error correction method, there is a method in which a convolutional code generated from input bits is decoded by Viterbi decoding on the receiving side, and a DSP is used for this error correction processing.
[0003]
Viterbi decoding realizes maximum likelihood decoding of a convolutional code by repeating a simple process of addition, comparison, and selection, and finally by a traceback operation for decoding data. The Viterbi decoding process will be briefly described below. A convolutional code is generated by mod2 addition of an input bit and a certain number of bits preceding it, and a plurality of encoded data is generated corresponding to one input bit. The number of input information bits affecting the encoded data is called a constraint length (K), and the number is equal to the number of stages of shift registers used for mod2 addition.
[0004]
This encoded data is determined by the input bits and the state of the preceding (K-1) input bits. This state shifts to a new state when a new information bit is input (transition), but the state that can be transitioned is determined by whether the new input bit is 0 or 1. The number of states is (K-1) because each of these bits can take 1 and 0.^K-1 It becomes a piece.
[0005]
In Viterbi decoding, the received encoded data sequence is observed, and the most probable state is estimated from all possible state transitions. Therefore, every time the encoded data (received data series) corresponding to 1 information bit is obtained, the inter-signal distance (metric) of the path to each state at that time is calculated, and among the paths reaching the same state The operation of leaving the one with a smaller metric as a surviving path is sequentially repeated.
[0006]
FIG. 25 shows a state S [n] and a state S [n + 2] at a previous time point with respect to a state S [2n] (n is a positive integer) at a certain time point in a convolutional encoder with a constraint length K.^K-2 ] Shows a state in which two paths representing state transitions are extended. For example, in the case of K = 3, when n = 1, for S [2], that is, the state of S10 (the state in which the preceding two bits are input in the order of “1” and “0”), S [1 ], That is, a transition from the state of S01 and S [3], that is, the state of S11, and when n = 2, the state of S [4], that is, the state of S00 (the state represented by the lower 2 bits) , S [2], that is, the state of S10, and S [4], that is, the state of S00.
[0007]
The path metric a is an inter-signal distance (branch metric x) between the output symbol of the path input to the state S [2n] and the received data series, and the branch of the surviving path up to the state S [n] at the previous time point. It is the sum with path metric A which is the sum of metrics. Similarly, the path metric b is the distance (branch metric y) between the output symbol of the path input to the state S [2n] and the received data series, and the state S [n + 2 at the previous time point.^K-2 ] With the path metric B, which is the sum of the branch metrics of the surviving paths. The path metrics a and b input to the state S [2n] thus obtained are compared, and the smaller path is selected as the surviving path.
[0008]
In Viterbi decoding, each process of addition, path metric comparison, and path selection for obtaining a path metric is performed at each point in time as described above.^K-1 Execute for each state. Further, in selecting a path, the history of which path has been selected is stored in the path select signal PS [i], [i = 0-2.^K-1 -1] must be left as it is. At this time, the subscript (for example, n) of the state immediately before the selected path is the subscript (n + 2) of the state before the other path that has not been selected.^K-2 ) Is smaller than PS), PS [i] = 0, and larger is PS [i] = 1. In the case of FIG. 25, n <(n + 2^K-2 Therefore, when a> b, the state S [n + 2^K-2 ] Is selected and PS [S2n] = 1, and when a ≦ b, the state S [n] is selected and PS [S2n] = 0. Finally, when decoding by traceback, the data is decoded while tracing back the surviving path based on this path select signal.
[0009]
This ACS arithmetic processing for Viterbi decoding in a conventional DSP will be described by taking TMS320C54x (manufactured by TEXAS INSTRUMENTS, hereinafter referred to as C54x) as a general-purpose arithmetic unit as an example. In the GSM cellular radio system, the following polynomials are used as convolutional codes.
G1 (D) = 1 + D^Three + D^Four , G2 (D) = 1 + D + D^Three + D^Four
[0010]
This convolutional code is represented by a trellis diagram having a butterfly structure shown in FIG. This trellis diagram shows how the convolutional code transitions from one state to another. If the constraint length K is now 5, 2^K-1 = 16 states or 8 butterfly structures exist between each symbol, and two branches are input to each state, and a new path metric is determined by ACS operation.
[0011]
The branch metric is defined by the following formula.
M = SD (2^* i)^* B (J, 0) + SD (2^* i + 1)^* B (J, 1)
Where SD (2^* i) is the first symbol of the symbol metric representing the soft decision input, and SD (2^* i + 1) is the second symbol of the symbol metric. B (J, 0) and B (J, 1) match the codes generated by the convolutional encoder shown in FIG.
[0012]
In C54x, the butterfly structure is processed at high speed by setting the ALU to dual 16-bit mode. To determine the new path metric (J), use the DADST instruction to^* J and 2^* Two path metrics of J + 1 and branch metrics (M and -M) are calculated in parallel, and comparison is performed using a CMPS instruction. To determine a new path metric (J + 8), two path metrics and a branch metric (M and -M) are calculated in parallel with the DSADT instruction. The calculation results are stored in the upper and lower positions of the double precision accumulator, respectively. A new path metric is determined by the CMPS instruction.
[0013]
The CMPS instruction compares the upper and lower accumulators and stores the larger one in the memory. In addition, it is updated each time a comparison is made so that it can be traced back later which is selected in the 16-bit transition register (TRN). The contents of TRN are stored in the memory after each symbol process. Information stored in the memory is used to search for the optimum path during the traceback process. FIG. 28 shows a macro program for butterfly calculation of Viterbi decoding. The value of the branch metric is stored in the T register before the macro is called. FIG. 29 shows an example of path metric memory mapping.
[0014]
In one symbol interval, 8 butterfly operations are performed, and 16 new states are obtained. This series of processing is repeatedly calculated over several symbol intervals, and when the processing is completed, traceback is performed next, the optimum path is searched from 16 paths, and a decoded bit sequence is obtained.
[0015]
The above is the mechanism of ACS operation of C54x, which is a general-purpose DSP. From the example of the macro program in FIG. 28, C54x implements updating of two path metrics in 4 machine cycles.
[0016]
[Problems to be solved by the invention]
In the future, demand for non-voice communication such as data transmission by mobile radio communication is expected to increase more and more, and non-voice communication has a lower bit error rate (hereinafter referred to as this). High transmission quality (referred to as BER) is demanded. One means for achieving a low BER is to increase the constraint length K of Viterbi decoding used as error correction. When the constraint length is increased by one, the number of path metrics (number of states) is doubled, so that the amount of computation in Viterbi decoding is doubled. In general, non-voice communication has a larger amount of information than voice communication, and the larger the amount of information, the more the processing amount (ACS calculation, etc.) required for Viterbi decoding.
[0017]
On the other hand, in mobile radio communication and the like, it is desired to maintain the battery life of the portable terminal for a long time. At the same time, miniaturization, weight reduction, and price reduction of portable terminals are also desired. For this reason, in a portable terminal, an area conventionally processed by a dedicated LSI is also made into one chip by DSP processing. The smaller the DSP throughput, the longer the battery can last.
[0018]
However, as described above, the amount of computation by the DSP tends to increase in the future, and there is a problem that it is difficult to sustain the battery of the mobile terminal for a long time. Further, if the amount of calculation increases, there is a problem that the processing capacity of the existing DSP is no longer exceeded, and it cannot be realized with one chip by the DSP. Furthermore, in order to increase the functionality of the DSP, a large-scale hardware investment causes an increase in the cost of the DSP itself, resulting in a problem that the price of the portable terminal cannot be reduced.
[0019]
The present invention solves such a conventional problem, and an object of the present invention is to provide an arithmetic processing unit that efficiently processes Viterbi decoding processing by a DSP, particularly ACS arithmetic, with as little hardware investment as possible. And
[0020]
[Means for Solving the Problems]
  An arithmetic processing apparatus of the present invention is an arithmetic processing apparatus capable of Viterbi decoding by a digital signal processor, wherein first comparison means for comparing first data with second data, third data, Second comparing means for comparing with the fourth data, the first comparing means and the second comparing means.By one instruction andIt is configured to operate in one cycle.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 shows the configuration of the arithmetic processing apparatus according to the first embodiment. In FIG. 1, 1 is a storage means for storing a path metric, 2 is a bus connected to the storage means 1 for supplying data and transferring operation results, 3 is a storage means for storing branch metrics, and 4 is a storage means 3 And 5 and 9 are comparison means for comparing data read from the storage means 1 and 3 via the buses 2 and 4, respectively, and 6 and 10 are storage means 1 and 3. Adding means for adding the data read from the buses 2 and 4 respectively, 7 is a storage means for storing the comparison result of the comparison means 5, 11 is a storage means for storing the comparison result of the comparison means 9, 8 Is a selection unit that inputs the addition result of the addition unit 6 and determines an output based on the comparison result of the comparison unit 5, and 12 is an input of the addition result of the addition unit 10, and is based on the comparison result of the comparison unit 9 Selection means for determining the force 13 enter the selection result of the selection means 8 and 12, a bus for transferring the storage means 1. The storage means 7 and 11 for storing the comparison results are both connected to the bus 2 and can transfer the comparison results to the storage means 1 via the bus 2.
[0030]
Next, the operation in this embodiment will be described with reference to FIGS. In the following description, the case where the constraint length K is 4 and the coding rate is 1/2 is considered. Both path metric and branch metric data types are single precision data. In the following description, for the sake of convenience, when the double precision data is (X, Y), X represents the upper side of the double precision data, and Y represents the lower side of the double precision data.
[0031]
Considering the convolutional encoder of FIG. 2 as an example, the four branch metrics when the coding rate is ½ are BM0, BM1, BM2, and BM3, respectively. Using these branch metrics, the transition state of the state (State) when the constraint length K = 4 is illustrated, and a butterfly structure as shown in FIG. 3 is obtained. Here, attention is paid to the node N0 and the node N1 in the old state (Old State). The node N0 and the node N1 transition at the node N′0 and the node N′4.
The branch metric (BM) taken at that time is
BM0 when node N0 to node N'0
BM1 when node N1 to node N'0
BM1 when node N0 to node N'4
BM0 when node N1 to node N'4
It is. Also, assuming that the path metric of the node N0 is PM0 and the path metric of the node N1 is PM1, the node metrics N0, N1 are exchanged by adding the branch metrics BM0, BM1 to the common path metrics PM0, PM1, respectively. It can be seen that it can be a '4 path metric. Using this relationship, two path metrics can be updated simultaneously by performing parallel processing.
[0032]
As shown in FIG. 3, this relationship also holds for subsequent node pairs (in the figure, a pair of node N2 and node N3, a pair of node N4 and node N5, and a pair of node N6 and node N7). Therefore, as shown in FIG. 3, the ACS calculation of the first half nodes N′0 to N′3 is processed by the comparison means 5, the addition means 6, the storage means 7 for storing the comparison results, and the selection means 8, and the latter half. The ACS operation of the nodes N′4 to N′7 is processed by the comparison means 9, the addition means 10, the storage means 11 for storing the comparison results, and the selection means 12.
[0033]
Hereinafter, detailed operations will be described regarding the ACS operation from the node N0 and the node N1 to the node N′0 and the node N′4. First, two path metrics are output from the storage unit 1 as (PM1, PM0) to the bus 2, while two branch metrics are output from the storage unit 3 to the bus 4 as (BM1, BM0). In the comparison means 5, two path metrics (PM1, PM0) are input from the bus 2, two branch metrics (BM1, BM0) are input from the bus 4,
PM1 + BM1-PM0-BM0
Calculate On the other hand, the adding means 6 inputs two path metrics (PM1, PM0) from the bus 2, and inputs two branch metrics (BM1, BM0) from the bus 4.
PM1 + BM1 and PM0 + BM0
Is output to the selection means 8 as (PM1 + BM1, PM0 + BM0).
[0034]
The selection means 8 inputs the most significant bit (hereinafter referred to as MSB: Most Significant Bit) which is the sign bit of the comparison result PM1 + BM1−PM0−BM0 of the comparison means 5 and outputs the higher order PM1 + BM1 according to the MSB value. , Select whether to output the lower PM0 + BM0.
That is,
PM1 + BM1 ≧ PM0−BM0
Then, PM1 + BM1-PM0-BM0 ≧ 0
Therefore, the MSB becomes 0. At this time, the lower PM0 + BM0 is selected, and this is newly output to the bus 13 as PM'0.
vice versa,
PM1 + BM1 <PM0-BM0
Then, PM1 + BM1-PM0-BM0 <0
Therefore, the MSB becomes 1, and at this time, the upper PM1 + BM1 is selected, and this is newly output to the bus 13 as PM'0. Further, the MSB of the comparison result of the comparison means 5 is sequentially stored in the storage means 7 at the same time.
[0035]
In the comparison means 9, two path metrics (PM1, PM0) are input from the bus 2, and two branch metrics (BM1, BM0) are input from the bus 4.
PM1 + BM0-PM0-BM1
Calculate On the other hand, in the adding means 10, two path metrics (PM1, PM0) are input from the bus 2, and two branch metrics (BM1, BM 0) are input from the bus 4.
PM1 + BM0 and PM0 + BM1
Is output to the selection means 12 as (PM1 + BM0, PM0 + BM1).
[0036]
The selection unit 12 inputs the MSB of the comparison result PM1 + BM0−PM0−BM1 of the comparison unit 9, and selects whether to output the upper PM1 + BM0 or the lower PM0 + BM1 depending on the value of the MSB.
That is,
PM1 + BM0 ≧ PM0-BM1
Then, PM1 + BM0-PM0-BM1 ≧ 0
Therefore, the MSB becomes 0. At this time, the lower PM0 + BM1 is selected, and this is newly output to the bus 13 as PM'4.
vice versa,
PM1 + BM0 <PM0-BM1
Then, PM1 + BM0-PM0-BM1 <0
Therefore, the MSB becomes 1, and at this time, the upper PM1 + BM0 is selected, and this is newly output to the bus 13 as PM'4.
Further, the MSB of the comparison result of the comparison unit 9 is sequentially stored in the storage unit 11 at the same time.
[0037]
As described above, it is possible to execute the ACS operation of the Viterbi decoding by the DSP in parallel by performing the same processing for the other node pairs. In the above description, a specific example in the case of the constraint length K = 4 and the coding rate 1/2 has been shown. However, even if the values of the constraint length and the coding rate are other values, the above relationship Therefore, it can be similarly implemented by making appropriate changes accordingly.
[0038]
(Embodiment 2)
FIG. 4 shows the configuration of the arithmetic processing apparatus according to the second embodiment. The arithmetic processing unit of the present embodiment is different from the arithmetic processing unit of the first embodiment (FIG. 1) in that the arithmetic processing unit is composed of four banks of RAM 14 as storage means for storing path metrics. Other configurations and operations are the same as those in the first embodiment.
[0039]
The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG. For example, in order to execute the ACS operation in the operation execution stage of the (n + 1) th cycle in the instruction 1, it is necessary to supply the RAM 14 with a path metric address read in advance in the memory access stage of the nth cycle. At this time, assuming that the RAM 14 can continuously read even addresses and odd addresses, that is, a RAM capable of double-precision reading, the two path metrics used for calculation can be used simply by specifying even addresses in the following situations. Can be read out.
・ One-state path metrics are stored in consecutive addresses in the order of even and odd addresses.
-One-state path metrics are divided into the first half and the second half, and stored in separate banks.
[0040]
The four-bank RAM 14 stores, for example, the first-half path metrics of the old state in bank 0 (referring to PM0, PM1, PM2, and PM3 in FIG. 3). 3 indicates PM4, PM5, PM6, and PM7), two path metrics are generated by one cycle of operation execution (ACS operation execution), and these are respectively sent to bank 2, Stored in bank 3. At this time, the bus 13 transfers double precision data, the path metrics from the nodes N′0 to N′3 are stored in the bank 2, and the path metrics from the node N ′ to the node N′7 are stored in the bank 3. Is done.
[0041]
FIG. 6 shows an example of memory access operation corresponding to FIG. When the one-state ACS operation is completed, in the next state, the path metric of the old state is read from the banks 2 and 3, and the path metric of the new state is stored in the banks 0 and 1. By switching between the bank pair for reading the path metric and the bank pair to be stored every time one-state ACS operation is completed using the four banks of RAM 14 as described above, the Viterbi decoding ACS operation by the DSP is executed in parallel. It becomes possible.
[0042]
In the above description, bank 0 and bank 1 and bank 2 and bank 3 have been described as an example of a pair of banks. However, even when other combinations are used, addresses supplied at the memory access stage are stored. It can be similarly implemented only by changing the address. In the present embodiment, the RAM 14 is composed of four banks. However, the number of banks is a minimum required number, and can be similarly implemented if the number is four or more.
[0043]
(Embodiment 3)
FIG. 7 shows the configuration of the arithmetic processing apparatus according to the third embodiment. The difference between the arithmetic processing unit of the present embodiment and the arithmetic processing unit of the first embodiment (FIG. 1) is that it is composed of a dual-port RAM 15 consisting of three banks as storage means for storing path metrics. Other configurations and operations are the same as those in the first embodiment.
[0044]
The arithmetic processing apparatus of this embodiment is also suitable for the arithmetic processing of the pipeline structure shown in FIG. Since the storage means for storing the path metric is the dual port RAM 15, it is possible to specify reading and writing to the same bank in one instruction. For example, in the instruction 1, the ACS operation is executed at the operation execution stage of the (n + 1) th cycle. Therefore, first, the address of the path metric to be read and the address of the path metric to be written are supplied to the dual port RAM 15 in the memory access stage of the nth cycle, and from the dual port RAM 15 in the same way as the RAM 14 of the second embodiment in the n + 1th cycle. It is possible to read even and odd addresses in succession, perform ACS operation, and write one path metric to the same bank.
[0045]
The arithmetic processing apparatus according to the third embodiment also operates under the following conditions, like the arithmetic processing apparatus according to the second embodiment.
・ One-state path metrics are stored in consecutive addresses in the order of even and odd addresses.
-One-state path metrics are divided into the first half and the second half, and stored in separate banks.
[0046]
The dual port RAM 15 stores, for example, the path metric of the first half of the old state in bank 0 (referring to PM0, PM1, PM2, PM3 in FIG. 3), and the path metric of the second half of the old state stored in bank 1 (FIG. 3). , PM4, PM5, PM6, and PM7) are stored, two path metrics are generated by one cycle of operation execution (ACS operation execution). 2 is stored. At this time, the bus 13 transfers double precision data, the path metrics from the nodes N′0 to N′3 are stored in the bank 0, and the path metrics from the nodes N′4 to N′7 are stored in the bank 2. Stored.
[0047]
FIG. 8 shows an example of memory access operation corresponding to FIG. The arithmetic processing unit of the present embodiment is different from the arithmetic processing unit of the second embodiment in that when the one-state ACS calculation is completed, only the bank 1 and the bank 2 are switched, and the bank 0 is not switched. This is that the ACS operation of the Viterbi decoding by the DSP can be executed in parallel. In the present embodiment, the dual port RAM 15 is composed of three banks. However, the number of banks is a minimum required number, and can be similarly implemented if the number is three or more.
[0048]
(Embodiment 4)
FIG. 9 shows the configuration of the arithmetic processing apparatus according to the fourth embodiment. The arithmetic processing unit of the present embodiment is different from the arithmetic processing unit of the second embodiment (FIG. 4) in that it includes input registers 16 and 17, and other configurations and operations are the same as those of the first embodiment. It is exactly the same as 2. In FIG. 9, the input registers 16 and 17 receive data from the bus 2 and output the data to the comparison means 5 and 9 and the addition means 6 and 10.
[0049]
The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG. For example, in order to execute the ACS operation in the operation execution stage of the n + 2 cycle in the instruction 1, the path metric address read in the memory access stage of the n cycle is supplied to the RAM 14 in advance, and in the data transfer stage of the n + 1 cycle. Data output from the RAM 14 is latched in the input registers 16 and 17 via the bus 2.
[0050]
In the pipeline shown in FIG. 10, one stage of data transfer is inserted before the operation execution stage in the stage of the pipeline shown in FIG. That is, at the beginning of the operation execution stage, the data from the RAM 14 is determined by the input register before each operation unit (referring to the comparison means 5 and 9 and the addition means 6 and 10). It is possible to save the time required for.
[0051]
Therefore, according to the present embodiment, it is possible to execute the ACS operation of Viterbi decoding by the DSP in parallel at a relatively high speed. Note that the present invention can be similarly implemented even if a dual port RAM is used as means for storing the path metric.
[0052]
(Embodiment 5)
FIG. 11 shows the configuration of the arithmetic processing unit according to the fifth embodiment. The arithmetic processing unit of the present embodiment is different from the arithmetic processing unit of the fourth embodiment (FIG. 9) in that it includes a swap circuit 18, and other configurations and operations are the same as those of the fourth embodiment. Exactly the same. In FIG. 11, the swap circuit 18 inputs data from the storage means 3 that stores the branch metrics and outputs the data to the bus 4.
[0053]
The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG. The swap circuit 18 outputs the values of two branch metrics inputted as double precision data in the form of {BM1, BM0} from the storage means 3 as {BM1, BM0} as they are, or swaps the upper and lower levels. And {BM0, BM1} to be output by an instruction or the like.
[0054]
The operation of the swap circuit 18 will be described. The constraint length K = 4 and the coding rate 1/2 will be described using the transition state of the path metric of the convolutional encoder shown in FIG. 2 and the butterfly structure shown in FIG. An ACS operation when transitioning from the node N0 and the node N1 in the old state to the node N'0 and the node N'4, and from the node N6 and the node N7 in the old state (node N'3) FIG. 12 is a comparison of the ACS operation when transitioning to the node N′7. That is, the ACS operation from the node N0 and the node N1 to the node N′0 and the ACS operation from the node N6 and the node N7 to the node N′3 are performed by the comparison unit 5 and the addition unit 6, but both ACS operations are common. The branch metrics BM0 and BM1 are used, and BM0 and BM1 are swapped. The same relationship holds in the comparing means 9 and the adding means 10 of the ACS operation from the node N0 and the node N1 to the node N'4 and the ACS operation from the node N6 and the node N7 to the node N'7. For this reason, the storage means 3 for storing branch metrics must be stored in both {BM0, BM1} and {BM1, BM0} forms, resulting in redundant hardware resources.
[0055]
The swap circuit 18 solves such redundancy. The storage means 3 for storing branch metrics stores only the form {BM0, BM1}, for example, and the swap circuit 18 stores this { BM0, BM1} is input and, for example, an instruction or the like is used to switch between {BM0, BM1} and {BM1, BM0} as an output, and the branch metric is stored by this swap circuit 18 Therefore, it is possible to omit the redundancy of the storage means 3 to be performed.
[0056]
In this embodiment, the description has been given using the node N0, the node N1, the node N6, and the node N7 in the old state with the constraint length K = 4 and the coding rate 1/2, but the node N2, the node N3 The above relationship is also established in the node N4 and the node N5, and further, a combination of the constraint length K and the coding rate other than the above is also established. Further, the present invention can be similarly implemented by using a dual port RAM as means for storing the path metric.
[0057]
(Embodiment 6)
FIG. 13 shows the configuration of the arithmetic processing apparatus according to the sixth embodiment. The arithmetic processing apparatus of the present embodiment is different from the arithmetic processing apparatus of the fifth embodiment (FIG. 11) in that it comprises two adders and one comparator as comparison means, and two adders as addition means. The other configurations and operations are the same as those in the fifth embodiment.
[0058]
In FIG. 13, reference numerals 19 and 20 denote adders for inputting and adding data from the bus 4 and the input register 16, and reference numeral 21 denotes a storage means for inputting and comparing the addition results from the adder 19 and the adder 20 and storing the comparison results. 7 and a comparator for outputting to the selecting means 8, 22 and 23 are input by adding data from the bus 4 and the input register 16, and an adder for outputting the addition result to the selecting means 8, and 24 and 25 are inputs to the bus 4. An adder for inputting and adding data from the register 17; and 26, a comparator for inputting and comparing the addition results from the adder 24 and the adder 25, and outputting the comparison results to the storage means 11 and the selecting means 12, 27 Reference numerals 28 and 28 denote adders which input data from the bus 4 and the input register 17 and add them, and output the addition result to the selection means 12. The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG.
[0059]
Next, the ACS calculation operation in this embodiment will be described. Assuming that the constraint length K = 4 and the coding rate 1/2, the convolutional encoder shown in FIG. 2, the butterfly structure shown in FIG. 3, and the nodes N0 and N1 shown in FIG. A description will be given by comparing the ACS operation and the ACS operation from the nodes N6 and N7 to the nodes N′3 and N′7.
[0060]
As shown in FIG. 13, when the two path metrics are output as {A, B} from the input registers 16 and 17 and the two branch metrics are output as {C, D} from the swap circuit 18, the adder 19 Then, the path metric {A} and the branch metric {C} are input and the addition result {A + C} is output. The adder 20 inputs the path metric {B} and the branch metric {D}, and the addition result {B + D }, And the comparator 21 inputs the addition result {A + C} of the adder 19 and the addition result {B + D} of the adder 20, compares {A + C− (B + D)}, and compares the MSB of the comparison result Is output. The adder 22 inputs the path metric {A} and the branch metric {C} and outputs the addition result {A + C}. The adder 23 inputs the path metric {B} and the branch metric {D}, and the addition result. {B + D} is output.
[0061]
On the other hand, the adder 24 inputs the path metric {A} and the branch metric {D} and outputs the addition result {A + D}, and the adder 25 inputs the path metric {B} and the branch metric {C}. , The addition result {B + C} is output, and the comparator 26 inputs the addition result {A + D} of the adder 24 and the addition result {B + C} of the adder 25, and compares {A + D− (B + C)}. The MSB of the comparison result is output. The adder 27 inputs the path metric {A} and the branch metric {D} and outputs the addition result {A + D}. The adder 28 inputs the path metric {B} and the branch metric {C} and adds them. The result {B + C} is output.
[0062]
With the above configuration and operation, if two path metrics {A, B} = {PM1, PM0} of the input register 16 and the input register 17 are set, and the output {C, D} = {BM1, BM0} of the swap circuit 18 is set. The ACS operation when transitioning from the node N0 and the node N1 in the old state shown in FIG. 12 to the node N′0 and the node N′4 can be realized.
[0063]
Further, when two path metrics {A, B} = {PM1, PM0} of the input register 16 and the input register 17 are set and the output {C, D} = {BM0, BM1} of the swap circuit 18 is shown in FIG. It is possible to realize an ACS operation when transitioning from the node N0 and the node N1 in the old state to the node N′0 and the node N′4.
[0064]
Therefore, according to the present embodiment, the update of two path metrics can be realized in one machine cycle by the pipeline operation by the DSP. In this embodiment, the description has been given using the node N0, the node N1, the node N6, and the node N7 in the old state with the constraint length K = 4 and the coding rate 1/2, but the node N2, the node N3 The above relationship is also established in the node N4 and the node N5, and further, a combination of the constraint length K and the coding rate other than the above is also established. Further, the present invention can be similarly implemented by using a dual port RAM as means for storing the path metric.
[0065]
(Embodiment 7)
FIG. 14 shows the configuration of the arithmetic processing apparatus according to the seventh embodiment. The difference between the arithmetic processing unit of the present embodiment and the arithmetic processing unit of the sixth embodiment (FIG. 13) is that one of the comparators is shared by the ALU 29, and the input registers 30, 31 are accordingly associated. And other buses 32, 33, 37, and 38, selectors 34 and 35, and a register file 36 as a storage means for storing branch metrics. This is exactly the same as Form 6.
[0066]
In FIG. 14, 30 is an input register for inputting data from the RAM 14 consisting of 4 banks via the bus 37, 31 is an input register for inputting data from the RAM 14 consisting of 4 banks via the bus 38, and 32 and the bus 33 are registers. A bus for inputting data from the file 36, a selector 34 for inputting data from the bus 32, the adder 19 and the input register 30 and selecting an output, and 35 for inputting data from the bus 33, the adder 20 and the input register 31. , A selector for selecting an output, 29 receives data from the selectors 34 and 35, performs arithmetic logic operation, outputs an arithmetic logic operation result to the bus 13, and further stores the MSB of the arithmetic logic operation result as a comparison result An ALU output to the means 7 and the selection means 8. The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG.
[0067]
In the present embodiment, when performing the ACS operation, the selector 34 selects the output of the adder 19 and inputs it to the ALU 29, the selector 35 selects the output of the adder 20 and inputs it to the ALU 29, and the ALU 29 inputs The two data are subtracted, and the MSB of the subtraction result is output to the storage means 7 for storing the comparison result and the selection means 8.
[0068]
In addition, when the ALU performs arithmetic logic operation between the register and the register, data is output from the register file 36 to the bus 32 and the bus 33, and the selector 34 and the selector 35 select the bus 32 and the bus 33, respectively. It is feasible. When the ALU performs an arithmetic logic operation between the register and the memory, data is output from the register file 36 to the bus 32, and data is input from the RAM 14 having four banks to the input register 31 via the bus 38. This can be realized by the selector 35 selecting the bus 32 and the input register 31, respectively.
[0069]
Conversely, when the ALU performs an arithmetic logic operation between the memory and the register, data is input from the RAM 14 consisting of four banks to the input register 30 via the bus 37, and data is output from the register file 36 to the bus 33. This can be realized by the selector 34 and the selector 35 selecting the input register 30 and the bus 33, respectively.
[0070]
In addition, when the ALU performs an arithmetic logic operation between the memory and the memory, data is input to the input register 30 and the input register 31 from the RAM 14 having four banks via the bus 37 and the bus 38, and the selector 34 and the selector 34 are selected. 35 can be realized by selecting the input register 30 and the input register 31, respectively.
[0071]
As described above, according to the present embodiment, one of the comparators that perform the ACS operation is also used as the ALU, so that the chip area can be reduced and the cost can be reduced when the arithmetic processing unit is implemented as an LSI. be able to. Note that the present invention can be similarly implemented even if a dual port RAM is used as means for storing the path metric.
[0072]
(Embodiment 8)
FIG. 15 shows a configuration of an arithmetic processing apparatus according to the eighth embodiment. The difference between the arithmetic processing unit of the present embodiment and the arithmetic processing unit of the seventh embodiment (FIG. 14) is that two adders used as comparison means are realized by 4: 2 COMPRESOR 39 and 40. Other configurations and operations are the same as those in the seventh embodiment.
[0073]
In FIG. 15, 39 is a data input from the bus 4 and the input register 16, and 4: 2COMPRESSOR outputs the operation result to the selector 34 and the selector 35, and 40 is a data input from the bus 4 and the input register 17 to the comparator 26. 4: 2COMPRESSOR that outputs the calculation result. The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG.
[0074]
Next, the ACS calculation operation in this embodiment will be described. Assuming that the constraint length K = 4 and the coding rate 1/2, the convolutional encoder shown in FIG. 2, the butterfly structure shown in FIG. 3, and the nodes N0 and N1 shown in FIG. A description will be given by comparing the ACS operation and the ACS operation from the nodes N6 and N7 to the nodes N′3 and N′7.
[0075]
First, the 4: 2COMPRESSORs 39, 40 are connected in series with a single block for the number of single-precision bits for performing the processing shown in FIG. 16, and perform addition processing faster than a normal full adder.
[0076]
As shown in FIG. 15, when two path metrics are output as {A, B} from the input registers 16 and 17, and two branch metrics are output as {C, D} from the swap circuit 18, 4: 2COMPRESSOR39 Then, the path metric {A}, the branch metric {C}, the inversion {｝ B} of the path metric {B}, and the inversion {￣D} of the branch metric {D} are input. In the ALU 29, the selectors 34 and 35 are used. Then, the two outputs of 4: 2COMPRESSOR39 are input and added. However, at this time, in order to realize the two's complement of {B} and {D}, “1” is input to the 4: 2COMPRESSOR 39 and the lowest carry input of the ALU 29. As a result, {A + C- (B + D)} is obtained, and the MSB is output. The adder 22 inputs the path metric {A} and the branch metric {C} and outputs the addition result {A + C}. The adder 23 inputs the path metric {B} and the branch metric {D} and adds the result { B + D} is output.
[0077]
On the other hand, in 4: 2COMPRESSOR 40, path metric {A}, branch metric {D}, inversion {￣B} of path metric {B}, and inversion {￣C} of branch metric {C} are input to comparator 26. Inputs and adds the two outputs of 4: 2COMPRESSOR39. However, at this time, in order to realize the two's complement of {B} and {C}, “1” is input to the 4: 2COMPRESSOR 40 and the lowest carry input of the comparator 26. As a result, {A + D- (B + C)} is obtained, and the MSB is output. The adder 27 inputs the path metric {A} and the branch metric {D} and outputs the addition result {A + D}. The adder 28 inputs the path metric {B} and the branch metric {C} and adds them. The result {B + C} is output.
[0078]
With the above configuration and operation, if two path metrics {A, B} = {PM1, PM0} of the input register 16 and the input register 17 are set, and the output {C, D} = {BM1, BM0} of the swap circuit 18 is set. The ACS operation when transitioning from the node N0 and the node N1 in the old state shown in FIG. 12 to the node N′0 and the node N′4 can be realized.
[0079]
Further, when two path metrics {A, B} = {PM1, PM0} of the input register 16 and the input register 17 are set and the output {C, D} = {BM0, BM1} of the swap circuit 18 is shown in FIG. It is possible to realize an ACS operation when transitioning from the node N0 and the node N1 in the old state to the node N′0 and the node N′4. Therefore, the update of two path metrics can be realized in one machine cycle by the pipeline operation by the DSP.
[0080]
In this way, according to the present embodiment, by applying 4: 2COMPRESSOR to the comparison means for performing the ACS operation, it is possible to perform the operation at a higher speed than when configured with two adders. Can be realized. In the example, the description has been given using the node N0, the node N1, the node N6, and the node N7 in the old state with the constraint length K = 4 and the coding rate 1/2. However, the node N2, the node N3, the node N4, Since the above relationship is also established at the node N5, and the combination of the constraint length K and the coding rate other than the above is also established, it can be similarly implemented. Further, the present invention can be similarly implemented by using a dual port RAM as means for storing the path metric.
[0081]
(Embodiment 9)
FIG. 17 shows the configuration of the arithmetic processing apparatus according to the ninth embodiment. The arithmetic processing apparatus of the present embodiment is different from the arithmetic processing apparatus of the eighth embodiment (FIG. 15) in that a double precision adder is used as the adding means, and at least one of them is also used as a double precision AU. Other configurations and operations are the same as those in the eighth embodiment.
[0082]
In FIG. 17, 41 is input double precision format data from the input register 16 and the bus 4, double precision AU for performing double precision arithmetic operation, 42 is input double precision format data from the input register 17 and the bus 4, The double precision adder performs a double precision addition operation. The output of the double precision AU 41 is output to the selection means 8 and the bus 13, and the output of the double precision adder 42 is output to the selection means 12. The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG.
[0083]
When performing an ACS operation in the present embodiment, the double precision AU 41 inputs two path metrics from the input register 16 in the double precision format as {A, B}, and 2 from the swap circuit 18 via the bus 4. Two branch metrics are entered as {C, D} in double precision format. At this time, the double precision AU 41 performs double precision addition, but as shown in FIG. 18, the carry from the bit position of the single precision MSB to the next stage is forced to zero. Thereby, the addition {A + C, B + D} of the two path metrics and the branch metrics can be performed in parallel at the same time.
[0084]
On the other hand, the double precision adder 42 inputs the two path metrics from the input register 17 in the double precision format as {A, B}, and the two branch metrics from the swap circuit 18 via the bus 4 in the double precision format. Input as {D, C}. Similarly to the double precision AU 41, the double precision adder 42 forces the carry from the bit position of the single precision MSB to the next stage to zero and simultaneously adds the two path metrics and branch metrics {A + D, B + C}. Operate in parallel.
[0085]
In this way, according to the present embodiment, the double precision AU41 is used as the adding means for performing the ACS calculation, and the carry from the bit position of the single precision MSB to the next stage is forced to zero during the ACS calculation. In double precision arithmetic operations other than the above, by adding control for propagating the carry, it can be used, for example, as a double precision cumulative adder at the time of product-sum operation. The cost can be reduced by further reducing the area. Note that the present invention can be similarly implemented even if a dual port RAM is used as means for storing the path metric.
[0086]
(Embodiment 10)
FIG. 19 shows the configuration of the arithmetic processing apparatus according to the tenth embodiment. The difference between the arithmetic processing unit of the present embodiment and the arithmetic processing unit of the ninth embodiment (FIG. 17) is that a shift register is used as the storage means for storing the comparison result. The operation is exactly the same as in the ninth embodiment.
[0087]
In FIG. 19, 43 is a shift register that receives the MSB of the calculation result of the ALU 29, 44 is a shift register that receives the MSB of the calculation result of the comparator 26, and both the shift registers 43 and 44 are connected to the bus 2. Data can be output. The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG.
[0088]
In the present embodiment, when the ACS operation is performed, the MSB of the comparison result by the ALU 29 is shifted into the shift register 43 as needed, and the MSB of the comparison result from the comparator 26 is shifted into the shift register 44 as needed. A signal (a signal indicating which of the two paths has been selected and used when tracing back after the ACS operation is completed) can be stored. Further, when the bit width of the shift registers 43 and 44 is, for example, a single precision data width, when the ACS operation is performed several times with single precision bits, the values of the shift registers 43 and 44 are transferred via the bus 2. It is necessary to store the path select signal in the RAM 14 having four banks.
[0089]
Thus, according to the present embodiment, by using the shift registers 43 and 44 as the storage means for storing the comparison result for performing the ACS operation, it can also be used as, for example, an operation instruction using a division shift register. In the case where the arithmetic processing unit is made into an LSI, the chip area can be further reduced to reduce the cost. Note that the present invention can be similarly implemented even if a dual port RAM is used as means for storing the path metric.
[0090]
(Embodiment 11)
FIG. 20 shows the configuration of the arithmetic processing apparatus according to the eleventh embodiment. The arithmetic processing unit of the present embodiment is different from the arithmetic processing unit of the tenth embodiment (FIG. 19) in that the input register 17 always swaps and inputs path metric data from the bus 2 to the 4: 2 COMPRESOR 40. Is that the branch metric data from the swap circuit 18 is input as it is without swapping, and the negated value of the comparison result of the comparator 26 is shifted into the shift register 44. Other configurations and operations are the same as those of the tenth embodiment. Exactly the same. The arithmetic processing apparatus of this embodiment is suitable for the arithmetic processing of the pipeline structure shown in FIG.
[0091]
When performing an ACS operation in the present embodiment, two path metrics {A, B} are directly input to the input register 16 as {A, B}, but the input register 17 is always swapped { B, A}. Thereafter, in the 4: 2COMPRESSOR 40, the two branch metrics are input from the swap circuit 18 as {C} and {￣D}, and the two path metrics are input from the input register 17 as {B} and {￣A}. Then, the two outputs of 4: 2COMPRESSOR40 are input and added, and {A + D−B−C} is calculated. On the other hand, the double precision adder 42 receives two branch metrics as {C, D} from the swap circuit 18 and two path metrics as {B, A} from the input register, and {B + C} and {A + D}. Simultaneously calculate in parallel and output to the selection means 12 in the form of {B + C, A + D}. The comparator 26 outputs the MSB of the comparison result to the selection unit 12 and the MSB of the negation value of the comparison result to the shift register 44.
[0092]
In this way, according to the present embodiment, one of the input registers for storing two path metrics is swapped and input, so that the 4: 2 COMPRESOR 40 and the double precision adder 42 are connected in the operation execution (EX) stage. There is no swapping at the input, and it is possible to perform a faster ACS operation. Note that the present invention can be similarly implemented even if a dual port RAM is used as means for storing the path metric.
[0093]
(Embodiment 12)
FIG. 21 shows the configuration of the mobile station apparatus in the twelfth embodiment. In FIG. 21, a mobile station apparatus 45 in the present embodiment performs a transmission / reception antenna unit 46, a radio unit 47 including a reception unit 48 and a transmission unit 49, and modulation and demodulation of signals, encoding and decoding. Baseband signal processing unit 50 for performing, speaker 58 for emitting sound, microphone 59 for inputting sound, data input / output unit 60 for inputting / outputting data to be transmitted / received to / from an external device, and operation status display And a control unit 63 for controlling the antenna unit 46, the radio unit 47, the baseband signal processing unit 50, the display unit 61, the operation unit 62, and the like.
[0094]
The baseband signal processing unit 50 includes a demodulation unit 51 that demodulates a reception signal, a modulation unit 52 that modulates a transmission signal, and a one-chip DSP 53. The DSP 53 includes the first to eleventh embodiments. A Viterbi decoding unit 55 comprising a form of arithmetic processing unit, a convolutional encoding unit 56 for performing convolutional encoding of a transmission signal, an audio codec unit 57 for encoding / decoding an audio signal, and a reception signal by measuring transmission / reception timing A timing control unit 54 that sends a transmission signal from the convolutional coding unit 56 to the modulation unit 52 is formed by software from the demodulation unit 51 to the Viterbi decoding unit 55, respectively.
[0095]
The control unit 63 of the mobile station device 45 controls the operation of the entire mobile station device 45, for example, displays a signal input from the operation unit 62 on the display unit 61 or receives a signal input from the operation unit 62. A control signal for performing an incoming / outgoing call operation is output to the antenna unit 46, the radio unit 47, the baseband signal processing unit 50, and the like according to the communication sequence.
[0096]
When voice is transmitted from the mobile station device 45, the voice signal input from the microphone 59 is AD converted (not shown), encoded by the voice codec unit 57 of the DSP 53, and the encoded data is convolutionally encoded. 56. When data is transmitted, data input from the outside is input to the convolutional encoding unit 56 via the data input / output unit 60. The convolutional coding unit 56 performs convolutional coding on the input data and outputs the data to the timing control unit 54. The timing control unit 54 rearranges input data and adjusts transmission output timing, and outputs the result to the modulation unit 52. The data input to the modulation unit 52 is digitally modulated, D / A converted (not shown), and output to the transmission unit 49 of the radio unit 47. The transmission part 49 converts this into a radio signal, sends it to the antenna part 46, and is transmitted as a radio wave from the antenna.
[0097]
On the other hand, at the time of reception, the radio wave received by the antenna unit 46 is received by the receiving unit 48 of the radio unit 47, AD converted, and output to the demodulating unit 51 of the baseband signal processing unit 50. The data demodulated by the demodulator 51 is rearranged by the timing controller 54 and then input to the Viterbi decoder 55 where it is decoded. The data decoded by the Viterbi decoding unit 55 is audio-decoded by the audio codec unit 57 and DA-converted during audio communication, and then output as audio from the speaker 58. During data communication, the data decoded by the Viterbi decoding unit 55 is output to the outside via the data input / output unit 60.
[0098]
In this way, in the mobile station apparatus 45 according to the present embodiment, the Viterbi decoding unit 55, the convolutional encoding unit 56, the audio codec unit 57, and the timing control unit 54 are formed by the software of the DSP 53 of one chip. Therefore, it can be assembled with a small number of parts. Further, since the Viterbi decoding unit 55 is formed of the arithmetic processing unit of the first to eleventh embodiments, two path metrics can be updated in one machine cycle by pipeline processing by the DSP 53, thereby achieving high speed. In addition, it is possible to realize the ACS operation of Viterbi decoding by the DSP 53 with a relatively small processing amount.
[0099]
Here, the demodulator 51 and the modulator 52 are shown separately from the DSP 53, but they can also be configured by software of the DSP 53. Further, the DSP of the sixth embodiment can be used as the DSP, and the convolutional encoding unit 56, the audio codec unit 57, and the timing control unit 54 can be configured by separate components.
[0100]
(Embodiment 13)
FIG. 22 shows the configuration of the mobile station apparatus in the thirteenth embodiment. The mobile station device 45A of the present embodiment is different from the mobile station device 45 of the twelfth embodiment (FIG. 26) in that a modulator 65A is provided with a spreader 65, and a demodulator 51A is provided with a despreader 64. The baseband signal processing unit 50A of the provided CDMA communication system is used, and other configurations and operations are similar in many respects to the twelfth embodiment. In the case of CDMA communication, the timing controller 54 may include a RAKE receiver that combines a plurality of fingers selected from a delayed pull file or the like (not shown).
[0101]
Thus, mobile station apparatus 45A in the present embodiment can be applied to CDMA communication by providing despreading section 64 in demodulation section 51A and spreading section 65 in modulation section 52A.
[0102]
(Embodiment 14)
FIG. 23 shows the configuration of the base station apparatus according to the fourteenth embodiment. Components having the same functions as those shown in FIG. In FIG. 23, the base station apparatus 68 in the present embodiment includes an antenna unit 46 including a reception antenna 66 and a transmission antenna 67, a radio unit 47 including a reception unit 48 and a transmission unit 49, and signal modulation. And a baseband signal processing unit 69 that performs demodulation, encoding, and decoding, a data input / output unit 60 that inputs / outputs data to be transmitted / received to / from a wired line, an antenna unit 46, a radio unit 47, and a baseband signal And a control unit 63 that controls the processing unit 69 and the like.
[0103]
The baseband signal processing unit 69 includes a demodulation unit 51 that demodulates a reception signal, a modulation unit 52 that modulates a transmission signal, and a one-chip DSP 53A. The DSP 53A includes the first to eleventh embodiments. A Viterbi decoding unit 55 composed of an arithmetic processing unit, a convolutional encoding unit 56 that performs convolutional encoding of the transmission signal, and a transmission signal is convolved from the demodulation unit 51 to the Viterbi decoding unit 55 by measuring transmission / reception timing. The timing control unit 54 sent from the encoding unit 56 to the modulation unit 52 is formed by software.
[0104]
The control unit 63 of the base station device 68 performs transmission / reception operations under the control of the base station device 68, and the data input from the wired line is sent to the convolutional encoding unit 56 via the data input / output unit 60. input. The convolutional coding unit 56 performs convolutional coding on the input data and outputs the data to the timing control unit 54. The timing control unit 54 rearranges input data and adjusts transmission output timing, and outputs the result to the modulation unit 52. The data input to the modulation unit 52 is digitally modulated, D / A converted (not shown), and output to the transmission unit 49 of the radio unit 47. The transmission part 49 converts this into a radio signal, sends it to the antenna part 46, and is transmitted as a radio wave from the antenna.
[0105]
On the other hand, at the time of reception, the radio wave received by the antenna unit 46 is received by the receiving unit 48 of the wireless unit 47, AD converted, and output to the demodulating unit 51 of the baseband signal processing unit 69. The data demodulated by the demodulator 51 is rearranged by the timing controller 54 and then input to the Viterbi decoder 55 where it is decoded. The data decoded by the Viterbi decoding unit 55 is output to a wired line via the data input / output unit 60.
[0106]
Thus, since the base station apparatus 68 in this Embodiment forms each part of the Viterbi decoding part 55, the convolutional encoding part 56, and the timing control part 54 with the software of DSP53A of 1 chip | tip, there are few component points Can be assembled with. Further, since the Viterbi decoding unit 55 is formed of the arithmetic processing unit of the first to eleventh embodiments, two path metrics can be updated in one machine cycle by pipeline processing by the DSP 53A, thereby achieving high speed. In addition, it is possible to realize the ACS operation of Viterbi decoding by the DSP 53A with a relatively small processing amount.
[0107]
Here, the demodulator 51 and the modulator 52 are shown separately from the DSP 53A, but they can also be configured by software of the DSP 53A. Also, the DSP of the sixth embodiment can be used as the DSP 53A, and the convolutional encoding unit 56, the audio codec unit 57, and the timing control unit 54 can be configured by separate components.
[0108]
(Embodiment 15)
FIG. 24 shows the configuration of the base station apparatus in the fifteenth embodiment. The base station device 68A of the present embodiment is different from the base station device 68 of the fourteenth embodiment (FIG. 24) in that a modulation unit 52A is provided with a spreading unit 65, and a demodulation unit 51A is provided with a despreading unit 64. The baseband signal processing unit 69A of the provided CDMA communication system is used, and other configurations and operations are similar in many respects to the twelfth embodiment. In the case of CDMA communication, the timing control unit 54 may include a RAKE receiving unit that combines a plurality of fingers selected from a delay pull file or the like (not shown).
[0109]
Thus, base station apparatus 68A according to the present embodiment can be applied to CDMA communication by providing despreading unit 64 in demodulation unit 51A and spreading unit 65 in modulation unit 52A.
[0110]
【The invention's effect】
As described above, according to the arithmetic processing device of the present invention, the instruction decoding means for decoding an instruction, the storage means having a predetermined bit width and holding two metrics on the upper side and the lower side, the memory Access means that reads the two metrics by accessing the upper side and the lower side of the means in parallel, and four types obtained by adding one of the two path metrics and one of the two branch metrics First comparison means for inputting first, second, third, and fourth data, which is data, and comparing the first data and the second data; and parallel to the first comparison means Since the second comparison means for operating the second data and comparing the third data and the fourth data is provided, two path metrics can be updated in one machine cycle by pipeline processing by the DSP. And this DSP ACS operation of the Viterbi decoding can be realized by a relatively small amount of processing speed, an advantageous effect that size reduction, weight reduction and cost reduction and battery life of the mobile terminal is enabled to obtain.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an arithmetic processing unit according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating an example of a convolutional encoder with a coding rate of 1/2.
FIG. 3 is a schematic diagram showing a butterfly structure when the restraint length K = 4.
FIG. 4 is a block diagram showing a configuration of an arithmetic processing unit according to Embodiment 2 of the present invention.
FIG. 5 is a timing chart for explaining a pipeline operation of the arithmetic processing unit according to the second embodiment of the present invention.
FIG. 6 is a schematic diagram showing an example of memory access operation of the 4-bank RAM 14 according to the second embodiment of the present invention;
FIG. 7 is a block diagram showing a configuration of an arithmetic processing unit according to Embodiment 3 of the present invention.
FIG. 8 is a schematic diagram showing an example of memory access operation of the dual port RAM 15 according to the third embodiment of the present invention;
FIG. 9 is a block diagram showing a configuration of an arithmetic processing unit according to Embodiment 4 of the present invention.
FIG. 10 is a timing diagram illustrating pipeline operation of the arithmetic processing unit according to the fourth embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration of an arithmetic processing unit according to a fifth embodiment of the present invention.
FIG. 12 is a list showing a comparative example of the ACS operation from the nodes N0 and N1 to the nodes N′0 and N′4 and the ACS operation from the nodes N6 and N7 to the nodes N′3 and N′7.
FIG. 13 is a block diagram showing a configuration of an arithmetic processing unit according to the sixth embodiment of the present invention.
FIG. 14 is a block diagram showing a configuration of an arithmetic processing unit according to a seventh embodiment of the present invention.
FIG. 15 is a block diagram showing a configuration of an arithmetic processing unit according to an eighth embodiment of the present invention.
FIG. 16 is an input / output diagram of 4: 2COMPRESSOR in the eighth embodiment of the present invention;
FIG. 17 is a block diagram showing a configuration of an arithmetic processing unit according to the ninth embodiment of the present invention.
FIG. 18 is a diagram for explaining carry control of a double precision AU.
FIG. 19 is a block diagram showing a configuration of an arithmetic processing unit according to the tenth embodiment of the present invention.
FIG. 20 is a block diagram showing a configuration of an arithmetic processing unit according to the eleventh embodiment of the present invention.
FIG. 21 is a block diagram showing a configuration of a mobile station apparatus in Embodiment 12 of the present invention.
FIG. 22 is a block diagram showing a configuration of a mobile station apparatus in Embodiment 13 of the present invention.
FIG. 23 is a block diagram showing a configuration of a base station apparatus according to Embodiment 14 of the present invention.
FIG. 24 is a block diagram showing a configuration of a base station apparatus according to Embodiment 15 of the present invention.
FIG. 25 is a state transition diagram (trellis diagram) showing a state transition path of a convolutional encoder in Viterbi decoding;
FIG. 26 is a schematic diagram showing a butterfly structure of a trellis diagram.
FIG. 27 is a schematic diagram illustrating an example of a generated code by a convolutional encoder.
FIG. 28 is a program diagram showing an example of a Viterbi operation for channel coding.
FIG. 29 is a schematic diagram showing an example of storing pointer control and path metrics.
[Explanation of symbols]
1 Storage means for storing path metrics
2 buses
3 Storage means for storing branch metrics
4 Bus
5 comparison means
6 addition means
7 Storage means for storing comparison results
8 selection means
9 Comparison means
10 Addition means
11 Storage means for storing comparison results
12 Selection means
13 Bus
14 4 banks of RAM
15 Dual port RAM
16 Input register
17 Input register
18 Swap circuit
19 Adder
20 Adder
21 Comparator
22 Adder
23 Adder
24 Adder
25 Adder
26 Comparator
27 Adder
28 Adder
29 ALU
30 Input register
31 Input register
32 buses
33 Bus
34 Selector
35 selector
36 Register file
37 bus
38 bus
39 4: 2COMPRESSOR
40 4: 2COMPRESSOR
41 double precision AU
42 double precision adder
43 Shift register
44 Shift register
45 Mobile station equipment
46 Antenna
47 Radio section
48 Receiver
49 Transmitter
50 Baseband signal processor
51 Demodulator
52 Modulator
53 DSP
54 Timing control unit
55 Viterbi decoder
56 convolutional codes
57 Audio codec section
58 Speaker
59 Microphone
60 Data input / output device
61 Display
62 Operation unit
63 Control unit
64 Despreading section
65 Diffusion part
66 Receiving antenna
67 Transmitting antenna
68 Base station equipment
69 Baseband signal processor

Claims (4)

An arithmetic processing device capable of Viterbi decoding by a digital signal processor,
First comparison means for comparing the first data and the second data;
Second comparison means for comparing the third data and the fourth data;
An arithmetic processing unit that operates the first comparison unit and the second comparison unit in one cycle by one instruction . The arithmetic processing unit according to claim 1, wherein at least one of the first comparison unit and the second comparison unit is configured by an ALU (Arithmetic Logic Unit). 3. The arithmetic processing apparatus according to claim 1, further comprising two shift registers that hold comparison results of the first comparison unit and the second comparison unit. The arithmetic processing apparatus according to claim 2, wherein the ALU (Arithmetic Logic Unit) is capable of performing a register-memory operation.

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