JP3191442B2 - Arithmetic unit for Viterbi decoding - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit for Viterbi decoding in a digital signal processor for performing Viterbi decoding of convolutionally encoded data for error correction.

[0002]

2. Description of the Related Art In recent years, digital signal processors (hereinafter abbreviated as DSPs) have been attracting attention as processors for use in devices such as mobile phones, for example, following the trend of digitization in the mobile communication field. Bit errors frequently occur in data communication on a mobile radio line, and it is necessary to perform error correction processing. Some error correction techniques use Viterbi decoding as a convolutional code, and a DSP may be used for this error correction processing.

In Viterbi decoding, maximum likelihood decoding (maximum likelihood decoding) of a convolutional code is performed by repeating a simple process of addition, comparison and selection, and finally by a traceback operation for decoding data.
Is realized. In this Viterbi decoding, encoded data (received data sequence) corresponding to one information bit
Is obtained, the inter-signal distance (metric) of the path in each state at that time is calculated, and the surviving path is obtained.

FIG. 4 shows a convolutional encoder having a constraint length k, and a state transition from a state S _n and a state (Equation 1) at a previous time to a state S _2n (n is a positive integer) at a certain time. 2 for
Shows the path of the book extending

[0005]

(Equation 1)

The path metric a is the sum of the signal-to-signal distance (branch metric) between the output symbol of the path input to the state S _2n and the received data sequence and the branch metric of the surviving path up to the previous state S _n. And the path metric. Similarly, the path metric b is
The sum of the distance (branch metric) between the output symbol of the path input to the state S _2n and the received data sequence (branch metric) and the path metric that is the sum of the branch metrics of the surviving path up to the previous state (Equation 1) It is.

[0007] State S_2nPath metrics a and b input to
And select the smaller one as the surviving path. This
Addition to find path metric like
Rick comparison and path selection^k-1Pieces
Perform for the state of. Whichever way you choose your pass
The path selection signal PS
[S _i], (I = 0 to $ 2^k-1-1｝)
There is a need. Subscript of the previous state of the selected path is other
PS [S_i] = 0, if not small
PS [S_i] = 1. Eventually due to traceback
Survive based on this path select signal when decoding.
The data is decrypted while going back up the path.

FIG. 5 shows that the state S _2n (n is a positive integer) at a certain point in time is passed to the state S _n or state (Equation 1) at the immediately preceding point based on the path select signal PS [S _2n ]. Is shown.

Generally, the state _Si and the path select signal PS
The state immediately before [S _i ] can be expressed by (Equation 2).

[0010]

(Equation 2)

At this time, if a convolutional code terminated by the last bit is used, the path select signal may be used as decoded data.

FIG. 6 is a block diagram showing an arithmetic unit inside a conventional DSP for Viterbi decoding.

In FIG. 6, 1 is a data memory,
It stores a path metric, a path select signal, decoded data, and the like. Reference numeral 3 denotes a barrel shifter that shifts data read from the data memory 1. Reference numeral 6 denotes a first bus, which is connected to the data memory 1 and supplies data and stores calculation results. Reference numeral 7 denotes a first register, which holds the number of shift bits when shifting by the barrel shifter 3. Reference numeral 8 denotes an arithmetic logic operation circuit (hereinafter abbreviated as ALU), which performs an arithmetic logic operation. 9 is a first latch,
The value of the left input of the ALU 8 is temporarily stored. A second latch 10 temporarily stores the value of the right input of the ALU 8. Reference numerals 11 and 12 denote second registers, each of which is composed of a plurality of registers and temporarily stores a calculation result. Reference numeral 13 denotes a second bus for supplying data from the register 11 or the register 12. The number of shift bits of the barrel shifter 3 is shown in a two's complement system.
A negative value indicates a left shift.

The operation of a traceback operation when Viterbi decoding is performed on coded data that has been subjected to convolutional coding ending with the last bit in the arithmetic device configured as described above will be described. The conditions are as follows: the constraint length of the convolutional code is k, the number of encoded information bits is n, the data memory 1, the first bus 6, the second bus 13, the first latch 9, the second latch 10, The bit widths of the ALU 8 and the second registers 11 and 12 are each 2 ^k-1 bits. Further, the path select signal PS _t [S _i ] at time t, (t = 0 to ｛(n−1) +
(K-1)}, i = 0 to {2 ^k-1 -1} are packed into one word as in the path memory (Equation 3) and PM [t], (t =
It is assumed that the data is stored in the data memory in the form of 0 ({(n-1) + (k-1)}).

[0015]

(Equation 3)

The decoded data Y [i], (i = 0 to
{N-1} is stored in the data memory 1 in one bit and one word.

Next, the traceback operation will be described in steps. (1) The fixed value [0] is stored in the second latch 10. A
The LU 8 stores the value of the second latch 10 in the second register 11 as it is.

[Start from State 0] ] For the next steps (2) to (10), i is defined as ｛(n−1) + (k−
1) Repeat n times while counting down in｝ to (k-1).

(2) The value of the second register 11 is stored in the first latch 9 via the second bus 13. ALU8
To obtain the two's complement of the value of the first latch 9 and store it in the second register 12.

(3) The value of the second register 12 is stored in the first register 7 via the first bus 6.

[It becomes the number of shift bits for selecting the next path select signal. (4) The path memory PM [i] is read from the data memory 1, shifted by the number of shift bits specified by the first register 7 by the barrel shifter 3, and stored in the second latch 10. The ALU 8 stores the value of the second latch 10 in the second register 12 as it is.

[The path select signal to be selected is shifted to the least significant bit (LSB). (5) The value of the second register 12 is stored in the first latch 9 via the second bus 13, and the fixed value [1] is stored in the second latch 10. In the ALU 8, the logical product of the first latch 9 and the second latch 10 is obtained, and the second register 1
2 is stored.

[Extract only LSB. (6) The value of the second register 12 is converted to the decoded data Y [i−
(K-1)] in the data memory.

[LSB becomes decoded data. (7) The fixed value [k] is stored in the first register 7.

(8) The value of the register 12 is transferred to the second bus 13
And stored in the first latch 9 through the second register 12
Is output by the barrel shifter 3 via the first bus 6 by the number of shift bits specified by the first register 7 and stored in the second latch 10. First in ALU8
Of the second latch 10 and the second latch 10 is calculated.
In the register 12.

(9) Fixed value [-1] in the first register 7
Is stored. (10) The value obtained by shifting the value of the second register 12 by the number of shift bits specified by the first register 7 by the barrel shifter 3 is stored in the second latch 10. ALU8 is second
Is stored in the register 12 as it is.

[Steps (6) to (10) calculate the previous state. As described above, in the conventional arithmetic device,
By performing a calculation by combining the barrel shifter 3 and the ALU 8, a traceback operation in Viterbi decoding of n information bits can be performed in (9n + 1) steps.

A traceback operation when the operation bit width is smaller than the number of states 2 ^{k -1} or when a convolutional code is used continuously without terminating at the last bit can be similarly performed.

[0029]

However, in the above-mentioned conventional arithmetic unit, there are many arithmetic steps required to find the immediately preceding state, and the decoded data is stored in one bit and one word. However, there is a problem that the capacity of the battery becomes large.

An object of the present invention is to solve such a conventional problem and to provide an excellent arithmetic unit capable of performing a traceback operation in Viterbi decoding with a small number of operation steps and a small data memory. It is assumed that.

[0031]

According to the present invention, there is provided a memory for storing data, a barrel shifter for shifting the data read from the memory, and a data which is an output signal of the barrel shifter. A shift register also having a function of loading data from the memory and storing data in the memory by using a specific 1 bit as a shift input, and an inverter for inverting an output of a specific register of the shift register. The output signal of the barrel shifter is shifted while the data that is the output signal is the shift bit number of the barrel shifter and the data read from the memory is shifted by the barrel shifter by the shift bit number indicated by the data that is the output of the inverter. Is input to the shift register. Than it is.

[0032]

Therefore, according to the present invention, the previous state can be obtained only by inputting a path select signal to be selected by shifting the path memory read from the data memory by the barrel shifter to the shift register. The number of shift bits of the barrel shifter can be determined, and the path select signal stored in the shift register can be used as decoded data. Therefore, the traceback operation in Viterbi decoding is performed with a small number of operation steps and a small data memory.

[0033]

FIG. 1 is a block diagram showing the configuration of an arithmetic unit for Viterbi decoding according to an embodiment of the present invention.

In FIG. 1, 1 is a data memory,
It stores a path metric, a path select signal, decoded data, and the like. Reference numeral 2 denotes a bus which is connected to the data memory 1 and supplies data and stores calculation results. Reference numeral 3 denotes a barrel shifter that shifts data read from the data memory 1. Reference numeral 4 denotes a shift register which can shift-input a specific bit of the output of the barrel shifter 3 and loads data from the data memory 1 via the bus 2 or stores data in the data memory 1. Reference numeral 5 denotes an inverter which inverts the value of a specific register of the shift register 4 and gives the barrel shifter 3 the number of shift bits. The number of shift bits of the barrel shifter 3 is shown in a two's complement system. When the number is a positive number, the shift bit is shifted right, and when the number is negative, the bit is shifted left. The shift register 4 sets the shift input side to the most significant bit (MSB).
And

A description will be given of the operation of the traceback operation when Viterbi decoding is performed on coded data that has been subjected to convolutional code ending with the last bit in the arithmetic unit configured as described above. The condition is that the constraint length of the convolutional code is k, the number of encoded information bits is n, and the bit width of the data memory 1, bus 2, and shift register 4 is 2 ^k-1 bits. The barrel shifter 3 is connected to the shift input of the shift register 4.
, And the inverter 5 inverts the upper (k-1) bits of the shift register 4 and shifts the barrel shifter 3 by k bits obtained by adding 0 to the MSB of the output (k-1) bits. Make it the number of bits.
Further, the path select signals PS _t [S _i ], (t =
0 to {(n-1) + (k-1)}, i = 0 to {2 ^k-1 −
1}) is packed into one word as in the path memory (Equation 3) and PM [t], (t = 0 to {(n-1) + (k-1)})
Is stored in the memory in the form of

The decoded data Y [i], (i = 0 to
{N−1}) packs 2 ^k−1 bits into one word and stores it in the data memory 1. Next, the traceback operation will be described in steps.

(1) A fixed value [0] is stored in the shift register 4. [Start from state 0. ] Next steps (2) to (3)
I for {(n-1) + (k-1)} to (k-1)
Repeat n times while counting down with.

(2) From the data memory 1, the path memory P
M [i] is read, and the k bits output from the inverter 5 are shifted by the number of shift bits designated by the barrel shifter 3, and the MSB output from the barrel shifter 3 is shifted and input to the shift register 4.

[Send the path select signal to be selected to the MSB. [The upper (k-1) bits after the shift input indicate the previous state. [At the same time, the inversion of the upper (k-1) bits becomes the basis of the number of shift bits for selecting the next path select signal. (3) Store the contents of the shift register 4 in the data memory once each time 2 ^k-1 bits are decoded.

[The selected path select signal becomes the decoded data. As described above, according to the present embodiment, the selection of the path select signal and the calculation of the immediately preceding state can be performed in step (2). Therefore, the traceback operation in the Viterbi decoding of the n-bit information bits can be performed by using {n + ( n / 2 ^k-1 ) +
It can be done in 1 $ steps.

FIGS. 2 and 3 are block diagrams showing the configuration of an arithmetic unit according to another embodiment of the present invention. Figures 2 and 3
Has the first register 7, the ALU 8, the first latch 9, the second latch 10, the second latch 11,
12, a second bus 13 is added, and these configurations are necessary for performing processing other than the traceback operation of Viterbi decoding.

A traceback operation can be performed in the same manner when the operation bit width is smaller than the number of states 2 ^{k -1} or when the convolutional code is used continuously without terminating at the last bit.

[0043]

According to the present invention, as is apparent from the above embodiment, a path select signal selected by shifting a path memory read from a data memory by a barrel shifter is inputted to a shift register by a previous state. Can be determined, the number of shift bits of the next barrel shifter can be determined, and the path select signal stored in the shift register can be used as decoded data. This can be performed with a data memory having a small number of operation steps and a small capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic unit for Viterbi decoding according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a Viterbi decoding operation device according to another embodiment.

FIG. 3 is a block diagram showing a configuration of a Viterbi decoding operation device according to still another embodiment.

FIG. 4 is a state transition diagram (trellis diagram) showing a state transition path of a convolutional encoder in Viterbi decoding.

FIG. 5 is a state transition diagram (trellis diagram) showing a trace of a path at the time of traceback in Viterbi decoding.

FIG. 6 is a block diagram showing a configuration of a conventional Viterbi decoding operation device.

[Explanation of symbols]

 1 data memory 2 bus 3 barrel shifter 4 shift register 5 inverter

Claims (1)

(57) [Claims] 1. A memory for storing data, a barrel shifter for shifting the data read from the memory, and a data load from the memory using a specific 1 bit of data as an output signal of the barrel shifter as a shift input. And a shift register for storing data in the memory, and an inverter for inverting an output of a specific register of the shift register, wherein data as an output signal of the inverter is the number of shift bits of the barrel shifter, and Wherein the data which is an output signal of the barrel shifter is input to the shift register while shifting the read data by a shift bit number designated by the data which is an output signal of the inverter by the barrel shifter. An arithmetic unit for decoding.