JP3269845B2 - Viterbi decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for decoding an error correcting code, and more particularly to a Viterbi decoder for performing a maximum likelihood decoding of a convolutional code.

[0002]

2. Description of the Related Art In recent years, in order to improve the reliability of data transmission, error correction techniques for correcting errors in transmission data occurring during transmission have been widely used in many fields. There are various methods, but the error correction code that adds a redundant signal to the transmission signal and corrects the error on the receiving side using this signal has a higher transmission efficiency than the method that detects the error and requests retransmission of data. It has features such as being good and requiring only a one-way transmission path, and is widely used in the field of digital transmission systems.

Various codes have been proposed for the error correction code system. It is roughly divided into a convolutional code and a block code. The former has the advantage that the maximum likelihood decoding is possible and the error correction capability is large, but has the disadvantage that the device size of the decoder becomes large. On the other hand, the latter block code can be decoded with a relatively simple configuration, but has the disadvantage that the error correction capability is smaller than that of the convolutional code.

A known example of a Viterbi decoder which is famous as a maximum likelihood decoder is disclosed in, for example, Japanese Patent Application Laid-Open No. 62-24343.
No. 1 "Maximum likelihood decoder". In preparation for the description of the present invention, the coding rate is １ ／ and the constraint length is K = 3.
The principle of Viterbi decoding will be described by taking the convolutional code as an example.

A generator polynomial of a convolutional code having a coding rate of 、 and a constraint length of K = 3 is

[0006]

G ₀ = (1 + D ² ) xg ₁ = (1 + D + D ² ) x In Expression 1, D represents a delay operator of one unit time, and the addition is performed by exclusive OR. The convolutional encoder of Formula 1 is configured as shown in FIG. In FIG. 1, reference numerals 1 and 2 denote delay elements, which constitute a 2-bit shift register.
3, 4, and 5 are exclusive OR gates. The operating state of the encoder is represented by the two bits of the contents 1 and m stored in the shift register. Each time the information bit x is input to the shift register, the state of the encoder changes, and two bits (g ₀ , g ₁ ) are transmitted as a transmission code. In the transmission path,
An error sequence is added to this to become a reception sequence. The decoder estimates the state transition of the encoder from the received sequence, selects the most likely (most likely) state transition, and estimates the information sequence from this.

The coding rate R is represented by R = k / n when k-bit input information is coded into n bits. The constraint length K is represented by K = (m + 1) k, where m is the number of delay elements.

The principle of operation of the Viterbi decoder will be described in more detail with reference to FIG. FIG. 2B is called a trellis diagram, and represents a temporal change of a state transition. Now, as information bit sequence x, 1,0,0,1,
It is assumed that 1,1,0,1, (0,0) is sequentially input to the shift register. The initial value of the shift register is 0,0, and termination bits 0,0 for clearing the shift register are added to the end of the information bit sequence. When the transmission code sequence is obtained with reference to FIG.
It looks like 11,10, ... The path for this state transition is represented by the thick solid line in FIG. On the receiving side, this transmission sequence is added to the error sequence 00, 00, 10, 0 on the transmission path.
The reception sequence 11, 01, 01, 1 to which 0, 01,.
, 11, ... are received. The decoder tracks all possible state transitions of the encoder with reference to the received sequence, and estimates the state transitions of the encoder. The transition between times t _m and t _{m + 1} is represented as shown in FIG. Here, x / g ₀ , g ₁ described in the branch of the transition indicate the information bit x when the encoder makes the transition and the values of the transmission codes g ₀ , g _{1 to be} output. For example, when the information bit 0 is input from the state 10, the transmission code 11 is output and the state transits to the state 00.

Here, "likelihood" is defined in order to quantitatively represent the likelihood of a state transition. That is, the received codes r ₀ , r ₁
The Hamming distance between the candidate code and the candidate code is set as the likelihood of the branch. For example, when the received code is 01, the (branch) likelihood of each candidate code is

[0010]

[Table 1]

Is given as follows: The result obtained by sequentially integrating the branch likelihoods of the state transitions up to each state is referred to as “state likelihood”. In the example of FIG. 2, the state transits from the initial state 00 at the time point 0 to the state 00 or the state 01. The output code of the transition from the state 00 to the state 00 is 00, whereas the received code at this time is 11, so the branch likelihood is 2. Similarly, state 0
The output code of the transition from 0 to state 01 is 11, whereas the received code at this time is 11, so the branch likelihood is 0. Therefore, the state likelihoods of the state 00 and the state 01 at the time point 1 are 2, 0, respectively. In FIG. 2B, a number indicating the state likelihood at each time is attached beside a white circle indicating the state. Next, based on the branch likelihood associated with the possible state transition from time 1 to time 2, the state likelihood of state 00 at time 2 is 3, the state likelihood of state 01 is 3, and the state likelihood of state 10 is Is 0 and the state likelihood of state 11 is 2. Further, a branch likelihood of a possible state transition from time 2 to time 3 is obtained. After this point 3, there are two branches leading to each state, and in the process of maximum likelihood decoding, a branch having a smaller (likely) likelihood value is selected, and the other branch is discarded. FIG.
In (b), the selected branch is indicated by a solid line, and the discarded branch is indicated by a broken line. The selected branch likelihood is accumulated as the state likelihood. For example, the state 00 at the time point 5 transits from the state 00 or the state 10 at the time point 4, and the sum of the state likelihood and the branch likelihood is 5, 2, and the state likelihood value from the state 10 is small. A transition is selected, and the state likelihood of state 00 at time 5 is 2. Thus, the code sequence related to the chain of branches finally selected (survival path) is the code sequence estimated by the Viterbi decoder by the maximum likelihood.

FIG. 3 shows the configuration of the Viterbi decoder. In the figure, 31 is a branch likelihood calculation circuit, 32 is an addition / comparison / selection circuit, 33
Is a state likelihood memory, 34 is a path memory, and 35 is a maximum likelihood determination circuit.

The branch likelihood calculating circuit 31 obtains the likelihood (branch likelihood) of each possible state transition based on the received signal by the method shown in Table 1. The addition / comparison / selection circuit 32 obtains a new state likelihood by adding a branch likelihood to the state likelihood at the immediately preceding time stored in the state likelihood memory 33, and obtains a plurality of state transitions of one state. The likelihoods are compared, the transition having the smallest state likelihood is selected from the comparisons, and the state likelihood of the selected transition is set as a new state likelihood.
Update 3 At the same time, information j of the selected transition
(I) Sends (representing a transition from state j to state i) to the path memory 34. The path memory sequentially stores the transition information or the state number of the transition, and obtains a decoding result from the state transition selected and left at the final point by the maximum likelihood determination unit 35.

The details of the convolutional code and the Viterbi decoding are described in, for example, pages 143 to 151 of “Digital Communication Circuit” published by Sangyo Tosho in 1990.

[0015]

In the Viterbi decoder described in the above prior art, the information sequence corresponding to the most probable state is updated by estimating the transition of the operating state of the encoder based on information obtained from the received signal. Is the decoded output.

Among the above functions, the addition, comparison and selection functions and the path memory part complicate the configuration of the Viterbi decoder with a large processing amount. As a method of configuring the latter path memory, there is a method as shown in FIG.

In the configuration shown in FIG. 4A, 40 ₁ , 40 ₂ ,.
Reference numeral ₁₂ denotes a specially structured memory cell having a selection circuit.
In this path memory, the memory has the same structure as the trellis diagram, the selection circuit is controlled by transition information, and the surviving path (a series of numbers of the selected state) itself is stored. This has the advantage that the processing of the path memory and the decoding processing of the final output by maximum likelihood determination can be performed at high speed.However, since the memory configuration is complicated, a general-purpose memory cannot be used. There are drawbacks such as the need to prepare another object.

On the other hand, the configuration of FIG. 4B stores transition information. In the figure, 41 ₀ , 41 ₁ ,…, 41 _M-1 , 41 _M , 4
1 _{M + 1} ,... Indicate each storage location (corresponding to an address) of the memory. Each state has a separate storage area, and the storage area of each state includes M (M is a multiple of the constraint length) storage locations and stores the surviving path to that state at a certain point in time. I do. The latest state is stored at the storage position of t = 0 in the storage area for each state, and this state is shifted to t = 1 and t = 2 for each new state transition (FIG. 2B). Note that the meaning is different from t of the above.) For example, FIG.
In the example of (b), focusing on the storage area of the state 00, first, 00 is stored at the storage position of t = 0, and at the next time point, this 00 is shifted to the position of t = 1, and a new 00 is stored at t = It is added at the 0 position. At the next time point, both 00s are shifted to the positions of t = 1 and t = 2, respectively, and a new 00 is shifted to the position of t = 2.
It is added at the 0 position. At the next point in time, the path from the immediately preceding state 00 is interrupted in state 00, and the path from the immediately preceding state 10 survives. Therefore, the contents stored in the immediately preceding state 10 are transferred to the state 00 storage area, and 00 is added to the latest position.

As described above, in the configuration of FIG. 4B, a general-purpose memory can be used as the path memory, but the process of updating the contents of the path memory is complicated, and the maximum likelihood is increased when the final output is decoded. It is necessary to perform a trace-back process to trace the determined path back in time to obtain an information sequence. Therefore, there is a disadvantage that the time required for decoding is long.

It is an object of the present invention to provide a path memory configuration method that can overcome the problems related to the path memory of the conventional Viterbi decoder. In other words, a configuration is shown in which general-purpose memory can be used and path memory update processing and maximum likelihood decoding processing can be performed at high speed, thereby simplifying the configuration of the Viterbi decoder and shortening the processing time. is there.

[0021]

SUMMARY OF THE INVENTION A Viterbi decoder according to the present invention is a convolutional code having a coding rate R = k / n and a constraint length K for coding k-bit information into an n-bit (n> k) code. , A path memory for storing at least N words (N is 2 to the power of Kk) equal to the number of states according to the state transition information. A part k of the selected state number (binary number) while shifting the contents to the MSB side
The bits are additionally stored and updated on the LSB side, and a decoded output is obtained from overflow information by the shift processing in the path memory.

According to another aspect, the Viterbi decoder of the present invention convolves a coding rate R = k / n and a constraint length K for coding k-bit information into an n-bit (n> k) code. In a Viterbi decoder for maximum likelihood decoding of a code using a path memory, path memories at the m-th time point and the (m + 1) -th time point having N (N is 2 to the power of Kk) words are provided to determine the state likelihood. The contents Pj (m) of the j-th word in the path memory at the m-th point are shifted toward the k-bit MSB based on the state transition information j (i) from the state j to the state i obtained based on the LSB. The part k of the state number i (binary number) on the side
The value to which the bit has been added is stored in the path memory i at the (m + 1) th time point.
The content of the path memory is updated at each state transition time point so that the content of the word is Pi (m + 1).

[0023]

The present invention proposes a new path memory configuration method using a part of k bits of a state number represented by a binary number as information to be stored in the path memory. Here, k is the number of information bits of the convolutional code of the coding rate k / n.
Hereinafter, the operation of the present invention for a typical configuration of the present invention will be described with reference to FIGS.

Considering only two points in time, the trellis diagram shown in FIG. 2 shows that two trellises of the basic unit shown in FIG. 5 are combined. Basic unit trellis from state lm, caused a transition to state mn by 1-bit information input signal n, and outputs a 2-bit code g ₀ g _1.
That is, the information bit is a part of the state number. Hereinafter, this least significant bit (LSB) is used. From this relationship, if some bits of the state number are stored, the information sequence can be decoded. This will be described with reference to the trellis diagram of FIG. 2 as an example.

FIG. 6 shows a partial trellis diagram selected from the trellis diagram of FIG. 2 by taking two trellises as an example.
Trellis A in FIG. 6 is the transmission code sequence in FIG. When the state transition of trellis A is represented by a state number and its LSB is taken out, it can be seen that it is equal to the information sequence. Conversely, when two adjacent bits of the information sequence are extracted, it can be seen that the state number at that time is indicated. Therefore, if the state number LSB is stored in the memory, it is expected that the state transition path can be realized with a small number of bits.
Although trellis B in FIG. 6 branches off in the middle of trellis A, the information sequence can also be decoded by the above-described method. The above description can be easily understood by considering the configuration of the encoder. That is, the convolutional encoder (FIG. 1) operates to add a new information sequence to the LSB while shifting the state number indicating the state to the MSB side.

In the decoder, according to the transition information output from the addition / comparison / selection circuit, state transitions for all states may be stored in the path memory by the above-described method. Explaining a specific path memory configuration method, a memory having storage positions for the number of states is expressed by two equations (Pj (m), Pi (m + 1), i,
j = 0 to N-1) Prepare. Since the state transition information j (i) indicates that the state has transitioned from the state j to the state i, the content of the word Pj (m) in the path memory of the state j at the time point m is shifted to the MSB side,
The least significant bit (LSB) of the state number i is added to this, and the result is added to the word Pi of the path memory in the state i at the time point m + 1.
Store it in (m + 1). When this process is completed for all the state numbers i, the contents of the path memory at the time points m and m + 1 are transferred, and a new path memory is updated. Normally, each word in the path memory has a bit length that is 5 or 6 times the constraint length, and decoding is performed starting from the oldest bit in the path memory.

According to the method of the present invention, k bits overflowing when the path memory is shifted to the MSB side can be used as the decoded output, and the maximum likelihood judgment output can be obtained without performing the trace-back processing as in the conventional method.

As described above, in the Viterbi decoder of the present invention, the processing associated with the path memory can be simplified. Furthermore, since a memory having a special structure is not required unlike the conventional method, a general-purpose memory element can be used, and convolutional codes having different coding rates and different numbers of states can be easily dealt with. Further, since the oldest bit in the path memory for the state with the lowest likelihood need only be output for the maximum likelihood determination to obtain the decoding result, there is no need to perform the traceback processing as in the conventional method. Processing can be speeded up.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

First, FIG. 7 shows an embodiment in which the present invention is applied to a path memory of a Viterbi decoder for decoding a code in which the number of information bits is 1 (k = 1), like the code shown in FIG.

[0031] In FIG. 7, 71 t _{m + 1} point of the path memory, 72 is the arithmetic circuit, 73 is a path memory of t _m time. The path memory 71 stores N words 71 ₀ , to 71 _i ,
, 71 _{N− 1} , and the path memory 73 similarly has N words.
73 ₀ , 〜, 73 _j , 〜, 73 _N-1 . Path memory 71, 73
Can be configured using separate memory elements, but can also be configured using different address areas of the same memory element. The number of bits in each word is five or six times the constraint length. Each word stores state information for a series of paths, and is itself referred to herein as a path memory. The operation circuit 72 receives the transition information j (i) from the addition / comparison / selection circuit,
retrieves the contents of t _m when the state j of the path memory Pj (m),
The value of each bit is shifted to the MSB side by k bits (k = 1 in this example). Here, a 1-bit left shift is realized by doubling the digital value of the path memory. Here, the LSB of the state number i represented by a binary number is added to the vacant LSB position. The obtained operation circuit output is t _{m + 1}
It is stored as the contents of the path memory Pi (m + 1) in the state i at the time. This process sequentially repeated for each state i, and when the process for all of the state number of N is finished, transferred the path memory content of t _{m + 1} point as it is in the path memory of t _m point in time, state to a new point in time The above processing is performed for the transition.

FIG. 11 shows the time point t in the example of FIG.
7 shows the contents of each word in the path memories 71 and 73 after updating the path memory based on the selected state transition information from = 6 to t = 7. From the state 00 at the time t = 6 to the states 00 and 01 at the time t = 7, from the state 11 at the time t = 6 to the state 10 at the time t = 7, and from the state 11 at the time t = 7 to the state 11 at the time t = 7. 6 from state 00, there is a transition, and time t =
It can be seen that the LSB 1 bit of the new state number is added to the LSB position of the word content of the transition source state in each word of the path memory 71 of No. 7.

In the shift processing of the arithmetic circuit 72, the input state information causes overflow of the LSB of the state number stored in each path memory after shifting by the number of bits of the word. Can be used as output. Usually, the shift processing at a certain point in time is the number of states N
In this case, the number of overflows to be used is determined by selecting the one with the smallest likelihood value at that time or by majority vote. However, at the point when the bits input to the path memory are subject to overflow, if the number of bits of the word is sufficiently ensured, the overflow path usually merges with the same path in each state. No matter which state the overflow bit is used, the result is the same.

In this embodiment, the transfer accompanied by the operation by the arithmetic circuit 72 is performed from the path memory 73 to the path memory 71, while the transfer from the path memory 71 to the path memory 73 is simply performed for copying. . Instead of this configuration, the calculation by the calculation circuit 72 based on the next transition information j (i) can also be performed at the time of transfer from the path memory 71 to the path memory 73. By doing so, the number of times of data transfer between memories accompanying the state transition can be reduced by half.

In the configuration shown in FIG. 7, the same number of words (addresses) as the number of states N is used for each of the path memories 71 and 73.
It can be understood that a memory having a number of bits that is a multiple of the constraint length in each word may be prepared. Regarding the operation / transfer processing based on the transition information, in the conventional path memory configuration shown in FIG. 4B, each time a new status word is added, the status word already stored in the storage area is shifted to the next address. If the surviving path to the current state changes, the entire contents must be transferred between the state storage areas. On the other hand, in the present invention, it is necessary to transfer a word between path memories at adjacent times for each state transition, but the number of words is N (4 in this embodiment).
This transfer is not a burden as it is only a matter of course. Also, since the shift processing is a bit shift within one word, it can be performed very easily as compared with the shift of the entire word. The arithmetic circuit can be realized by hardware, or can be realized by a configuration by software processing such as a microcomputer or a DSP.

As described above, according to the present embodiment, a path memory can be realized without using a memory having a special configuration as in a conventional method of forming a trellis structure in a path memory, and transition information is stored. Unlike the conventional path memory having the above-described method, a trace-back process for obtaining a decoded output is not necessary, and therefore, there is an advantage that the maximum likelihood determination process can be performed at a high speed.

FIG. 7 shows an embodiment in which the present invention is applied to a code having the number of information bits of 1 (k = 1). However, the present invention can be easily extended to a code having k = 2 or more. FIG. 8 shows an example of a convolutional code when the number of information bits is 2. In the figure, 81 ₁ to 811 ₁₀ are exclusive OR gates, 82 ₁ , 82 ₂ , 82 ₃ , 8
₂₄ is a delay element. FIG. 8 shows a convolutional code having a coding rate R = 2/3 and a constraint length K = 6.

[0038]

G ₀ = D ² x + (1 + D + D ² ) yg ₁ = (1 + D) x + (1 + D + D ² ) yg ₂ = (1 + D + D ² ) x + y is there. When two bits x and y of information are input, a three-bit code g ₀ g ₁ g ₂ is output to cause a state transition. The number of states of this code is 16, which is 2 to the power of Kk.

FIG. 9A shows a basic unit trellis of the convolutional code shown in FIG. The figure shows information bits when n ₂ n ₃ = 00. N ₁ n ₀ = 0 to avoid complicating the figure
Only the transition branch to 0 is shown by a solid line. N ₁ n ₀ / g ₀ g ₁ attached to the solid line
g ₂ represents an information bit n ₁ n ₀ when the transition of the branch occurs code bits g ₀ g ₁ g _2. FIG. 9B shows code bits for all transition branches in FIG. 9A. The entire trellis of the code in FIG. 8 has 16 states, and is a trellis in which four basic unit trellises (n ₂ n ₃ = 00 to 11) in FIG. 9A are combined. From the basic unit trellis, it can be seen that, even in the case of this code, the state transition can be completely represented by storing the least significant two bits of the state number.

The number of information bits as shown in FIGS.
FIG. 10 shows an embodiment of a path memory to which the present invention is applied to a Viterbi decoder for a convolutional code in the case of (1). In the figure, 101 is a path memory at time t _{m + 1} , 102 is an arithmetic circuit, and 103 is a path memory at time t _m . 101 ₀ , 〜, 10
1 _i , ,, 101 _{N -1} , 103 _{0 ,,,} 103 _j,,, 103 _{N -1} are words constituting a path memory. Path memory 1 of the embodiment of FIG.
The operations of 01 and 103 are almost the same as those of the embodiment of FIG. 7, but the operation circuit 102 is different. Transition information j (i)
Is received from the addition / comparison / selection circuit, the contents of the path memory Pj (m) at the point in time t _m are fetched, and the contents of
Shift to the side. Adding the least significant 2 bits of the state number i to LSB2 bit vacated, is stored in the path memory of t _{m + 1} time as Pi (m + 1). The path memory updating and decoding processing can be performed in the same manner as in the embodiment of FIG.

The configuration of the arithmetic circuit of FIG. 10 can be performed by addition processing as in FIG. 7, and conversely, FIG. 7 can also be processed by bit shift. Also in this example,
The arithmetic processing can be performed between the path memories 101 and 103 in both directions. The configuration in FIG. 10 can be configured by either hardware or software.

In each of the embodiments described above, the k bits on the LSB side of the state number to be stored in the path memory are stored. However, the k bits on the LSB side of the state number (in some cases, the middle) are stored. It will be easily understood from the description of FIG. 6 that the same result can be obtained by doing so. However,
If the LSB of the state number i is not used, the LSB side bit of the last remaining state number i needs to be fetched into the path memory.

Although the present invention has been described with respect to the embodiment in which the present invention is applied to Viterbi decoding of a convolutional code having 1 or 2 information bits, the present invention can be similarly applied even when the number of information bits is larger. I can do it. In the conventional path memory, the configuration may change completely when the coding rate changes. However, in the present invention, it can be easily dealt with only by changing the number of bits of the word in the path memory.

[0044]

According to the present invention, since the path memory of the Viterbi decoder can be configured using a general-purpose memory, the configuration can be simplified, and the convolutional code having different coding rates and different numbers of states can be easily realized. Can deal with. Since the number of words in the path memory can be reduced, the processing for updating the path memory requires only a small amount of processing, and the processing time can be reduced. Further, since only a part (k bits) of the state number is stored, not only the surviving path can be represented by a small number of bits, but also the maximum likelihood determination processing for obtaining a decoded output is performed using the MSB of the path memory.
, It is sufficient to output the overflowing bits as they are,
Since there is no need to trace back unlike the conventional method, the maximum likelihood determination processing can be speeded up. In an actual configuration, no special function is required, so that it can be realized by hardware using a logic circuit or software using a general-purpose processor.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a convolutional encoder.

FIG. 2 is a trellis diagram showing the operation of the convolutional encoder of FIG.

FIG. 3 is a configuration block diagram of a Viterbi decoder.

FIG. 4 is a configuration diagram of a path memory according to a conventional method.

FIG. 5 is a diagram showing a basic unit trellis of the trellis diagram of FIG. 2;

FIG. 6 is a partial trellis diagram of FIG. 2 for explaining the principle of the present invention.

FIG. 7 is a configuration diagram of one embodiment of the present invention.

FIG. 8 is a configuration diagram of a convolutional encoder having a coding rate of 2/3 and a constraint length of 6;

FIG. 9 is a diagram illustrating a basic unit trellis of the convolutional code of FIG. 8;

FIG. 10 is a configuration diagram of a second embodiment according to the present invention.

FIG. 11 is an explanatory diagram of the update processing of the path memory of FIG. 7;

[Explanation of symbols]

1,2,82 ₁ , 82 ₂ , 82 ₃ , 82 ₄ … Delay element, 3,4,5,81 ₁ , 〜, 81 ₁₀ …
Exclusive OR gate, 31 ... branch likelihood calculation circuit, 32 ... addition / comparison selection circuit, 33 ... state likelihood memory, 34 ... path memory, 35 ...
Maximum likelihood determination circuit, path memory at the time of 71,101 ... tm _{+ 1} , 72,102
... calculation circuit, 73,103 ... t _m path memory of the time.

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03M 13/00 H04L 25/00 H04L 27/00 H04L 1/00

Claims (4)

(57) [Claims] 1. Viterbi decoding for decoding a k-bit information into an n-bit (n> k) code with a coding rate R = k / n and a constrained length K with maximum likelihood decoding using a path memory. M-th time with N words (N is 2 to the power of Kk)
Point and the path memory at the (m + 1) th time point, and the state j to the state i obtained based on the state likelihood determination.
The path memory at the m-th point based on the state transition information j (i)
To the k-bit MSB side of the content Pj (m) of the j-th word
And the LSB side of the state number i (binary number)
The value to which some k bits have been added is the path memo at the (m + 1) th point.
Each state is set so that the content of the i-th word of the word is Pi (m + 1).
Calculation cycle for updating the contents of the path memory at each state transition time
And a road . 2. The operation circuit according to claim 1, wherein the operation circuit is operated before each state transition.
At the end of updating the path memory contents, the
Transfer the contents of the path memory to the path memory at the m-th time point
2. The Viterbi decoder according to claim 1, wherein: 3. The operation circuit switches the path memory at the (m + 1) -th time point and the path memory at the m-th time point after the completion of the updating of the path memory content performed at each state transition time ,
Viterbi decoder according to claim 1, characterized in that the contents of the path memory of the m-th time by updating the contents of the path memory of the (m + 1) -th time. 4. The method according to claim 1, wherein the number of bits of each word of said path memory is
When the content of the path memory is updated, it is set to a multiple of the constraint length K.
K bits overflowed from the MSB side of the path memory
Viterbi decoder of claim 1, 2 or 3 wherein utilizing the data as a decoded output.