JP2591332B2 - Error correction decoding device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoding device used for a digital car telephone or the like.

2. Description of the Related Art Conventionally, when a digital signal is transmitted, an error correction decoding device is known as a device that corrects a received signal even when a code error occurs due to noise, distortion, or the like received from a transmission path. . In such an error correction decoding device, several error correction techniques are employed.

As described above, among error correction methods, there is a method using Viterbi decoding. Viterbi decoding is maximum likelihood decoding that performs convolutionally encoded data using an algorithm called a Viterbi algorithm. In this Viterbi decoding, encoded data (reception sequence) corresponding to one information bit
, The metric (cumulative metric) of the surviving path in each state at that time is calculated and updated. At this time, if the branch metric taken by each path is calculated every time for the value of the received sequence at that time, the amount of calculation becomes enormous.

Therefore, conventionally, an error correction decoding device using Viterbi decoding has a table in which a value of a branch metric taken by each path is stored in advance for each value of a reception sequence in a storage circuit, and a value of the reception sequence at each time is stored in a storage circuit. By extracting the value of each branch metric from the table, the metric of each state can be calculated and updated with a small calculation value.

FIG. 6 and FIG. 7 are diagrams showing examples of tabulated branch metric values stored in a branch metric storage circuit of an error correction decoding device using conventional Viterbi decoding.

This is a punctured code with a coding rate of 9/17 and a constraint length of 6, and the generator polynomial is g ₀ (D) = 1 + D + D ³ + D ⁵ g ₁ (D) = 1 + D ² + D ³ + D ⁴ + D ⁵ is there. The puncturing matrix is It is. At this time, in the error correction decoding apparatus using Viterbi decoding, the number of states is 2 ^K−1 = 32 because of the constraint length K = 6, and if hard decision decoding is performed, the received sequence R becomes 2 bits and the dummy bits A: (0,0) B: (0,1) C: (1,0) D: (1,1) When not including dummy bits (indicated by *) Is divided into two cases, E: (0, *) and F: (1, *). In each state, since there are two paths extending from the immediately preceding point to that state, each of the states A to F has two branch metric values in each state. The tables obtained in this way are shown in FIGS. 6 and 7.

In the error correction decoding device using the Viterbi decoding, decoding is performed as follows using the above-described table.

When the received data is input, it is determined which of A to F the received sequence corresponds to, and the two data in the table as shown in FIG. 6 or FIG. 7 stored in the branch metric storage circuit are determined accordingly. The surviving path is determined by extracting the branch metric value of the path, adding the value to the metric value of the two states that extend the path from the immediately preceding time point to the state, and comparing the values.

As described above, even in the above-described conventional error correction decoding apparatus, even if received data is input, a branch metric table for each received sequence is calculated without calculating a branch metric taken by each path for the value of the received sequence every time. By using this, the metric can be calculated with a small amount of calculation.

SUMMARY OF THE INVENTION However, in the above-described conventional error correction decoding apparatus for Viterbi decoding, it is necessary to store all branch metric values in a memory circuit for each received sequence. There was a problem of needing.

Therefore, the present invention is to solve the above-mentioned conventional problem, and to provide an excellent error correction decoding device capable of performing Viterbi decoding by significantly reducing the memory amount without increasing the operation amount. It is the purpose.

Means for Solving the Problems In order to achieve the above object, the present invention provides an error correction decoding device capable of Viterbi decoding, which calculates and updates a cumulative metric (path metric) of surviving paths in each state at each time point. Addition / comparison / selection circuit for processing and weighing (branch metric) on the value of the received sequence in advance
A first table indicating possible value of a path and a second table indicating how a branch metric that a path in each state can actually take correspond to the first table are stored. When a reception sequence is determined, a candidate for a branch metric is determined from the first table, and by combining the candidates according to a type to which each state belongs from the second table, an actual branch is determined. It is characterized in that a metric value can be obtained.

Operation The present invention has the following effects by the above configuration.

When the received sequence is input, the candidate of the branch metric that the path can take for the value is known in the first table, and how the above candidates are combined in the second table to determine the branch that each path actually takes Since it is known for each state whether the value matches the metric value, the branch metric of each path can be easily obtained with a small memory amount by combining the two tables.

Examples Hereinafter, the present invention will be described based on the illustrated examples.

FIG. 1 is a block diagram showing an embodiment of an error correction decoding device capable of Viterbi decoding according to the present invention.

FIGS. 2, 3 and 4 are explanatory diagrams showing first to third tables used in the embodiment of the present invention.

The error correction decoding device capable of Viterbi decoding shown in FIG.
It comprises an Add / Compare Select (ACS) circuit 1, a metric (branch metric) storage circuit 2, a cumulative metric (metric) storage circuit 3, a path memory circuit 4, and a maximum likelihood determination circuit 5. It is configured as follows.

Here, ACS circuit 1 takes the receive data from the input terminal T _i, to calculate the metric of the surviving path, giving the calculation results to the metric memory circuit 3 and a path memory circuit 4. The branch metric storage circuit 2 stores a table 200 shown in FIG. 2, a table 300 shown in FIG. 3, and a table 400 shown in FIG. 4, and these are supplied to the ACS circuit 1. And the table shown in FIG.
Reference numeral 200 denotes the relationship between the values of the reception sequences A to D that do not include the dummy bits and the candidates p _{1 to} p ₄ of the values that the path can take as the branch metric. In addition, the table 300 shown in FIG. 3 shows the values of the reception sequences E to F including the dummy bits, which can be taken by the path as a branch metric.
shows the relationship between p ₁ ~p _4. And the table of FIG.
400 shows how the branch metric actually taken by the path in each state corresponds to the above table.

The metric storage circuit 3 stores and updates the metric calculated in the ACS circuit 1 and supplies the metric to the ACS circuit 1 and the maximum likelihood determination circuit 5. The path memory circuit 4 stores and updates the surviving path from the ACS circuit 1 and can supply the surviving path to the maximum likelihood determination circuit 5. The maximum likelihood decision circuit 5, are also available outputs decoded data obtained by determining a decoded output from the survivor path from the path memory circuit 4 from the output terminal T _0.

By the way, the table 200 shown in FIG. 2 and the table 300 shown in FIG. 3 are obtained as follows from the table 400 shown in FIG. That is, this is a punctured code having a coding rate R = 9/17 and a constraint length K = 6, and the generator polynomial is g ₀ (D) = 1 + D + D ³ + D ⁵ g ₁ (D) = 1 + D ² + D ³ + D ^4, which is a + D ^5. The puncturing matrix is It is. In an error correction decoding apparatus using Viterbi decoding, when performing hard decision decoding, the received sequence R becomes 2 bits, and when no dummy bit is included, A: (0,0) B: (0,1) C: (1,0) D: (1,1) Further, when a dummy bit (indicated by *) is included, there are two types of E: (0, *) F: (1, *). These are divided into cases.
At this time, if the shift register (not shown) of the decoder is composed of 5 bits, the state S _i (i = 0 to 31) in the Viterbi decoder takes 32 bits.
S _i can be divided into m = 0 to 15 in two states in the order of the value of i. This means that m = n (where n is an integer of 0 ≦ n ≦ 15) includes both the state S _2n and the state S _{2n + 1} .

Next, the operation of the above embodiment will be described in detail below.

FIG. 5 shows a state in which four paths extend from the state S _n and the state S _{n + 16 immediately} before the state S _2n and the state S _{2n + 1} at a certain time. In each state, since there are two paths extending to the state from the immediately preceding point, four values of the branch metric are required. In this figure,
Assuming that the value of the branch metric of each path is a, b, c, d, the value of (a, b, c, d) is determined for each m according to the reception sequence R.

Receive data is input through the input terminal T _i to the ACS circuit 1. The ACS circuit 1 determines which of the received sequences A to D containing no dummy bits or the received sequences E and F containing the dummy bits corresponds to the received data, and prepares the branch metric storage circuit 2 accordingly. From the table 200 shown in FIG. 2 or the table 300 shown in FIG. 3, candidates p ₁ to
get the p _4.

Next, the ACS circuit 1 converts the data stored in the branch metric storage circuit 2 from the table 400 shown in FIG.
For each state, it is determined to which of the types I to IV the value of m belongs, and the value of the branch metric is accordingly changed to p ₁ to p ₄
Is determined by the combination of

For example, if the reception sequence at a certain point is A, the ACS circuit 1
Obtains _four branch metric candidates, P ₁ = 0 P ₂ = 2 P ₃ = 1 P ₄ = 1, from the table 200 in FIG. The ACS circuit 1 converts the states S ₀ and S ₁ at the time of m = 0 into a type I by the table 400 in FIG.
Detect that it belongs to. Therefore, ACS circuit 1
Is the branch metric of these two states (a, b,
c, d) by (p ₁ , p ₂ , p ₂ , p ₁ ) = (0, ₂ , ₂ , 0)
You will get as

Similarly, for each state S _i (i = 0 to 31), the ACS circuit 1 refers to the table 200 to the table 400 in FIG. The surviving path is determined by comparing the value and the value of the immediately preceding point stored in the metric storage circuit 3 with the value of the metric of the two states that extends the path to that state, and comparing them. At this time, it is possible to prevent an increase in the amount of processing due to the determination as to which type the value of m belongs in FIG. 4 by performing calculations for each of the types I to IV instead of the order of the value of m. It is.

In the above embodiment, the embodiment in which the punctured code performs Viterbi decoding has been described. However, the above embodiment can also be applied to Viterbi decoding using a convolutional code. When this convolutional code is used, the branch metric storage circuit 2 stores a table showing candidates of values that a path can take as a branch metric with respect to the value of the received sequence, and a state corresponding to FIG. Is provided with a table indicating how the branch metrics actually taken by the path correspond to the above table.

As described above, according to the above embodiments, when the reception sequence is determined, the branch metric candidates are determined, and by combining these candidates according to the type to which each state belongs, the actual branch metric value can be obtained. It has the advantage that it can be done. Further, according to the above embodiments, it is not necessary to store all branch metrics in the memory circuit for each reception sequence, so that the amount of memory can be significantly reduced.

According to the present invention, as is apparent from the above embodiment, when the reception sequence is determined, the branch metric candidates are determined, and by combining these candidates according to the type to which each state belongs, the actual branch metric value is determined. It has the advantage that it can be obtained. The present invention has an effect that the amount of memory can be significantly reduced because it is not necessary to store all branch metrics for each reception sequence in a memory circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an error correction decoding apparatus according to the present invention, FIGS. 2 to 4 are explanatory diagrams showing tables used in an embodiment of the present invention, and FIG. 6 and 7 are explanatory diagrams showing tables of branch metric values used in the conventional apparatus. 1 ... ACS circuit, 2 ... branch metric storage circuit,
3 ... Metric storage circuit, 4 ... Path memory circuit,
5. Maximum likelihood determination circuit, 200, 300, 400 ... table.

Claims (1)

(57) [Claims] 1. An error correction decoding device capable of Viterbi decoding, comprising: an addition / comparison / selection circuit for performing an arithmetic operation for calculating and updating a cumulative metric (path metric) of a surviving path in each state at each time; A first table showing candidates of values that the path can take as a metric (branch metric) and how the branch metric that the path can actually take in each state corresponds to the first table. And a storage circuit storing a second table shown in the table.When a reception sequence is determined, a branch metric candidate is determined from the first table, and the candidate is determined from the second table according to a type to which each state belongs. An error correction decoding device characterized in that an actual branch metric value can be obtained by combining the values.