JP3229047B2 - Viterbi decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoder used for correcting an error in a digital signal in a digital communication system or the like.

[0002]

2. Description of the Related Art Conventionally, in a digital communication system or the like as shown in FIG. 6, a digital signal supplied from an information source 111 is subjected to processing such as encoding in a convolutional encoder 113 and then transmitted and received. On the side, the received signal is demodulated by the demodulation unit 115 and then decoded by the Viterbi decoder 117.

The Viterbi decoder is provided to correct errors in a digital signal, and all states that can occur in the encoder, specifically, the state of the shift register, are changed in each state at each decoding time. The most probable path among a plurality of paths that can transition to a certain stage, in other words, the most likely path among the paths to be merged into a certain stage, so-called “surviving path”, and further specifies those surviving paths Is a decoder that estimates the maximum likelihood information sequence with high probability by outputting bits that have been traced back in the past by the length of. For example, the coding rate 1 /
In the convolutional code of n, if the number of stages of the shift register in the encoder is m, the constraint length ν is (m + 1), and the number of states is 2 ^m .

FIG. 7 is a block diagram showing an example of an encoder that performs convolutional encoding with an encoding rate r = 1/2 and two stages of registers.

Hereinafter, a specific operation of the convolutional coding will be described with reference to FIG. In FIG. 7, the shift register 113a stores the input data at the previous time (t-1), and the shift register 113b stores the input data at the previous time (t-2). Thus, the data i to the shift register 113a when the input data i from input terminal T ₁ (t) is given (t-
1) The data i (t-2) is stored in the shift register 113b.
Is stored.

The adder 113c receives the input data i
The exclusive OR of (t) and the output i (t−2) of the shift register 113b is obtained, and the adder 113d outputs the output i (t−1) of the shift register 113a and the output of the adder 113c, that is, the input data. i (t) and shift register 11
The exclusive OR with the exclusive OR of the output i (t−2) of 3b is obtained.

[0007] The output of the adder 113c is output from the output terminal T ₂ as encoded data C ₀ (t), the output of the adder 113d is output from the output terminal T ₃ as encoded data C ₁ (t) You.

Accordingly, the following equations (1) and (2) are established.

C ₀ (t) = i (t) + i (t−2) (1) C ₁ (t) = i (t) + i (t−1) + i (t−2) (2) , The encoder shown in FIG. 7 is a shift register 113a,
The following four states can be taken according to the contents of 113b.

State S ₀ : i (t−1) = 0, i (t−2) = 0 State S ₁ : i (t−1) = 0, i (t−2) = 1 State S ₂ : i (t-1) = 1, i (t-2) = 0 state _{S 3: i (t-1} ) = 1, i (t-2) = 1 the output C _0, C ₁ of the encoder It is uniquely determined by the current state and the next input data i, and at the same time, the next transition state is determined.

Hereinafter, referring to the block diagram shown in FIG. 8, the state transition diagram shown in FIG. 9, and the trellis diagram shown in FIG. 10, the above-mentioned states S ₀ ,..., S ₃ and the coded data C ₀ , A description will be given of a conventional Viterbi decoder together with an operation of correcting a data error on the receiving side based on C ₁ .

Each decoding stage (decoding time) shown in FIG.
In soft decision, or the hard decision received signal r _0, r ₁ set is input from the input terminal T _a shown in FIG. 8, the envelope information of the received signal corresponding to each decoding stage (decoding time) in FIG. 8
Is input to the input terminal T _b shown in, the received signals r _0, r ₁ is supplied to the branch metric calculating circuit 103, each branch on the trellis diagram shown in FIG. 10 B10
1, a numerical value indicating the likelihood of B102,.
That is, a branch metric is calculated.

Thereafter, these branch metrics are represented by A
CS (Add Compare Select) circuit 1
05, and the path with the highest likelihood that can transition to each state is selected from the path metric calculated by the sum of the branch metrics. For example, in the trellis diagram of FIG. 10, for selecting the first (t-1) the maximum likelihood path can transition to S ₀ of the stage, the branch path metric S ₀ in the (t-2) stages B101 a value obtained by adding the branch metric, the (t-2) and a value obtained by adding the branch metric of the branch B103 path metric S ₁ on stage are compared, one is selected.

[0014] On the other hand, from the memory 107 for storing the path read the (t-2) S ₀ and S ₁ of the surviving path at stage, the path is selected based on the comparison result of the above path metric . The selected surviving path is written into the memory 107 again together with a new bit.
Here, one bit added at the time of updating the surviving path is determined by a state transition method as shown in each branch of FIG.

When decoding of all input received signal sequences is completed, an output signal determined by an appropriate determination method from a surviving path corresponding to each state is output from an output terminal _Tc .

[0016]

In such a conventional Viterbi decoder, when the envelope information cannot be accurately extracted due to imperfection of a circuit for generating the envelope information of the received signal, a branch metric calculation circuit is required. However, there is a disadvantage that the reliability of the value of the branch metric calculated by the equation (1) decreases, and the reliability of decoding decreases.

Further, the conventional Viterbi decoder has a high error correction capability when the probability of occurrence of information at an information source is uniform. However, when the occurrence probability of the information is non-uniform, since the conventional Viterbi decoder does not perform decoding in consideration of the occurrence probability of the information, it seems that some or all of the occurrence probability of the information is known. In such a case, it cannot always be said that it has the optimum decoding capability.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a Viterbi decoder having a low decoding error rate.

[0019]

According to a first aspect of the present invention, there is provided a smoothing means for smoothing envelope information relating to a received signal, an output of the smoothing means, and a receiving means. A branch metric calculation means for calculating a branch metric from the signal to the signal corresponding to the transition from the preceding state to the next state; and a path to that state for all possible states. A path metric storage unit for storing a signal; and a path metric storage unit for storing a path metric indicating the likelihood of the path, wherein the path metric stored in the path metric storage unit is calculated by the branch metric calculation unit. The branch metric is added to generate the addition result corresponding to each state, these addition results are compared, the next path is selected, and this path metric is added. Wherein updating the stored contents of the path memory unit, updates the stored contents of said path metric storage means by said addition result corresponding to this path by AC
The gist of the present invention is to include an S circuit and output means for outputting a path selected by the ACS circuit as a decoding result.

Further, the second invention of the present application provides a branch metric calculating means for calculating a branch metric representing a correlation between a signal corresponding to a transition from a preceding state to a next state from an input received signal, A path metric storage unit for storing a signal indicating a path leading to the state for all possible states; and a path metric storage unit for storing a path metric indicating the likelihood of the path. The branch metric calculated by the branch metric calculation means is added to the path metric stored in the step (a), an addition result corresponding to each state is generated, these addition results are compared, and the next path is selected. An ACS circuit for updating the storage content of the path storage means with a path, and determining a decoding result from the path stored in the path storage means Decoding information storage means for storing part or all of the decoding information relating to the decoding result, wherein the ACS circuit comprises a predetermined metric determined based on the information stored in the decoding information storage means. Is added to the path metric.

Further, the Viterbi decoder according to the second aspect of the present invention has a checking means for judging whether or not the decoding result is correct. When the decoding result is judged to be correct, the contents of the decoding information storage means are determined. Is preferably updated.

[0022]

The Viterbi decoder according to the first aspect of the present invention configured as described above performs a transition from the preceding state to the next state from the output obtained by smoothing the envelope information relating to the received signal and the received signal. Improving the reliability of the branch metric by calculating a branch metric representing the correlation with the corresponding signal, and then adding the branch metric to the path metric stored in the path metric storage means in the ACS circuit;
After generating the addition result corresponding to each state, comparing these addition results, selecting the next path, and updating the storage content of the path storage means with this path, the path stored in the path storage means is changed. Output as decryption result.

The Viterbi decoder according to the second aspect of the present invention calculates a branch metric from an input received signal,
The branch metric is added to the path metric stored in the path metric storage means by the CS circuit, and the addition result is compared to select the next path and update the storage contents of the path metric storage means by this path. Further, the ACS circuit adds a predetermined metric determined based on the information stored in the decoded information storage means to the path metric, for example, when the nature of occurrence of part or all of the information is known. Therefore, the decoding error rate is improved.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first example of a Viterbi decoder according to the present invention.
FIG. 3 is a block diagram showing a configuration of the example. In Figure 1, the soft-decision information b _1, b ₂ of the soft decision received signal is input to the input terminal T _a, envelope information c of the received signal is inputted to the input terminal T _b. Envelope information c of the received signal input from the input terminal T _b is inputted to the smoothing circuit 1, is smoothed, it is supplied to the branch metric calculating circuit 3 with the received signal inputted from the input terminal T _a .

Here, assuming that the envelope information smoothed by the smoothing circuit 1 is “c ′”, the branch metric calculation circuit 3 performs the smoothed envelope information c ′ and the soft decision information b _{1 of the} received signal. , B ₂ , a branch metric is calculated. Here, if the soft decision information when there is no error is “b ′”, the branch metric m is expressed by the following equation (3) when the hard decision information of the received signal matches the received signal assumed in each branch. And Expression (5), and when they do not match, Expression (4) and Expression (6) are used.
It is calculated by equation (7).

M ₁ = c ′ ² (| b ₁ | −b ′) ² (3) c ′ ² (| b ₁ | + b ′) ² (4) m ₂ = c ′ ² (| b ₂ | −b ′) ² ... (5) c ′ ² (| b ₂ | + b ′) ² ... (6) m = m ₁ + m ₂ (7) where the branch metric is expressed by the above formulas (3) to (3). Instead of the expression (6), the calculation can also be performed by the following expressions (8) to (11).

M ₁ = c ′ ² | b ₁ | (8) −c ′ ² | b ₁ | (9) m ₂ = c ′ ² | b ₂ | (10) −c ′ ² | b ₂ | (11) These branch metrics are supplied to the ACS circuit 5. The ACS circuit 5 selects, from the path metrics calculated by accumulating the branch metrics, the most likely path among the states that can transition to each state. That is, by adding a branch metric to the path metric of the previous stage stored in the path metric storage means provided in the ACS circuit 5, the path metrics of all paths that can transition to the state are calculated and compared, The path corresponding to the maximum likelihood path metric is selected. Here, the path at the previous stage is read from the path memory 6 as the path storage means, and the updated path is written again to the path memory 6,
The path metric corresponding to the updated path is written to the path metric storage. When the decoding is completed, the maximum likelihood path is output from the output terminal _Tc as a decoding result.

That is, in the conventional Viterbi decoder, if a disturbance such as Gaussian noise remains in the envelope information used for calculating the branch metric, the disturbance lowers the reliability of the branch metric calculation, and The error rate was degraded. On the other hand, in the first Viterbi decoder according to the present invention, the reliability of the calculation of the branch metric is reduced by smoothing the envelope information to reduce or remove the disturbance included in the envelope information. This will increase the decoding error rate more than before.

Next, the configuration of a second embodiment of the Viterbi decoder according to the present invention will be described with reference to the block diagram shown in FIG. As shown in FIG. 2, when the received signals subjected to the soft decision or the hard decision are input from the input terminal T, these received signals are supplied to the branch metric calculation circuit 3 and the respective branches on the trellis diagram of FIG. The branch metrics corresponding to B101, B102,... Are calculated.

These branch metrics are supplied to the ACS circuit 5A. The ACS circuit 5A determines a third value determined from the branch metric and part or all of the decoded information.
From the path metric calculated by accumulating the metrics of
The path with the highest likelihood among the states that can transition to each state is selected. That is, by adding a branch metric to the path metric in the previous stage and further adding a third metric, the path metrics of all paths that can transition to the state are calculated and compared, and the path metric corresponding to the maximum likelihood path metric is calculated. Select a path.

Here, the third metric determined from part or all of the decoded information is obtained, for example, from the occurrence probability of the information sequence. As an example, k and (k +
1) Consider a case where a bit has a correlation with the previous frame. K and (k + 1) of the decoding result of the previous frame
The second bit is stored in the second memory 7b of FIG.
That is, it is understood that the k and (k + 1) -th bits to be decoded in the current frame occur with a certain probability according to the contents of the k and (k + 1) -th bits stored in the second memory 7b. It is assumed that the occurrence probability is held at the decoder side. For example, if the k-th bit of the previous frame is “0” and the (k + 1) -th bit is “0”, k,
And the (k + 1) th bit occurs on the transmitting side with a probability p as given in a table (see Table 1) stored in the ACS circuit.

[0033]

[Table 1] In the trellis diagram shown in FIG. 5, the k-th and (k + 1) -th stages correspond to the k-th and (k + 1) -th outputs of the decoding result, respectively. In FIG. 5, the k-th and (k + 1) -th bits of the surviving path of each state are “0” and “0” in the path merged with the state S ₀ in the (k + 1) -th stage, and “1” and “0” in the state S _1. ", in the state S _2" 0 "and" 1 ", which is in the state S _3" 1 "and" 1 ". Here, the third metric is calculated from the decoding result of the previous frame and the value p of the occurrence probability stored in the second memory 7b based on the following equation.

M ₃ = −w * log _e (p) where w is an appropriate coefficient.

Then, the path in the previous stage is read from the first memory, the branch metric is added, and the third metric is obtained only during the ACS calculation of the (k + 1) th stage.
M ₃ metric is added to the path metric. The updated path is written again to the first memory. When the decoding is completed, the maximum likelihood path is output from the output terminal as a decoding result.

That is, the conventional Viterbi decoder decodes the information sequence assuming that the occurrence probabilities of part or all of the information sequence are uniform. At this time, if the occurrence probabilities of part or all of the information sequence are not uniform, the conventional Viterbi decoder does not always perform optimal decoding. On the other hand, the Viterbi decoder according to the present embodiment has a feature that when the occurrence probability of a part or all of an information sequence is known on the decoding side, the decoding error rate can be reduced by using the information. .

Next, referring to the block diagram shown in FIG.
The configuration of a third embodiment of the Viterbi decoder according to the present invention will be described. In the above-described second embodiment, the third path metric is calculated by an equation corresponding to a sequence of decoded information whose occurrence probability is known, but this value always takes a constant value for the sequence of decoded information. When it is known, this can be written in the third memory 7c shown in FIG. 3, read out based on the information stored in the second memory 7b, and input to the ACS circuit 5B.

In this way, in the case of the second embodiment,
The calculation of the third metric every time can be replaced with the reading from the third memory 7c, which has a feature that the amount of calculation can be reduced.

Further, the configuration of the fourth embodiment of the Viterbi decoder according to the present invention will be described with reference to the block diagram shown in FIG. In the above-described second embodiment, the decoding result is input to the check circuit 9 and the decoding information stored in the second memory 7b is updated only when no error occurs in the decoding result by the check circuit 9. A third metric is calculated in accordance with the series of the decoded information stored in the second memory 7b. As the check circuit 9, a circuit for detecting an error based on a CRC bit added on the transmission side or a circuit for determining that an error has occurred when the value of the path metric of the decoding result exceeds a certain threshold value There is. In the second embodiment, when an error occurs in the decoding result, a third metric is calculated using erroneous decoding information and added to the path metric. this is,
Deteriorating the reliability of decoding. On the other hand, in the Viterbi decoder of this embodiment, even when an error occurs in the decoding result, the update of the second memory is controlled by the check circuit, so that the reliability of the decoding result is not deteriorated. There are features.

[0040]

As described above, according to the present invention, the predetermined metric obtained by smoothing the envelope information to improve the reliability of the branch metric and by using a part or all of the decoded information is used as the path metric. , The decoding error rate can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment according to the present invention.

FIG. 3 is a block diagram showing a configuration of a third embodiment according to the present invention.

FIG. 4 is a block diagram showing a configuration of a fourth embodiment according to the present invention.

FIG. 5 is a trellis diagram for explaining the operation of the second to fourth embodiments.

FIG. 6 is a block diagram showing the configuration of the entire communication system.

FIG. 7 is a block diagram illustrating a configuration of an encoder.

FIG. 8 is a block diagram illustrating a configuration of a conventional Viterbi decoder.

FIG. 9 is an explanatory diagram showing state transitions and input / output thereof in the encoder shown in FIG. 7;

FIG. 10 is a trellis diagram of the encoder shown in FIG. 7;

[Explanation of symbols]

 Reference Signs List 1 smoothing circuit 3 branch metric calculation circuit 5 ACS circuit 7 memory 7a first memory 7b second memory 7c third memory 9 inspection circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 13/00 H04L 1/00

Claims (3)

(57) [Claims] 1. A smoothing means for smoothing envelope information related to a received signal received, and a signal corresponding to a transition from a preceding state to a next state from an output of the smoothing means and the received signal. Branch metric calculation means for calculating a branch metric indicating a correlation between the path and the path, path storage means for storing a signal indicating a path leading to the state for all possible states, and a path indicating the likelihood of the path Path metric storage means for storing a metric, and adding a branch metric calculated by the branch metric calculation means to the path metric stored in the path metric storage means to generate an addition result corresponding to each state Then, these addition results are compared, the next path is selected, and the storage contents of the path storage means are updated by this path. Viterbi decoder and having an output means for outputting a decoding result and the ACS circuit for updating the stored contents, the selected path in the ACS circuit of the path metric storage means by said addition result corresponding to. 2. A branch metric calculation means for calculating a branch metric indicating a correlation between a signal corresponding to a transition from a preceding state to a next state from an input received signal; Path storage means for storing a signal indicating a path leading to the state, and path metric storage means for storing a path metric indicating the certainty of the path. The branch metrics calculated by the branch metric calculation means are added to generate an addition result corresponding to each state. An ACS circuit for updating the storage content, and a decoding result is determined from the path stored in the path storage unit. Decoding information storage means for storing part or all of signal information, wherein the ACS circuit converts a predetermined metric determined based on information stored in the decoding information storage means into the path metric. A Viterbi decoder characterized by adding. 3. The decoding device according to claim 2, further comprising a checking unit for determining whether or not the decoding result is correct, wherein when the decoding result is determined to be correct, the content of the decoding information storage unit is updated. 2. The Viterbi decoder according to 2.