JP4295871B2 - Error correction decoder - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an error correction decoder.
[0002]
[Prior art]
When an information sequence generated from a predetermined information source is transmitted through an erroneous transmission line, it is generally performed by encoding by adding redundancy. For coding, the information sequence is divided into fixed-length blocks, and each block is coded independently of the coding of the other blocks. There is a tree coding that involves.
[0003]
In the tree coding, coding performed in consideration of the encoder state σt at an arbitrary time t is called trellis coding, and the transition state of the code sequence obtained by trellis coding can be represented by a trellis diagram. It has been known. A linear trellis code is called a convolutional code.
[0004]
By the way, processing for terminating the trellis code is performed at the time of trellis encoding so that the decoding side knows the starting point when decoding the convolutionally encoded code sequence. This trellis termination process is a process of resetting the encoder state to the all-zero state. If the code is a non-recursive code, the trellis is added by adding 0 to the information bits as the number of shift registers in the encoder. Termination can be performed.
[0005]
However, in the case of recursive codes, trellis termination processing cannot be performed simply by adding such tail bits, and a complicated mechanism must be used as described below. In addition, a turbo coder is known as a configuration in which two recursive encoders are connected. However, in such a turbo coder, the state of the two encoders needs to be zero, so that trellis termination processing is further complicated. Become.
[0006]
FIG. 7 is a diagram showing the configuration of the turbo coder described above, in which a first encoder 10A and a second encoder 10B are connected via an interleave processing unit 11. The first encoder 10A includes a switch 12A, adders 13A and 16A, and delay units (D) 14A and 15A configured by shift registers. Similarly to the first encoder 10A, the second encoder 10B includes a switch 12B, adders 13B and 16B, and delay units (D) 14B and 15B.
[0007]
When the information bits I constituting the information sequence input to the first encoder 10A are encoded by adding parity bits, the switch 12A is closed, but when the encoding of the information bits I is completed, the switch 12A is closed. Is released and tail bits Y1 and Y2 are transmitted by the number of shift registers.
[0008]
The information bit I is also input to the interleave processing unit 11, and after data is rearranged based on a predetermined rule, it is input to the second encoder 10B and the same as the first encoder 10A. Processing is performed.
[0009]
However, when such a configuration is used, it is necessary to perform processing for switching the switches 12A and 12B at a predetermined timing in order to obtain tail bits. Since it is output from an output position different from that of the tail bit, a new circuit for combining these two bits is required, and the configuration of the encoder becomes complicated.
[0010]
There is also known a method of preventing performance degradation when termination processing is not performed by adding known information bits as tail bits without performing trellis termination processing of the turbo coder. However, in this case, it is necessary to add a sufficiently long tail bit, and as a result, there is a disadvantage that the coding rate is lowered.
[0011]
[Problems to be solved by the invention]
As described above, when performing trellis termination processing of a recursive code used in a turbo coder, the structure of the encoder becomes complicated, or when trying to avoid trellis termination processing, a sufficiently long tail bit is required and the code There was a problem that the conversion rate decreased.
[0012]
The present invention has been made paying attention to such a problem, and the object of the present invention is to simplify the configuration of the encoder by eliminating the processing of adding tail bits and to reduce the coding rate. An object of the present invention is to provide an error correction decoder that can be prevented.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, an error correction decoder according to a first aspect of the present invention corrects a code sequence obtained by systematic convolutional coding with respect to a received sequence received via a transmission path having an error. In the error correction decoder that performs the above, an addition comparison / selection unit that obtains a surviving path by performing processing from the received signal received in the past and receives data on the surviving path obtained by the addition comparison / selection unit Storage means for storing in correspondence with addresses in the order of signals received in the past from the received signal, and for the surviving path stored in the storage means, the address of the received sequence starting from the address of the most recently received signal Trace means for sequentially performing trace processing.
[0014]
According to a second aspect of the present invention, in the error correction decoder according to the first aspect, the storage unit stores data corresponding to a predetermined length of time, and the trace is stored for each of the stored predetermined time data. By repeating the tracing process by means, error correction is performed on the entire received sequence.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a turbo decoder to which an error correction decoder according to the present invention is applied. As shown in FIG. 1, the turbo decoder has two soft input / soft output decoders in order to increase error correction capability. The first soft input / soft output decoder 305 includes a memory 301A for storing information bits I of a received sequence received via a transmission path having an error in a code sequence obtained by systematic convolutional coding, and a reception The outputs of the memory 301B for storing the first parity bit Y1 of the sequence and the memory 310 for storing the external information likelihood are received as soft inputs, decoding processing is performed, and the soft decision results are output to the adder 309 To do. The adder 309 performs an addition operation using the output of the memory 301A, the output of the soft input / soft output decoder 305, and the output of the deinterleaver 304 that performs processing for returning the signal rearranged by the interleaver to the original arrangement. The result is output to an interleaver 303B that rearranges the signals.
[0016]
The second soft input / soft output decoder 306 also includes a signal obtained by rearranging the output of the memory 301A by the interleaver 303A, a signal obtained by rearranging the output of the adder 309 by the interleaver 303B, and a second received sequence. The output of the memory 301 </ b> C for storing the parity bit Y <b> 2 is received as a soft input, decoding processing is performed, and the soft decision result is output to the adder 307. The adder 307 outputs the output of the second soft input / soft output decoder 306, the signal obtained by rearranging the output of the memory 301A by the interleaver 303A, and the signal obtained by rearranging the output of the adder 309 by the interleaver 303B. An addition operation is performed as an input, and the result is output to the deinterleaver 304. Further, the hard decision output unit 308 converts the soft decision output (multi-valued data) of the second soft input / soft output decoder 306 into a corresponding hard decision output (binary data) and outputs it.
[0017]
FIG. 2 is a diagram showing the configuration of the first soft input / soft output decoder 305 and the second soft input / soft output decoder 306 described above. In FIG. 2, the first output of an ACS (Add Compare Select) / path metric difference calculation unit 401 is stored in a path memory 402 as a storage unit, and the second output is input in an ML (Most Likelihood) path trace / hard decision unit 403. The third output is connected to the competitive path trace / soft output calculation unit 404. The path memory 402 is directly connected to the competitive path trace / soft output calculation unit 404 via an ML (Most Likelihood) path trace / hard decision unit 403.
[0018]
An ACS (Add Compare Select) / path metric difference calculation unit 401 calculates a path metric by cumulatively adding the branch metrics obtained for all branches in the trellis diagram, and compares the path metrics of the paths. The path metric that gives the maximum likelihood is selected as the surviving path. By calculating the path metric difference Δ between the two paths flowing into each state, the path metric difference is obtained for all surviving paths.
[0019]
However, the ACS processing here is performed by inputting data in the reverse order to the reception sequence as shown in FIG. 3 using SOVA (Soft Output Viterbi Algorithm). That is, as indicated by → in FIG. 3, the ACS processing is performed from the received signal received at the most recent time point t to the time points t-1, t-2,. ing. As a result, the surviving path obtained by the ACS processing is stored in the path memory 402 in association with the address in the order of the signal received in the past from the signal received most recently.
[0020]
Next, the ML path trace / hard decision unit 403 and the competing path trace / soft output calculation unit 404 as the trace means start the address of the signal received most recently based on the surviving path stored in the path memory 403. Trace processing is executed in the order of reception series as points. Here, the conventional trace processing is called “trace back”, and the trace processing is performed on the received signal in the reverse order, that is, the most recently received data as the starting point. However, in the present embodiment, as indicated by → in the trellis diagram of FIG. 4, the trace processing is performed in the order of the reception sequence from the signal received most recently to the time points 0, 1, 2, 3, to t−1, t. It is characterized by performing. Here, the state in which the trace processing is started is performed from S0. This is because the initial state of the encoder is 0, so that the reliability is improved when the trace processing is performed from the state S0.
[0021]
In addition, the error correction decoder of this embodiment is configured by a turbo decoder, and it is necessary to store a received sequence in the path memory 402 in order to perform interleaving processing. On the other hand, since the reception sequence is stored in this way, the address position (state S0) for starting the trace processing can be easily searched. Furthermore, since the trace process may be performed up to the end of the received data, the present embodiment can be applied regardless of whether or not the tail bit at the end of the trellis is added to the received sequence.
[0022]
In practice, data corresponding to a predetermined length of time called a window is stored in the path memory 402, and trace processing is repeatedly performed by the tracing means for each of the stored predetermined time data, whereby the entire received sequence is stored. Error correction is performed.
[0023]
Further, in the final state (S3) of the trace processing, the reliability can be improved by taking a sufficiently long trace length.
[0024]
The trace processing of this embodiment will be described in detail below with reference to FIG. In the trace processing unit 705, the ML path 701 in the path memory 402 is selected by the ML path trace process, and the conflict path 702 is selected by the conflict path trace process. Next, the selected ML path 701 and the contention path 702 are compared and notified to the soft output calculation unit 703 that performs the soft output calculation on the position of the trellis transition that gives different decoding results. The soft output calculation unit 703 compares the path metric difference from the ACS / path metric calculation unit 401 with the currently stored value for the different bit positions of the ML path 701 and the competing path 702, and selects the smaller one. save. The output of the soft output calculation unit 704 and the code decoded by the ML path 701 are multiplied by the multiplier 704 and output as a soft decision output (multi-value data).
[0025]
FIG. 6 is a diagram showing a configuration of a turbo coder corresponding to the turbo decoder of the present embodiment. As can be seen from FIG. 6, since it is not necessary to add tail bits by using the above decoding method, a switch for performing a switching process when adding tail bits, a circuit for combining information bits and tail bits, and the like are not required. The configuration of the turbo coder is simplified. The initial value of the turbo coder is all zero.
[0026]
As described above, in the turbo decoder, ACS processing is performed in the reverse order of the reception sequence and trace processing is performed in the order of the reception sequence, so that the configuration of the turbo coder is simplified and the coding rate is reduced. The trellis code can be terminated without
[0027]
【The invention's effect】
According to the present invention, in the decoding process in the error correction decoder, the ACS process is performed in the reverse order of the reception sequence, and the trace process is performed in the order of the reception sequence. Therefore, it is necessary to add a tail bit at the time of encoding. This simplifies the construction of the encoder and allows the trellis code to be terminated without reducing the coding rate.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a turbo decoder to which an error correction decoder of the present invention is applied.
FIG. 2 is a diagram illustrating a configuration of a first soft input / soft output decoder 305 and a second soft input / soft output decoder 306 illustrated in FIG. 1;
FIG. 3 is a trellis diagram for explaining the procedure of ACS processing according to the present embodiment;
FIG. 4 is a trellis diagram for explaining a procedure of trace processing according to the present embodiment;
FIG. 5 is a diagram for explaining trace processing according to the present embodiment;
FIG. 6 is a diagram showing a configuration of a turbo coder corresponding to the turbo decoder of the present embodiment.
FIG. 7 is a diagram showing a configuration of a conventional turbo coder.
[Explanation of symbols]
301A, 301B, 301C,
303A, 303B ... interleaver,
304: Deinterleaver,
305, 306 ... soft input soft output decoder,
307 ... adder,
308: Hard decision output unit,
309 ... adder,
310 ... memory,
401... ACS / path metric difference calculation unit,
402: Path memory,
403 ... ML path trace / hard decision unit,
404: Competing path trace / soft output calculation unit.

Claims (2)

In an error correction decoder that performs error correction on a received sequence received via a transmission line having an error, a code sequence obtained by systematic convolutional coding,
Addition comparison selection means for obtaining a surviving path by performing processing from the received signal received in the past,
Storage means for storing the data about the surviving path obtained by the addition comparison selection means in association with the addresses in the order of the signals received in the past from the received signals;
With respect to the surviving path stored in the storage unit, a tracing unit that performs a trace process in the order of the reception sequence with the address of the signal received most recently as a starting point;
An error correction decoder comprising: Data corresponding to a predetermined length of time is stored in the storage means, and error correction is performed on the entire received sequence by repeatedly performing the trace processing by the trace means for each data stored for the predetermined time. The error correction decoder according to claim 1.

Images