JPH10178356A - Arithmetic processing unit and ratio station equipment using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic processing unit by which trace back processing of Viterbi decoding is executed in a small bit width at a high speed efficiently. SOLUTION: The arithmetic processing unit is provided with a memory 1 storing a path selection signal, a barrel shifter 3 shifting data read from the memory 1, a shift register 4 receiving a bit shifted toward the MSB by the barrel shifter 3, and a means 5 that converts data at a specific bit location of the shift register 4 to generate a shift number of the barrel shifter 3, and also with an address generating means 10 that stores a path selection signal at the same point of time divided into a plurality of groups to the memory 1 and provides an output of an address and with an address conversion means 7 that combines the address and the specific bit location value of the shift register 4 to generate a group read address. Then trace back of Viterbi decoding is conducted by a short bit width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device incorporated in a mobile communication device, a DSP device using the same, and a wireless station device incorporating the DSP device, and more particularly to an efficient Viterbi decoding process. Is made possible.

[0002]

2. Description of the Related Art In recent years, digital signal processors (hereinafter abbreviated as DSPs) have been widely used as equipment built-in processors in, for example, cellular phones in accordance with the digitization movement in the field of mobile communication. . In data communication on a mobile radio communication line, bit errors frequently occur, and therefore, it is necessary to perform error correction processing. As a method of error correction, there is a method of decoding a convolutional code generated from input bits by Viterbi decoding on a receiving side, and a DSP is used for this error correction processing.

[0003] In Viterbi decoding, maximum likelihood decoding of a convolutional code is realized by repeating a simple process of addition, comparison and selection, and finally by a traceback operation for decoding data. Hereinafter, the Viterbi decoding process will be briefly described.

[0004] A convolutional code is generated by mod2 addition of an input bit and a certain number of bits preceding it.
A plurality of encoded data are generated corresponding to one input bit. The number of input information bits that affect the encoded data is called a constraint length K, and the number is equal to the number of shift register stages used for mod2 addition.

[0005] The encoded data is determined by the input bits and the state of the preceding (K-1) input bits. This state shifts (transits) to a new state when a new information bit is input. However, the state in which transition is possible is determined by whether the new input bit is 0 or 1. The number of states is 2 ^{K -1 because} each of the (K-1) bits can take 1, 0.

In Viterbi decoding, a received encoded data sequence is observed, and the most probable state is estimated from all possible state transitions. For this purpose, every time encoded data (received data sequence) corresponding to one information bit is obtained, the signal distance (metric) of the path to each state at that time is calculated, and the same state is obtained. The operation of leaving the path with the smaller metric as the surviving path among the paths reached is sequentially repeated.

FIG. 17 shows a state S [n] and a state S [n + 2 ^K , which are one time earlier than state S [2n] (n is a positive integer) in a convolutional encoder having a constraint length ^{K. -2} ]
2 shows that two paths representing state transitions are extended. For example, in the case of K = 3, when n = 1, S [2], that is, S [1] with respect to the state of S10 (state where the preceding two bits are input in the order of “1” and “0”) ],
That is, transition from the state of S01 and the state of S [3], that is, the state of S11 is possible, and when n = 2, the state of S [4], that is, the state of S00 (the state represented by the lower 2 bits) is obtained. And S
It is possible to make a transition from [2], ie, the state of S10, and S [4], ie, the state of S00.

The path metric a is a distance between signals (branch metric x) between the output symbol of the path input to the state S [2n] and the received data sequence, and the state S at the immediately preceding time.
This is the sum with the path metric A, which is the sum of the branch metrics of the surviving paths up to [n].

Similarly, the path metric b has the state S [2n].
, The distance (branch metric y) between the output symbol of the path input to and the received data sequence, and the state S at the immediately preceding time
This is the sum with the path metric B, which is the sum of the branch metrics of the surviving paths up to [n + 2 ^K-2 ].

The path metrics a and b input to the state S [2n] thus obtained are compared, and the smaller path is selected as the surviving path.

In the Viterbi decoding, as described above, each processing of addition for obtaining a path metric, comparison of path metrics, and selection of a path is executed for 2 ^{K -1} states at each time.

Further, in selecting a path, a history of which path is selected is stored in a path select signal PS [i],
It is necessary to keep it as [i = 0 to 2 ^K−1 −1]. At this time, if the suffix (eg, n) of the state immediately before the selected path is smaller than the suffix (n + 2 ^K−2 ) of the state immediately before the other path that was not selected, PS [i] = 0, and if larger, PS [i] = 1. In the case of FIG.
Since n <(n + 2 ^K−2 ), when a ≧ b, the state S [n
+2 ^K-2 ] is selected, PS [S2n] = 1, and a <b
At this time, the state S [n] is selected, and PS [S2n] = 0.

Finally, when decoding by traceback, data is decoded while tracing the surviving path based on this path select signal.

Next, traceback processing will be briefly described with reference to FIG. FIG. 18 shows the path select signal PS for a state S [2n] (n is a positive integer) at a certain point in time.
Based on [2n], the state S [n] or the state S at the previous time
This shows a state where the path is traced back to [n + 2 ^K-2 ].

Generally, the state S [i] and the path select signal P
Using S [i], the previous state is S [i / 2 + PS
[i] × 2 ^K-2 ]. When a convolutional code terminated by tail bits is used, the path select signal becomes 0 when the immediately preceding decoded data is 0, and the path select signal becomes 1. Is when the decoded data at the previous time is 1. Therefore, this path select signal can be used as decoded data.

As shown in FIG. 15, an arithmetic unit inside a conventional DSP for Viterbi decoding includes a data memory 1 for storing a path metric, a path select signal, decoded data, and the like.
A barrel shifter 3 for shifting data read from the data memory 1, a first bus 2 connected to the data memory 1 for supplying data and transferring operation results, and a shift by the barrel shifter 3. Register 23, which holds the number of bits to be shifted, an arithmetic and logic operation circuit (hereinafter abbreviated as ALU) 26 for performing an arithmetic and logic operation, and a first latch for temporarily storing the value of the left input of ALU 26. 24, a second latch 25 for temporarily storing the value of the right input of the ALU 26, second registers 27 and 28 for temporarily storing the operation result, and a register 27.
Or a second bus for supplying data from the register 28
It has 12 and.

The number of shift bits of the barrel shifter 3 is expressed in a two's complement system. When the number is a positive number, the shift is to the right, and when the number is negative, the shift is to the left.

The operation of a trace-back operation when Viterbi decoding is performed on coded data that has been convolutionally coded and terminated with tail bits by this arithmetic unit will be described.

The conditions at this time are as follows: the constraint length of the convolutional code is K, the number of encoded information bits is n, the data memory 1, the first bus 2, the second bus 12, and the first latch 24. ,
It is assumed that the bit width of each of the second latch 25, the ALU 26, and the second registers 27 and 28 is 2K ^-1 bits.

Further, the path select signal PSt at time t
[i], (t = 0 to {(n-1) + (K-1)}, i = 0
~ {2 ^K-1 -1}) is the path memory PM [t] = {PSt
[2 ^K-1 -1], PSt [2 ^K-1 -2], ‥, PSt [1], P
St [0]} is packed into one word, and PM [t], (t
= 0 to {(n-1) + (K-1)}) in the data memory 1.

Also, the decoded data Y [i], (i = 0
.. {N-1}), one bit is stored in the data memory 1 as one word.

In the traceback operation, the data memory 1
, PM [t] is read out, the path select signal to be selected is shifted to the least significant bit (LSB) by the barrel shifter 3, and the LSB is extracted to be decoded data. The number of shifts is determined by the 2's complement of the selected state.
In this convolutional code, since it is set to terminate at the tail bit, it starts from state 0, and the state at the time before that is calculated by [i / 2 + PS [i] × 2 ^K−2 ]. Ask. Then, based on the obtained state, the next path select signal is set to L.
Determine the number of shifts when shifting to SB. By repeating such a procedure, a decoded data sequence can be obtained.

Next, the traceback operation will be described in steps.

Step 1: A fixed value "0" is stored in the second latch 25 to start from the state 0. The ALU 26 stores the value of the second latch 25 in the second register 27 as it is. Steps 2 to 10 are repeated n times while counting down the value of i from {(n−1) + (K−1)} to (K−1).

Step 2: The value of the second register 27 is stored in the first latch 24 via the second bus 12. AL
In U26, the two's complement of the value of the first latch 24 is obtained and stored in the second register 28.

Step 3: The value of the second register 28 is stored in the first register 23 via the first bus 2 (the number of shift bits for selecting the next path select signal).

Step 4: The path memory PM [i] is read from the data memory 1, shifted by the number of shift bits specified by the first register 23 by the barrel shifter 3, and stored in the second latch 25. The ALU 26 stores the value of the second latch 25 as it is in the second register 28 (the path select signal to be selected is shifted to the least significant bit [LSB]). Step 5: The value of the second register 28 is stored in the first latch 24 via the second bus 12, and the fixed value "1" is stored in the second latch 25. The ALU 26 calculates the logical product of the first latch 24 and the second latch 25 and stores the logical product in the second register 28 (only the LSB is extracted).

Step 6: The value of the second register 28 is stored in the data memory 1 as decoded data Y [i- (K-1)] (LSB becomes the decoded data).

Step 7: The fixed value "K" is stored in the first register 23.

Step 8: Change the value of the second register 27 to the second
, Stored in the first latch 24 via the bus 12, and outputs the value of the second register 28 to the barrel shifter 3 via the first bus 2, which is specified by the first register 23. The output is stored in the second latch 25. The ALU 26 calculates the logical sum of the first latch 24 and the second latch 25 and stores the result in the second register 28.

Step 9: The fixed value "-1" is stored in the first register 23.

Step 10: The value obtained by shifting the value of the second register 28 by the number of shift bits specified by the first register 23 by the barrel shifter 3 is stored in the second latch 25.
The ALU 26 stores the value of the second latch 25 as it is in the second register 27 (the previous state is calculated by the processing of steps 7 to 10).

As described above, in the conventional arithmetic unit, by performing the arithmetic operation by combining the barrel shifter 3 and the ALU 26, the trace in the Viterbi decoding of n information bits is performed.
The sub operation can be performed in (9n + 1) steps.

However, in this conventional arithmetic unit, the
There is a problem that the number of execution steps required for the back operation is large, and an arithmetic processing device for solving this problem is disclosed in, for example, JP-A-6-112848.

This device, as shown in FIG. 16, is connected to a data memory 1 for storing a path metric, a path select signal and the like, and supplies data and transfers operation results. A bus 2; a barrel shifter 3 for shifting a selected path select signal of the path memory data read from the data memory 1 to the most significant bit (MSB); and a shift input of the MSB output from the barrel shifter 3.
Also, a shift register 4 for performing data loading from the data memory 1 or storing data in the data memory 1 via the bus 2, and inverting values of a plurality of predetermined bit positions of the shift register 4. In addition, an inverter 29 is provided to the barrel shifter 3 as a shift bit number.

Note that the number of shift bits of the barrel shifter 3 is represented by a two's complement system.
Negative numbers shift left. The shift register 4 has the MSB on the shift input side.

The operation of the traceback operation when Viterbi decoding is performed on coded data that has been subjected to convolutional coding terminated with tail bits by this arithmetic unit will be described.

The conditions at this time are as follows: the constraint length of the convolutional code is K, the number of encoded information bits is n, and the bit width of the data memory 1, bus 2, and shift register 4 is 2 ^{K -1} bits. . The MSB of the output of the barrel shifter 3 is input to the shift input of the shift register 4, and
Inverts the upper (K-1) bits of the shift register 4 and outputs K bits obtained by adding "0" to the MSB of the output (K-1) bits as the number of shift bits of the barrel shifter 3.

The path select signals PSt [i], (t
= 0 to {(n-1) + (K-1)}, i = 0 to {2 ^K-1
-1}) is, as before, the path memory PM [t] = {PS
t [2 ^K-1 -1], PSt [2 ^K-1 -2], ‥, PSt [1],
PSt [0]｝, packed into one word, PM [t],
(T = 0 to {(n-1) + (K-1)}) and are stored in the data memory 1 and the decoded data Y
[i] and (i = 0 to {n-1}) are stored in the data memory 1 with one bit as one word.

In the traceback operation, the data memory 1
Is shifted by the barrel shifter 3, the path select signal to be selected is shifted to the MSB, and this path select signal is input to the shift register 4. At this time, the upper (K-1) bit of the shift register 4 is 1
This represents the previous state. So the next shift number is
It can be obtained by inverting this upper (K-1) bit. This shift number is generated by the inverter 29,
The path select signal to be selected in the next path memory is transferred to the MSB of the barrel shifter 3 output, and the shift register 4
To enter.

As a result of this repetition, the selected path select signal serving as decoded data is sequentially stored in the shift register 4 and stored in the data memory 1 every time a predetermined number of bits are stored.

The traceback operation will be described in steps.

Step 1: In order to start from the state 0, a fixed value "0" is loaded and stored in the shift register 4.

In the following steps 2 and 3, i
Is repeated n times while counting down from {(n-1) + (K-1)} to (K-1).

Step 2: The path memory PM [i] is read from the data memory 1 and the barrel shifter 3 converts the path memory PM [i] into an inverter 29.
And shifts the MSB of the output of the barrel shifter 3 into the shift register 4 (by this operation, the selected path select signal becomes the most significant bit [MSB]). Here, the upper [K-1] bits of the shift register 4 after the shift input indicate the previous state.
The inversion of the upper [K-1] bits is the basis for the number of shift bits for selecting the next path select signal).

Step 3: The contents of the shift register 4 are stored in the data memory 1 once each time 2 ^K-1 bits are decoded (the path select signal selected and stored in the shift register 4 is This is decoded data.)

As described above, in this apparatus, step 2
Selects the path select signal and calculates the previous state, and performs traceback processing of Viterbi decoding on n information bits {n + (n / ^2K-1 ) +1}.
Can be performed in steps.

[0048]

However, in these conventional processors, the bit width of the data memory or bus is 2 ^K-1 bits (K is the constraint length of the convolutional code to be decoded).
This is required, and there is a problem that as the value of K increases, the bit width of the data path needs to be increased accordingly.

The present invention solves such a conventional problem. Even when the value of 2 ^{K -1} is larger than the bit width of the data path, the traceback processing of Viterbi decoding can be performed quickly and efficiently. And a DSP using the arithmetic processing device, and a DS using the DSP.
An object is to provide a wireless station device incorporating P.

[0050]

Therefore, in an arithmetic processing unit according to the present invention, a path select signal at the same time is divided into a plurality of groups and stored in a data memory, and an address for reading this group is stored in an address. The address is generated by combining an address output from the generating means and a value of a specific bit position of the shift register to which the selected path select signal is sequentially input.

Therefore, traceback processing in Viterbi decoding can be performed with a bit width shorter than 2 ^K−1 bits, and high-speed and efficient arithmetic processing can be performed.

[0052]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a data memory for storing a path select signal, a barrel shifter for shifting data read from the data memory, and a data shifted to the MSB by the barrel shifter are provided. An arithmetic processing apparatus for performing Viterbi decoding, comprising: a shift register for inputting one bit; and data conversion means for converting data at a specific bit position of the shift register to generate a shift number in a barrel shifter. Address generating means for dividing the path select signal at the same time into a plurality of groups and storing the divided signals, and outputting an address of the data memory; and an address output from the address generating means and a value of a specific bit position of the shift register. Address for generating a group address to be read from the data memory based on the Are those provided with conversion means,
Traceback processing in Viterbi decoding can be performed with a bit width shorter than 2 ^K-1 bits.

According to a second aspect of the present invention, the path select signal is divided into a plurality of groups so that the suffix added to each of the path select signals in the group is continuous.
The address conversion means generates an address of the group using the address output from the address generation means and the value of a predetermined number of bit positions including the bit at the input end of the shift register. In the case of = 6, the path select signal of a total of 32 bits at the time point t is stored in the form of two words having a 16-bit width from PSt [0] to PSt [15] and from PSt [16] to PSt [31]. Is done.

According to a third aspect of the present invention, the data conversion means at this time generates a shift number in the barrel shifter by inverting a value of a predetermined number of bit positions excluding a bit at an input terminal of the shift register. When the bit width of each word of the path select signal stored in the data memory is n, the upper log ₂ n bits excluding the MSB of the shift register are inverted to generate the number of shifts in the barrel shifter. You.

According to a fourth aspect of the present invention, the path select signal is divided into a plurality of groups so that the suffix assigned to each of the path select signals within the group keeps a constant difference.
The address conversion means is configured to generate the address of this group using the address output from the address generation means and the value of the bit position excluding the bit at the input end of the shift register. In the case of 6,
Path select signals PSt [0], PSt with even subscripts
[2], ‥, PSt [30] and the path select signals PSt [1], PSt [3], ‥, PSt [31] whose suffixes are odd.

According to a fifth aspect of the present invention, the data conversion means at this time inverts the value of a predetermined number of bit positions including the bit at the input terminal of the shift register to generate the shift number in the barrel shifter. In this configuration, the upper log ₂ n bits including the MSB of the shift register are inverted to generate the number of shifts in the barrel shifter.

According to a sixth aspect of the present invention, the address conversion means at this time reads the value from the shift register necessary for generating the address of this group from the data memory in the immediately preceding group of the group. At this time, the data is obtained from a predetermined bit position of the shift register. This enables trace back processing of a pipeline structure.

According to a seventh aspect of the present invention, an ACS (Add, C
ompare, Select) operation means is provided, the path select signals output from the ACS operation means are sequentially stored in the shift register, and after the path select signals of the group are stored in the shift register, the path select signals are transferred for each group. Then, the group of path select signals described in claim 2 can be efficiently stored using a traceback processing mechanism.

According to the present invention, an ACS operation means for performing addition, comparison and selection operations in Viterbi decoding processing is provided, and a path select signal output from the ACS operation means is supplied to a plurality of shift registers including the shift register. 5. The method according to claim 4, wherein after sequentially storing the path select signal of the group in each shift register, the path select signal is transferred for each group and stored in the data memory. The group of the selected path select signals can be efficiently stored using the traceback processing mechanism.

According to a ninth aspect of the present invention, the ACS operation means is provided with an addition means comprising a plurality of full adders, and controls propagation of a carry signal output from a part of the full adders to the next stage. Enabling the addition means to be used as one or more accumulators.
The arithmetic adder can be used also as a general product-sum arithmetic adder.

According to a tenth aspect of the present invention, there is provided an arithmetic processing unit, a product-sum operation unit, an input / output unit for inputting / outputting data, and controlling the operation processing unit, the product-sum operation unit, and the input / output unit. A DSP having a control unit, wherein the arithmetic processing device according to any one of claims 1 to 9 is provided as the arithmetic processing device, and the arithmetic processing device is included in a normal DSP having a product-sum operation unit. It is possible to obtain a DSP that can efficiently perform traceback processing of built-in and Viterbi decoding.

[0062] According to the eleventh aspect of the present invention, there is provided an antenna unit for transmitting and receiving a signal, a reception radio unit for receiving a reception signal from the antenna unit, a transmission radio unit for transmitting a transmission signal to the antenna unit, A baseband signal processing unit that demodulates and decodes a received signal, encodes and modulates a transmission signal, a control unit that controls an antenna unit, a reception radio unit, a transmission radio unit, and a baseband signal processing unit; A radio station device having an input / output unit for inputting / outputting a signal,
The baseband signal processing unit is provided with at least a DSP that executes decoding of a received signal among functions performed by the baseband signal processing unit, and the DSP includes the arithmetic processing device according to claim 1. Thus, it is possible to obtain a wireless station device capable of efficiently performing a traceback process of Viterbi decoding.

According to a twelfth aspect of the present invention, the baseband signal processing section performs modulation and demodulation in a CDMA communication system, and can constitute a radio station apparatus performing CDMA communication.

According to a thirteenth aspect of the present invention, the input / output section of the radio station apparatus is provided with means for converting an audio signal into an electric signal and means for converting the electric signal into an audio signal. The wireless station device is configured to input and output an audio signal through the wireless communication device, and can be configured as a wireless mobile station that performs efficient Viterbi decoding processing.

The invention according to claim 14 uses this wireless station apparatus as a wireless base station, and can constitute a wireless base station that performs efficient Viterbi decoding processing.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) As shown in FIG. 1, an arithmetic processing unit according to a first embodiment includes a data memory 1 for storing a path metric, a path select signal, and the like, and
A bus 2 connected to the data memory 1 for supplying data and transferring operation results; a barrel shifter 3 for shifting data read from the data memory 1 via the bus 2;
The MSB of the output of the barrel shifter 3 is shifted in, and
The MSB is output to the address conversion unit 7 and the bus 2
Via the data memory 1 or the data load from the data memory 1.
Shift register 4 for storing data in data memory 1
A data conversion unit 5 that inverts the values of a plurality of predetermined bit positions of the shift register 4 and supplies the same to the barrel shifter 3 as the number of shift bits, and an address generation unit that generates an address to be supplied to the data memory 1 10 and address generator
And an address conversion unit 7 for converting a value input from the shift register 4 and outputting the converted value as an address of the data memory 1. The address generation unit 10 stores an address to be supplied to the data memory 1. Address register 6
And an increment register 9 for storing an increment value to be added to the address register 6, and an adder 8 for adding the value of the increment register 9 to the value of the address register 6 and storing the result in the address register 6. .

The number of shift bits of the barrel shifter 3 is represented by a two's complement system.
Negative numbers shift right. The shift register 4 sets the shift input side as the most significant bit (MSB).

Next, the operation of the trace-back processing when the convolutional code with the constraint length K = 6 terminated by tail bits in the arithmetic processing unit of this embodiment is Viterbi-decoded will be described with reference to FIGS. 4 and FIG.
Here, the number of encoded information bits is n.
The bit width m of the data path of the data memory 1, the bus 2, the barrel shifter 3, the shift register 4, the address register 6, and the like is assumed to be 16 bits (m = 16). Therefore, unlike the conventional example, the value of 2K ^-1 (= 32) is
It is larger than the bit width of tapas.

The data converter 5 has an inverter 21 as shown in FIG. The data conversion unit 5 includes:
Four bits excluding the MSB from the upper five bits of the shift register 4 are input, and the inverter 21 inverts the value of the input four bits (log ₂ m). Then, a 1-bit value "0" is added to the 4-bit MSB output from the inverter 21.
The bit value is output to the barrel shifter 3 as a control signal indicating the number of shift bits.

FIG. 4 is a diagram for explaining the operation specifications of the barrel shifter 3. The barrel shifter 3 converts the input signal according to the 5-bit control signal output from the data converter 5 as shown in FIG. A shift operation for shifting and outputting is performed.

The address converter 7 has the configuration shown in FIG. 5, and receives the 16 bits output from the address register 6 and the MSB of the shift register 4. The address conversion unit 7 outputs the upper 15 bits of the output of the address register 6 to the data memory 1 as it is, selects one of the LSB of the output of the address register 6 and the value of the MSB of the shift register 4, and Output as the LSB of the address to be supplied to the data memory 1.

FIG. 3 shows a state where the path select signal is stored in the data memory 1 having a width of 16 bits. Path select signal PSt [i] at time point t (i = 0 to 31)
As shown in FIG. 3A, a total of 32 bits are stored in the 16-bit data memory 1 in two words. That is, PSt [15: 0] is stored at address “2t + 0”, and PSt [31:16] at address “2t + 1”.
Is stored.

The point to be noted here is the number i representing the state.
Is represented by a 5-bit binary number, its MSB is 0.
(I = 0 to 15), the corresponding PSt
[i] is stored at the address "2t + 0" of the data memory 1, and when its MSB is 1 (i = 16 to 31), the corresponding PSt [i] is the address of the data memory 1. This is stored in “2t + 1”. The MSB of the shift register 4 is added to the address conversion unit 7 of this embodiment.
Is input for this reason. As described below, during the traceback process, the shift register 4
Of the shift register 4 are stored in the upper 5 bits of the address “2t” and “+0” of the address “2t”.
Or "+1" is given.

Also, the decoded data Y [j], (j = 0
~ {N-1}) packs 16 bits into one word,
Stored in the data memory 1.

In the traceback operation, the address generation unit
After 10 outputs the value stored in the address register 6,
By repeating the operation of adding the increment value of the increment register 9 to that value and re-storing it in the address register 6, addresses corresponding to "2t + 0" are sequentially output.
When the MSB of the shift register 4 is 0, the address conversion unit 7 sets “2t + 0”.
When B is 1, "2t + 1" is supplied to the data memory 1 as an address.

The data memory 1 reads the path memory based on the address output from the address conversion unit 7. This path memory is input to the barrel shifter 3, and the barrel shifter 3
, According to the control signal of the data conversion unit 5, converts the read path select signal in the read path memory into the MSB
Shift to The MSB is the shift register 4
To enter.

At this time, the upper 5 bits stored in the shift register 4 indicate the previous selected state. Of the upper 5 bits, the MSB is output to the address converter 7 to designate “+0” or “+1” at the next address, and the remaining 4 bits are output to the data converter 5. Inverted. This inverted 4
The bit value indicates the number of shifts required to shift the path select signal corresponding to the immediately previous selected state to the MSB in one word of the path memory stored in two words. .

By repeating such a procedure, the shift register 4 sequentially stores the selected path select signals to be decoded data, and transfers them to the data memory 1 when a predetermined number of bits are accumulated.

Next, the traceback operation will be described in steps.

Step 1: "0" is stored in the address register 6 as an initial value.

Step 2: The fixed value "2" is stored in the increment register 9.

Step 3: In order to start from the state 0, a fixed value "0" is loaded into the shift register 4 and stored.

For the next steps 4 and 5, j
Is repeated n times while counting down from {(n-1) +5} to 5.

Step 4: The address generator 10 outputs the value of the address register 6 to the address converter 7 and adds the value of the address register 6 to the value of the increment register 9 by the adder 8 to obtain the address register. 6 and updated. The address converter 7 outputs the upper 15 bits of the input value of the address register 6 to the data memory 1 as it is, selects the value of the MSB of the shift register 4, and supplies the LSB of the address to be supplied to the data memory 1. Output as The data memory 1 reads the path memory PM [i] from the address output from the address conversion unit 7 and outputs it to the barrel shifter 3 via the bus 2. The barrel shifter 3 shifts by the number of shift bits specified by the 5 bits of the output of the data converter 5 and shifts the MSB of the output of the barrel shifter 3 into the shift register 4 (the path select signal to be selected is the highest order) The bit is shifted to the bit [MSB], where the upper [K-1] bits (= 5 bits) of the shift register 4 after the shift input indicate the immediately preceding state. K-1] bit inversion is the basis for the number of shift bits for selecting the next path select signal.)

Step 5: The contents of the shift register 4 are stored in the data memory 1 once each time 16 bits are decoded.
To be stored. (The path select signal selected and stored in the shift register 4 is the decoded data.) As described above, in the arithmetic processing device of this embodiment, the training of the Viterbi decoding for n information bits is performed. The sub-back process can be executed in {n + (n / 2K ^-1 ) +3} steps. At this time, in step 4, the address generation unit 6 and the address conversion unit 7 supply an address corresponding to the value of the shift register 4 to the data memory 1, so that the path select signal PSt [i] at the time point t is shown in FIG. As shown in FIG. 3, even when the data is divided and stored in a plurality of words of the data memory 1, the traceback processing can be performed efficiently.

In the above description, of the upper 5 bits of shift register 4, the MSB is output to address converter 7 and the remaining 4 bits are output to data converter 5.
However, the upper 5 bits of the shift register 4 are output to the address converter 7, which outputs the MSB among them to the address converter 7, inverts the remaining 4 bits, and outputs You may comprise so that 0 may be added.

In the above description, a specific example in the case where the constraint length is 6 has been described. However, even if the constraint length is other than that, it is similarly implemented by making appropriate changes accordingly. be able to. For example, when the constraint length K = 7, as shown in FIG. 3B, the path select signal PSt [i] at the time point t is divided into four words and the data memory 1
To be stored. In this case, the upper two bits of the upper six bits of the shift register 4 are used for specifying the address, and the remaining four bits are used as the basis of the number of shift bits for selecting the next path select signal.

(Second Embodiment) The arithmetic processing device of the second embodiment has a configuration suitable for arithmetic processing of a pipeline structure.

This device has the configuration shown in FIG. This device differs from the first embodiment (FIG. 1) in the following three points.

The first point is the connection relationship between the data conversion unit 5 and the shift register 4. Unlike the first embodiment, the data conversion unit 5 is connected so that the upper 4 (log ₂ m) bits including the MSB of the shift register 4 are input.

The second point is a connection relationship between the address conversion unit 7 and the shift register 4. In this embodiment, not the MSB of the shift register 4 but the M
It is connected so that the fourth bit counted from SB, that is, the value of bit 12 is input. The third point is that the data memory 1
7A, the path select signal PSt [i] at the time t is stored in the data memory 1 (i = 0 to 31), as shown in FIG.
Out of the bits, PSt [i] (i = even number) indicates the address “2t
+0 ”, PSt [i] (i = odd number) is stored at address“ 2t +
1 ".

The point to be noted here is the number i representing the state.
Is represented by a 5-bit binary number, when the LSB is 0 (i = even number) instead of its MSB, the corresponding PSt [i] is stored in the address "2t + 0" of the data memory 1. When the LSB is 1 (i = odd number), the corresponding PSt [i] is stored in the data memory 1 at the address "2t + 1". In this embodiment, the MSB of the shift register 4 is not input to the address conversion unit 7 for this reason.

The reason why the data is connected so that the data of the fourth bit, not the fifth bit, counting from the MSB of the shift register 4 is input to the address conversion unit 7 is as follows.

This arithmetic processing device, as shown in FIG.
The operation is performed by the pipeline structure. For example, instruction # 1
In order to execute the shift in the cycle n + 1, it is necessary to supply an address to the data memory 1 at the beginning of the cycle n to perform a memory access. The LSB of the address of the data memory 1 containing the data to be shifted in the cycle n + 1 is the value shifted into the fifth bit from the MSB of the shift register 4 when the cycle n is executed. , At the beginning of cycle n, is located at the fourth bit counting from the MSB. Therefore, the fourth bit, not the fifth bit, counted from the MSB of the shift register 4 is connected to the address conversion unit 7.

The upper 5 bits stored in the shift register 4 indicate the previous selected state, and the value obtained by inverting the upper 4 bits in this state indicates that the path select signal is an even number. The number of shifts required to shift the path select signal corresponding to the immediately previous selected state to the MSB in one word of the path memory stored separately for odd numbers is shown.

Further, the decoded data Y [j], (j = 0
~ {N-1}) packs 16 bits into one word,
Stored in the data memory 1.

With this configuration, this apparatus performs traceback processing in the same processing steps as in the first embodiment even when performing arithmetic processing of a pipeline structure as shown in FIG. Becomes possible.

Next, the traceback operation will be described in steps.

Step 1: "0" is stored in the address register 6 as an initial value.

Step 2: The fixed value "2" is stored in the increment register 9.

Step 3: To start from state 0, a fixed value "0" is stored in the shift register 4.

In the next steps 4 and 5, j
Is repeated n times while counting down from {(n-1) +5} to 5.

Step 4: The address generator 10 outputs the value of the address register 6 to the address converter 7 and adds the value of the address register 6 to the value of the increment register 9 by the adder 8 to obtain the address register. 6 and updated. The address conversion unit 7 outputs the upper 15 bits of the input value of the address register 6 to the data memory 1 as it is, and selects the fourth bit value from the MSB of the shift register 4 and supplies it to the data memory 1. Is output as the LSB of the address to be processed. The data memory 1 stores the path memory PM based on the address output from the address conversion unit 7.
[i] is read and stored in an internal latch (not shown).

Step 4 ': The data memory 1 outputs the value of the internal latch (not shown) to the barrel shifter 3 via the bus 2. The barrel shifter 3 shifts the MSB of the output of the barrel shifter 3 by the shift bit number designated by the 5 bits of the output of the data conversion section 5 and shifts the shift register 4
(The path select signal to be selected is shifted to the most significant bit [MSB]. Here, the upper [K-1] bits (= 5 bits) of the shift register 4 after the shift input are performed.
Indicates the previous state. In addition,
The inversion of [K-1] bits is the basis for the number of shift bits for selecting the next path select signal. ).

Step 5: The contents of the shift register 4 are stored in the data memory 1 once every time 16 bits are decoded.
(The path select signal selected and stored in the shift register 4 is decoded data.)

Steps 4 and 4 'correspond to a memory access cycle and a shift execution cycle in the pipeline structure of FIG. 8, respectively.
Apparently, it appears to be executing in one step.

As described above, in the arithmetic processing unit of this embodiment, the path select signals PSt [i], (i = 0-3)
1) Since a total of 32 bits are stored in the data memory 1 evenly and oddly, the word of the path memory to be read is specified at the previous cycle even when the arithmetic processing is executed by pipeline. The traceback pipeline processing can be efficiently performed in the same processing steps as in the first embodiment.

The connection relationship between the address conversion unit 7 and the shift register 4 can be changed in design due to the difference in the pipeline structure. Also, the bit arrangement of the path select signal stored in the data memory 1 can change according to the value of the constraint length K of the convolutional code. For example, when the constraint length K = 7, as shown in FIG. 7B, the lower two bits of the value of the number i representing the state may be arranged so as to determine the stored address. At this time, the address conversion unit 7 may be designed so as to convert the address by inputting the corresponding 2-bit value of the shift register 4 as shown in FIG.

As described above, the design of this embodiment can be variously modified so as to be suitable for the constraint length K of the convolutional code to be decoded and the pipeline operation structure of the arithmetic processing unit.

(Third Embodiment) The arithmetic processing device according to the third embodiment performs not only traceback processing in Viterbi decoding but also ACS (Add, Compare, Select) operations, that is, addition, comparison, and selection operations. It can be performed efficiently.

This device, as shown in FIG. 10, stores the value of the path metric in the Viterbi decoding process together with the data memory 1 in addition to the same configuration from 1 to 10 as in the first embodiment (FIG. 1). A data memory 11, a register file 20 for storing the value of the branch metric, and a viterbi using the value of the path metric stored in the data memories 1 and 11 and the value of the branch metric stored in the register file 20. ACS for performing an ACS operation in decoding processing
An arithmetic unit 13 and a bus 12 connected to the data memory 1 for data transmission are provided.

As shown in FIG. 11, the ACS operation unit 13
Adders 14 and 15 for adding the value of the path metric output to the buses 2 and 12 and the value of the branch metric output from the register file 20, and the magnitude of the addition result output from each of the adders 14 and 15 A comparator 16 for performing comparison and outputting one bit of a control signal representing the comparison result to the shift register 4 and a selector 19 described later; a register 17 for temporarily storing the addition result output from each of the adders 14 and 15;
18 and the control signal output from the comparator 16
A selector 19 for selecting the smaller one of the two addition results stored in 17 and 18 and outputting the selected value to the bus 2 or 12
Is provided.

Next, an operation of performing an ACS operation in this device will be described.

The data memory 1 stores path metric values including the value of the path metric A shown in FIG. The data memory 11 stores path metric values including the value of the path metric B shown in FIG.
The register file 20 stores the values of branch metrics including the values of branch metrics x and y.

The adder 14 of the ACS operation unit 13 outputs the path metric A read from the data memory 1 via the bus 2.
Is added to the value of the branch metric x read from the register file 20, and the addition result is output to the comparator 16 and stored in the register 18. The adder 15
The value of the path metric B read from the data memory 11 via the bus 12 is added to the value of the branch metric y read from the register file 20, and the addition result is output to the comparator 16. Stored in register 17.

The comparator 16 outputs “0” when the addition result output from the adder 14 is smaller than the value output from the other adder 15, and determines whether the addition result output from the adder 15 is “0”. Is smaller than the value output from the other adder 14, the control signal 1 bit which becomes "1" is
And selector 19.

The selector 19 sets the value of this control signal to “0”.
If the value of the control signal is "1", the register 18 is selected, and the register 17 is selected via the bus 2 or 12,
The value stored in each register is stored in data memory 1 or
Store it in 11.

The shift register 4 stores the control signal output from the comparator 16, that is, the path select signal while shifting it bit by bit.

The above is the processing for one ACS operation.

For example, the constraint length K of the convolutional code to be decoded
In the case of = 6, if the above process is repeated 32 times, the ACS operation for one symbol of the received sequence can be performed. At this time, the selector 19 stores its output in the data memory 1 up to the first 16 times. The path select signal stored in the shift register 4 is stored in the data memory 1 via the bus 2. Next, in the last 16 ACS operations, the selector 19 stores its output in the data memory 11 via the bus 12. The 16 bits of the second half path select signal stored in the shift register 16 are
Stored in the data memory 1.

As a result, the path select signal is stored in the data memory 1 as shown in FIG. The ACS operation for one symbol of the received sequence is repeated for n symbols of the received sequence.

Thereafter, if traceback processing is performed according to the procedure described in the first embodiment, Viterbi decoding processing can be performed.

As described above, in this arithmetic processing device, the shift register 4 sequentially stores the path select signal output from the ACS arithmetic unit 13 bit by bit at the time of the ACS arithmetic operation. ACS calculation processing can also be performed efficiently. Further, since the shift register 4 can be used for both the ACS operation and the traceback processing, when this arithmetic processing device is realized by an LSI,
The cost can be reduced by reducing the chip area. In addition, since the operating frequency can be reduced by reducing the number of execution steps, the power consumption of the entire arithmetic processing unit can be reduced.

(Fourth Embodiment) The arithmetic processing unit according to the fourth embodiment uses the ACS operation of Viterbi decoding to execute the operation shown in FIG.
(A) enables storage of the path selector signal.

As shown in FIG.
There is provided a second shift register 21 for storing the path select signal output from the operation unit 13. Other configurations are the same as those of the third embodiment (FIG. 10).

This device performs exactly the same operation as the third embodiment except for the process of storing the path select signal. The process of storing the path select signal is performed as follows.

For example, the constraint length K of the convolutional code to be decoded
In the case of = 6, the ACS operation described in the third embodiment is repeated 32 times. At this time, the path select signal output by the ACS operation unit 13 is alternately output by the shift register 4 and the shift register 21 to 1 Stores bit by bit. That is, the path select signal is stored in the shift register 4 when the number is an even number, and is stored in the shift register 21 when the number is an odd number. 32
After the ACS operations are completed, the shift register 4
And the path select signal stored in the shift register 21 are sequentially stored in the data memory 1 via the bus 2.

At this time, the path select signal is as shown in FIG.
Is stored as shown in FIG. Therefore, after the ACS operation for one symbol of the received sequence is repeated for n symbols of the received sequence, traceback processing can be executed and Viterbi decoding can be performed in accordance with the procedure described in the second embodiment.

As described above, in this arithmetic processing device, the shift register 4 and the shift register 21 alternately store the path select signal output by the ACS operation unit 13 bit by bit during the ACS operation. Even in the processor having the pipeline structure shown in the second embodiment, not only traceback processing but also ACS operation processing can be performed efficiently.

Further, the shift register 4 can be used for both the ACS operation and the traceback processing.
When achieving I, the chip area can be reduced and the cost can be reduced. In addition, since the operating frequency can be reduced by reducing the number of execution steps, the power consumption of the entire arithmetic processing unit can be reduced.

In this embodiment, two shift registers 4 and 21 are provided, but the number of shift registers may be further increased. For example, if the shift register is designed to be provided with a total of four shift registers, the path select signal is sequentially stored one bit at a time in the four shift registers at the time of the ACS calculation when the constraint length K of the convolutional code to be decoded is K = 7. When the data is finally stored in the data memory 1 in order, the path select signal is stored as shown in FIG.

(Fifth Embodiment) The arithmetic processing device according to the fifth embodiment is obtained by improving the adder in the ACS operation unit according to the third and fourth embodiments.

As shown in FIG.
The operation unit 13 includes an adder 22 having a 32-bit width.
The addition of two data is executed simultaneously and in parallel on the upper side and the lower side. Therefore, functionally, the same operation as the configuration shown in FIG. 11 can be performed. That is, it can be operated as two 16-bit adders.

As shown in FIG. 14, this adder 22 includes 32 full adders therein, and each of the full adders adds corresponding bits 0 to 31. Bit 0
The adder adds the input X [0] and the input Y [0] to output a sum 0 [0] without carry and a carry signal Ci [0],
The full adder of bit 31 adds the input X [31], the input Y [31] and the carry signal Ci [30] of the preceding stage, and outputs a sum 0 [31] without carry. The full adders 1 to 30 add the input X, the input Y, and the carry signal Ci of the preceding stage, and output the sum 0 without carry and the carry signal Ci.

Of these, only the carry signal Co [15] output from the full adder of bit 15 is input to the AND circuit, and is transmitted to the full adder of bit 16 of the next stage via this AND circuit. Output as Ci [15]. AND
A control signal from a control unit (not shown) is also input to the circuit, and the control signal is configured to prohibit the propagation of the carry signal to the next stage.

Functionally, a 16-bit full adder of bits 0 to 15 corresponds to the adder 14 in FIG. 11, and a 16-bit full adder of bits 16 to 31 corresponds to FIG. Corresponds to the adder 15.

When performing the ACS operation, the value of the control signal input to the AND circuit becomes 0, and the propagation of the carry signal output from the full adder of bit 15 is prohibited. At this time, Viterbi decoding can be performed by exactly the same operation as in the third or fourth embodiment.

When this control signal is set to 1,
The adder 22 operates as a normal 32-bit adder.
Normally, a DSP has 32 accumulators for a product-sum operation.
Although an adder having a bit width equal to or larger than a bit is provided, the adder 22 can also be used as its accumulator.

As described above, the arithmetic processing device according to this embodiment can efficiently perform not only traceback processing but also ACS arithmetic processing. It can also be used for cumulative addition.

Therefore, when the arithmetic processing unit is implemented as an LSI, the chip area can be reduced and the cost can be reduced.

(Sixth Embodiment) In the sixth embodiment, a DSP having the arithmetic processing units of the first to fifth embodiments will be described.
Will be described.

The DSP is a one-chip microprocessor dedicated to digital signal processing and has a hardware configuration capable of performing a product-sum operation at high speed. In the DSP of this embodiment, as shown in FIG. In addition to the product-sum operation unit 62, the operation processing device 61 of the first to fifth embodiments, an input / output unit 63 that inputs and outputs data to and from the outside, an operation processing device 61, a product-sum operation unit 62, Control unit 64 that controls input / output unit 63
Are provided in one chip.

When the arithmetic processing unit 61 functions under the control of the control unit 64, the DSP 60 provides a DS for Viterbi decoding.
Acts as P, without increasing the bit width of the bus
Traceback processing for Viterbi decoding can be performed quickly and efficiently with a small number of steps.

The product-sum operation unit 62 is controlled by the control unit 64.
, The product-sum operation can be executed at high speed, and the operation in a digital filter, an FFT (Fast Fourier Transform) operation device, or the like can be efficiently processed.

As described above, the arithmetic processing units of the first to fifth embodiments can be incorporated in a normal DSP.

(Seventh Embodiment) In a seventh embodiment, a description will be given of a radio mobile station incorporating a DSP for performing Viterbi decoding.

This radio mobile station, as shown in FIG.
Antenna section 710 for transmission and reception, receiving section 721 and transmitting section 72
2, a baseband processing unit 730 that performs modulation and demodulation and encoding and decoding of signals, a speaker 751 that emits audio, and a microphone 752 that inputs audio,
A data input / output unit 753 for inputting / outputting data to be transmitted / received to / from an external device, a display unit 754 for displaying an operation state, an operation unit 755 such as a numeric keypad, an antenna unit 710, a radio unit 720,
Baseband signal processing unit 730, display unit 754, and operation unit 755
And a control unit 760 for controlling the operation.

The baseband signal processing section 730 includes a demodulation section 731 for demodulating a reception signal, a modulation section 735 for modulating a transmission signal, and a one-chip DSP 740.
Reference numeral 740 denotes a Viterbi decoding unit 742 including the arithmetic processing units according to the first to fifth embodiments, a convolution encoding unit 743 for convolutionally encoding a transmission signal, and an audio codec unit 744 for encoding and decoding an audio signal. A timing control unit 741 for transmitting a transmission signal from the demodulation unit 731 to the Viterbi decoding unit 742 and transmitting a transmission signal from the convolution encoding unit 743 to the modulation unit 735 by measuring transmission / reception timing is formed by software.

The control section 760 of the radio mobile station 700 controls the operation of the entire radio mobile station 700. For example, a signal input from the operation section 755 is displayed on the display section 754, and a signal input from the operation section 755 is displayed. In response to this, control signals for performing the operation of the outgoing / incoming call are output to antenna section 710, radio section 720, baseband signal processing section 730, etc. according to the communication sequence.

When voice is transmitted from radio mobile station apparatus 700, the voice signal input from microphone 752 is AD-converted (not shown), encoded by codec section 744 of DSP 740, and the encoded data is convolved. Input to encoding section 743. When data is transmitted, data input from the outside is input to the convolution encoding unit 743 via the data input / output unit 753. The convolution encoding unit 743 performs convolution encoding on the input data, and
Output to

Timing control section 741 rearranges input data and adjusts transmission output timing, and outputs the result to modulation section 735.

Data input to modulation section 735 is digitally modulated, D / A converted (not shown), and output to transmission section 722 of radio section 720.

[0154] Transmitting section 722 converts the signal into a radio signal and sends it to antenna section 710, which transmits the signal as a radio wave.

On the other hand, at the time of reception, the radio wave received by the antenna unit 710 is received by the reception unit 721 of the radio unit 720,
It is converted and output to demodulation section 731 of baseband signal processing section 730. The data demodulated by the demodulation unit 731 is subjected to data rearrangement and the like by the timing control unit 741,
The data is input to the Viterbi decoding unit 742, where it is decoded.

The data decoded by the Viterbi decoding unit 742 is
At the time of voice communication, voice is decoded by the voice codec unit 744, DA-converted, and then output from the speaker 751 as voice.

At the time of data communication, the Viterbi decoding unit 74
The data decoded in 2 is output to the outside via the data input / output unit 753.

FIG. 21 shows a CDMA radio communication system in which the configuration of the radio mobile station apparatus shown in FIG. 20 is partially changed, a spreading section 737 is provided in modulation section 735, and a despreading section 733 is provided in demodulation section 731. 2 illustrates a mobile station device. This device can perform CDMA communication by including the spreading unit 737 and the despreading unit 733.

As described above, this radio mobile station apparatus 700
Each part of the Viterbi decoder 742, the convolutional encoder 743, the audio codec 744, and the timing controller 741 is a D-chip of one chip.
Since it is formed by SP740 software, it can be assembled with a small number of parts. Further, since the Viterbi decoding unit 742 is formed by the arithmetic processing units of the first to fifth embodiments, it is not necessary to increase the bit width of the bus. Nevertheless, traceback processing of Viterbi decoding can be performed quickly and efficiently with a small number of steps.

Here, demodulation section 731 and modulation section 735
Are shown separately from the DSP740, but they are
It is also possible to configure with 40 softwares.

The DSP of the sixth embodiment is used as a DSP.
Using the SP, the convolutional encoding unit 743, the audio codec unit 744, and the timing control unit 741 can be configured by different components.

(Eighth Embodiment) In an eighth embodiment, a description will be given of a radio base station incorporating a DSP for performing Viterbi decoding.

This radio base station, as shown in FIG.
An antenna unit 810 having a transmitting antenna 812 and a receiving antenna 811; and a wireless unit 820 including a receiving unit 821 and a transmitting unit 822.
And a baseband signal processing unit 830 for performing signal modulation and demodulation and encoding and decoding, a data input / output unit 853 for inputting / outputting data to be transmitted / received to / from a wired line, an antenna unit 810, and a radio unit. 820, and baseband signal processing unit 83
0 and the like.

The baseband signal processing section 830 includes a demodulation section 831 for demodulating a received signal, a modulation section 835 for modulating a transmission signal, and a one-chip DSP 840.
Reference numeral 840 denotes a Viterbi decoding unit 842 including the arithmetic processing units according to the first to fifth embodiments, a convolution encoding unit 843 that convolutionally encodes a transmission signal, and a demodulation unit 831 that measures a transmission / reception timing to measure a reception signal. The Viterbi decoding unit 842 is formed by software with a timing control unit 841 that sends a transmission signal from the convolutional encoding unit 843 to the modulation unit 835.

In this radio base station 800, transmission / reception operations are performed under the control of control section 860, and data input from a wired line is input to convolutional coding section 843 via data input / output section 853. Then, after being subjected to convolutional encoding by the convolutional encoder 843, it is output to the timing controller 841.

The timing control section 841 adjusts the rearrangement of input data and the transmission output timing, and
5 and digitally modulated by the modulator 735,
After the D / A conversion, the signal is converted into a radio signal by the transmission unit 822 of the radio unit 820 and transmitted to the radio mobile station via the transmission antenna 812 by radio waves.

On the other hand, at the time of reception, the radio wave received by the reception antenna 811 is received by the reception unit 821 of the radio unit 820,
D-converted, and the demodulation unit 831 of the baseband signal processing unit 830
Is output to Then, the data demodulated by the demodulation unit 831 is subjected to data rearrangement and the like in the timing control unit 841 and input to the Viterbi decoding unit 842, where the decoded data is transmitted through the data input / output unit 853. Output to the wired line.

FIG. 23 shows a CDMA radio communication system in which the configuration of the radio base station apparatus shown in FIG. 22 is partially changed, a modulation section 835 is provided with a spreading section 837, and a demodulation section 831 is provided with a despreading section 833. 3 shows a base station device. This device can perform CDMA communication by including the spreading unit 837 and the despreading unit 833.

As described above, this radio base station apparatus 800
Since each part of the Viterbi decoding unit 842, the convolutional coding unit 843, and the timing control unit 841 is formed by one-chip DSP840 software, it can be assembled with a small number of parts. In addition, the Viterbi decoding unit 842 includes
Therefore, the traceback process of Viterbi decoding can be performed at high speed and efficiently with a small number of steps without increasing the bit width of the bus.

Here, demodulation section 831 and modulation section 835 are also used.
Can be configured by the software of the DSP 840, and the DSP of the sixth embodiment can be used as the DSP, and the convolution encoding unit 843 and the timing control unit 841 can be configured by separate components. It is.

[0171]

As is apparent from the above description, the arithmetic processing device of the present invention can perform traceback processing of Viterbi decoding in a small number of steps at high speed and efficiently without increasing the bit width of a data memory or a bus. Can be performed.

In the device for inputting the path selector signal obtained by the ACS operation to the shift register, the ACS operation processing of Viterbi decoding and the trace
It is possible to efficiently cooperate with the subbag process.

Further, the device in which the adder used for the ACS operation can be used also for the cumulative addition enables efficient use of the circuit.

In such an apparatus, the chip area can be reduced when implementing an LSI, and cost reduction and low power consumption can be realized.

Also, a DSP utilizing this arithmetic processing unit is used.
And the DSP can be used as a circuit for error correction to configure a radio mobile station apparatus and a radio base station apparatus. In these devices, in signal processing during communication, traceback processing of Viterbi decoding can be performed quickly and efficiently with few steps.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic processing device according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating a configuration of a data conversion unit in the arithmetic processing device according to the first embodiment;

FIG. 3 is a diagram showing a structure of data stored in a data memory in the arithmetic processing unit according to the first embodiment;

FIG. 4 is a diagram for explaining the operation of a barrel shifter in the arithmetic processing units according to the first to fifth embodiments of the present invention;

FIG. 5 is a diagram illustrating a configuration of an address conversion unit in the arithmetic processing device according to the first embodiment;

FIG. 6 is a block diagram illustrating a configuration of an arithmetic processing device according to a second embodiment of the present invention;

FIG. 7 is a diagram showing a structure of data stored in a data memory in the arithmetic processing unit according to the second embodiment;

FIG. 8 is a timing chart illustrating a pipeline operation in the arithmetic processing device according to the second embodiment;

FIG. 9 is a diagram illustrating a configuration of an address conversion unit in an arithmetic processing device according to a second embodiment;

FIG. 10 is a block diagram illustrating a configuration of an arithmetic processing device according to a third embodiment of the present invention;

FIG. 11 is a block diagram illustrating a configuration of an ACS operation unit of the operation processing device according to the third and fourth embodiments of the present invention;

FIG. 12 is a block diagram illustrating a configuration of an arithmetic processing device according to a fourth embodiment of the present invention;

FIG. 13 is a block diagram illustrating a configuration of an ACS operation unit of an operation processing device according to a fifth embodiment of the present invention;

FIG. 14 is a block diagram illustrating a configuration of an adder in an arithmetic processing device according to a fifth embodiment;

FIG. 15 is a block diagram illustrating a configuration of a conventional arithmetic processing device.

FIG. 16 is a block diagram showing a configuration of another conventional arithmetic processing device.

FIG. 17 is a state transition diagram (trellis diagram) showing paths of state transition of a convolutional encoder in Viterbi decoding;

FIG. 18 is a state transition diagram (trellis diagram) showing an operation to trace a path at the time of traceback in Viterbi decoding;

FIG. 19 is a block diagram of a DSP according to a sixth embodiment of the present invention;

FIG. 20 is a block diagram illustrating a configuration of a wireless mobile station device according to a seventh embodiment of the present invention;

FIG. 21 is a block diagram showing another configuration of the wireless mobile station device according to the seventh embodiment;

FIG. 22 is a block diagram illustrating a configuration of a wireless base station device according to an eighth embodiment of the present invention.

FIG. 23 is a block diagram illustrating another configuration of the wireless base station device according to the eighth embodiment.

[Explanation of symbols]

 1, 11 data memory 2, 12 bus 3 barrel shifter 4, 21 shift register 5 data conversion unit 6 address register 7 address conversion unit 8, 14, 15, 22 adder 9 increment register 10 address generation unit 13 ACS operation unit 16 comparator 17, 18 registers 19 selector 20 register file 23 first register 24 first latch 25 second latch 26 ALU 27, 28 second register 29 inverter 60, 740, 830 DSP 61 arithmetic processing unit 63 input / output unit 64 Control unit 700 Wireless mobile station device 710, 810 Antenna unit 720, 820 Wireless unit 721, 821 Receiving unit 722, 822 Transmitting unit 730, 830 Baseband signal processing unit 731, 831 Demodulating unit 733, 833 Despreading unit 735, 835 Modulation Unit 737, 837 Spreading unit 741, 841 Timing control unit 742, 842 Viterbi decoding unit 743, 843 Convolutional coding unit 744 Audio codec unit 751 Speaker 752 Microphone 753, 853 Data input / output unit 754 Display Unit 755 Operation unit 760, 860 Control unit 800 Wireless base station device 811 Receiving antenna 812 Transmitting antenna

Claims (14)

[Claims] 1. A data memory for storing a path select signal, a barrel shifter for shifting data read from the data memory, and an MSB by the barrel shifter
A shift register for inputting one bit shifted to
A data conversion means for converting data at a specific bit position of the shift register to generate a shift number in the barrel shifter. An address generating means for outputting an address of the data memory, wherein the select signal is divided into a plurality of groups and stored based on an address outputted from the address generating means and a value of a specific bit position of the shift register An address conversion means for generating an address of the group to be read from the data memory. 2. The path select signal is divided into a plurality of groups so that subscripts added to each of the path select signals in the group are continuous. 2. The arithmetic processing device according to claim 1, wherein the address of the group is generated using an address output from the means and a value of a predetermined number of bit positions including a bit at an input terminal of the shift register. 3. The data shift means according to claim 2, wherein said data converting means inverts a value of a predetermined number of bit positions excluding a bit at an input terminal of said shift register to generate a shift number in said barrel shifter. An arithmetic processing unit according to any one of the preceding claims. 4. The path select signal is divided into a plurality of groups so that a suffix added to each of the path select signals in the group keeps a constant difference, and the address conversion means includes: 2. The arithmetic processing device according to claim 1, wherein the address of the group is generated using an address output from the address generating means and a value of a bit position excluding a bit at an input terminal of the shift register. 5. The data conversion means according to claim 4, wherein said data conversion means inverts a value of a predetermined number of bit positions including a bit at an input terminal of said shift register to generate a shift number in said barrel shifter. An arithmetic processing unit according to any one of the preceding claims. 6. The shift register according to claim 1, wherein said address conversion means reads a value from said shift register necessary for generating an address of said group at a time when a group immediately preceding said group is read from said data memory. The arithmetic processing device according to claim 4, wherein the arithmetic processing device obtains the data from a predetermined bit position. 7. An ACS operation means for performing addition / comparison / selection operation in Viterbi decoding processing, wherein path select signals output from said ACS operation means are sequentially stored in said shift register, and said group is stored in said shift register. The arithmetic processing device according to claim 2, wherein after the path select signal is stored, the path select signal is transferred for each group and stored in the data memory. 8. An ACS operation means for performing addition / comparison / selection operation in Viterbi decoding processing, wherein a path select signal output from said ACS operation means is sequentially stored in a plurality of shift registers including said shift register. ,
The arithmetic processing device according to claim 4, wherein after the path select signal of the group is stored in each of the shift registers, the path select signal is transferred for each group and stored in the data memory. . 9. The ACS operation means includes an addition means including a plurality of full adders, and enables control of propagation of a carry signal output from a part of the full adders to a next stage,
9. The arithmetic processing device according to claim 7, wherein said adding means can be used as one or more accumulators. 10. A digital signal comprising an arithmetic processing unit, a product-sum operation unit, an input / output unit for inputting / outputting data, and a control unit for controlling the operation processing unit, the product-sum operation unit, and the input / output unit. A digital signal processing processor, comprising: the arithmetic processing device according to claim 1 as the arithmetic processing device. 11. An antenna unit for transmitting and receiving a signal, a radio reception unit for receiving a reception signal from the antenna unit, a radio transmission unit for transmitting a transmission signal to the antenna unit, and demodulation and decoding of the reception signal Baseband signal processing section for encoding and modulating a transmission signal, a control section for controlling the antenna section, reception radio section, transmission radio section and baseband signal processing section, and input and output of signals to and from the outside In the radio station device comprising an input and output unit, the baseband signal processing unit, of the functions performed by the baseband signal processing unit, at least, comprises a digital signal processing processor that performs decoding of the received signal,
A radio station apparatus, wherein the digital signal processor includes the arithmetic processing device according to claim 1. 12. The baseband signal processing unit according to claim 1, wherein
The wireless station device according to claim 11, wherein modulation and demodulation of the MA communication system are performed. 13. An input / output unit comprising: means for converting an audio signal into an electric signal; and means for converting an electric signal into an audio signal, wherein the radio station apparatus receives the audio signal through the input / output unit. The radio station apparatus according to claim 11, wherein the radio station apparatus outputs a signal. 14. The radio station device according to claim 11, wherein the radio station device is a radio base station.