JPS63153922A - Viterbi decoder - Google Patents

Abstract

PURPOSE:To make a minimum metric value node detection circuit unnecessary and to miniaturize a circuit scale, by obtaining an encoded output at every decoding cycle from a bit of maximum likelihood path information held at a trace storage part. CONSTITUTION:A path selection part 72 performs survival path selection by performing path metric arithmetic calculation and comparison of results, and outputs path selection signals SP1-SPn, and stores them on a path selection signal storage part 3 extending over path history length. A trace arithmetic part 74 finds the node information of maximum likelihood path by a mode switching signal MC, and stores it in a trace path storage part 75, and updates the information to the latest one. A decoding part 77 obtains the decoded output at every decoding cycle from the node information at the final stage of the maximum likelihood path held at the trace path storage part 75. The decoding of the decoder 77 is controlled so as to be performed for several times in one tracing cycle by a division control part 76.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (Fig. 1) Working Examples Example Structure of the Device ( (Fig. 2, Fig. 3) Basic operation explanation of the path trace method (Fig. 4) Basic operation explanation of the divided path trace method (Fig. 4, Fig. 5) Detailed operation explanation of the embodiment device (Fig. 4) Figure 6) Effects of the Input/Output Camote Trace Mode Invention [Summary] In a path tracing type Viterbi decoder that repeatedly traces the maximum likelihood path and stores it in the trace memory, and obtains the decoded output from the maximum likelihood path information. , l trace cycles are divided into multiple decoding cycles and tracing is performed to obtain decoding outputs.

[Industrial application field]

The present invention relates to a Viterbi decoder using a split path tracing method.

The Tabi decoder is a decoder used for maximum likelihood decoding of convolutional codes, and it selects the path with the closest code distance to the received code sequence from among multiple known code sequences as the maximum likelihood path, and It obtains decoded data in response to a path that has been detected, and because of its high error correction ability, it is used as an error correction device in satellite communications and other applications.

(Prior Art) In a conventional path trace type Tobi decoder, the node with the minimum path metric value is selected as a survivor at the previous stage based on the node number and the path selection signal corresponding to the node at the start of the trace. The most likely path is obtained by repeating the operation of finding the surviving node of the previous stage of the found node over the path history length (that is, the path memory length). The decoded output is obtained from the node number of the node that reached the node.

In this conventional path tracing type Viterbi decoder, one trace cycle in which a surviving path is traced once over the path history length is defeated by one decoding cycle to obtain a 1-bit decoding output. In order to obtain the output, a process must be performed to trace the surviving paths over l path history length, and the bit transmission rate decreases because the time required for the tracing is long.

In order to solve this problem, the present applicant
Both Japanese Patent Application No. 168758/1983 and Japanese Patent Application No. 168759/1983 filed on July 17, 1987 refer to the "Viterbi decoder".
A segmented path-tracing Viterbi decoder entitled . In these proposed Viterbi decoders, the maximum likelihood path traced in each trace cycle differs in shape from the maximum likelihood path obtained in the previous and subsequent trace cycles only at the beginning of the trace, and the latter half is Noting that the shapes almost match, decoding is performed using the already obtained maximum likelihood path without waiting for the end of one trace cycle, thereby improving the bit transmission rate. In other words, decoding is performed multiple times in one trace cycle, and in each trace cycle, the maximum likelihood path is updated, and in each decoding cycle, information about the node that reached the end of the maximum likelihood path obtained at that point is I am trying to get the decrypted output from .

[Problem that the invention seeks to solve]

The Viterbi decoder using the split path tracing method described above must start tracing from the node with the minimum path metric value, so additional circuits such as a minimum path metric value node detection circuit are required. There is a problem that the circuit size is somewhat large.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a divided path trace type Viterbi decoder with a reduced circuit scale.

[Problem that the invention seeks to solve]

FIG. 1 is a block diagram of the principle according to the present invention.

The Viterbi decoder using the split path trace method according to the present invention uses a distributor 71 that calculates branch metric values BM(11 to BM(711) for each node from the received code.
, a plurality of units 72 (11
72 (n), each unit 72 (13 to 72 (1 ml) calculates path metric link values for two paths leading to its corresponding node based on the branch metric value from the distributor 71. A surviving path is selected from the two paths by comparing the calculation results, and a path selection signal PS (11 to P S
A path selection signal storage unit 73 that stores path selection signals PS (1) to PS (111) of each node corresponding to each node over a path history table consisting of a predetermined number of stages. , for a given node, based on the path selection signal corresponding to the node, the surviving path calculates the previous node leading to the node, and based on the calculation result, calculates the previous node. a trace calculation unit 74 that traces the trace calculation unit 74; a trace path storage unit 75 that holds the node information obtained by the trace calculation unit 74 across the path history table; a division control unit 7 that performs control to divide the trace cycle into a plurality of decoding cycles;
6, and a decoding unit 77 that obtains a decoded output every decoding cycle from the maximum likelihood path information held in the trace path storage unit 75.

[For production]

The path selection signal PS (11 to P
S(nl) is sequentially stored in the path selection signal storage unit 73 over the path history table.The trace calculation unit 74 repeatedly calculates the node information of the maximum likelihood path and stores it in the trace path storage unit 75. As a result, the maximum likelihood path ↑ blue report held in the trace path storage unit 75 is continuously updated to the latest one.
A decoded output is obtained for each decoding cycle from the node information of the highest stage of the maximum likelihood path held in No. 5. The decoding by the decoding unit 77 is controlled by the division control unit 76 so that it is performed multiple times in one trace cycle, thereby improving the decoding processing speed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the overall configuration of a Viterbi decoder as an embodiment of the present invention. In this Viterbi decoder, the code constraint length is 4, and the number of nodes in the lattice structure is 8. In the figure, 1 is a distributor, 2 is an AC3 circuit, 3 is a path trace control section, 4 is a path memory, and 5 is a trace memory. The received code received from the transmitting side is input to the distributor 1, and the distributor 1 calculates the branch metric value RM (01
~BM(7) is calculated and given to the AC3 circuit 2.

The AC3 circuit 2 consists of 8 AC3 circuits provided corresponding to each node.
Consisting of parts 2(0) to 2(7). AC3 part 2(0)~2
(7) each consists of an adder, a comparator, and a selector,
AC5 parts 2(0) to 2(7) respectively have branch metric values BM (01 to BM (
71 is manually input from the distributor 1, and path metric values are input from the AC 3 section corresponding to two paths that can survive in the lattice structure. AC3 part 2 (O
) to 2(7) each add the path metric value one symbol before to the input branch metric to calculate a new path metric value for each of the two paths, and compare these path metric values with a comparator. The path selection signal P S (01 to P S f
? ) is output.

The path memory 4 receives the path selection signal P S from the AC3 circuit 2.
(0) to P S (71) are input and stored in the path history table corresponding to each node, and the path memory length becomes the path history table.

A detailed block diagram of the path trace control section 3 is shown in FIG. In FIG. 3, a trace counter 30 is a decrement counter for indicating a path trace position, and a path memory length PL is input as an initial setting input. The borrow output CY is connected to the load input terminal LD, so that the count value is sequentially decreased based on the size of the path memory length, and when it becomes 0, the original path memory length is repeated. The output of the trace counter 30 is used as an address signal for the path memory 4 and the trace memory 5. and an address for writing node information of the maximum likelihood path obtained by calculating this node number into the trace memory 5.

The input/output counter 31 has an increment counter for instructing the write address of the path selection signal according to the received code and the read address of the decoded output in the decoding cycle.
It is a counter, and the same (path memory length PL) is input as the initial setting input/output. Its carry output CY is led to the load input terminal LD, so the count value is sequentially increased, and the path memory length PL is input. 0 person output counter 31 that operates so as to repeatedly become 0 when the size of .
The output of is used as an address signal for path memory 4 and trace memory 5.

Therefore, the direction of addressing by the trace counter 30 and the direction of addressing by the human output counter 31 for the path memory 4 and the trace memory 5 are opposite to each other. That is, as shown in FIG.
The trace direction and the path selection signal writing direction for the trace memory 5 are opposite, and the content writing direction and the decoding output reading direction of the path memory of the traced node for the trace memory 5 are opposite.

The input/output counter 31 specifies the address when writing the path selection signals P S (0) to P S (7) obtained by the AC3 circuit 2 into the path memory 4, and specifies the decoded signal D.
Specifies the address when reading information used as EC from the trace memory 5.

A mode switching signal MC is led to the enable input terminal EN of the trace counter 30 via an inverter 37 and directly to the enable input terminal EN of the human output counter 31, and each counter 30, 31 receives its enable input. The operation is enabled when the terminal EN is at 11 levels.

Address signals ^DD 11) and ADD (21 are input terminals I N (1) and I of the selector 32, respectively) of the trace counter 30 and the human output counter 31
N+2). The selector 32 selects and outputs an input signal according to the mode switching signal input to its selection control terminal SEL, and when the mode switching signal MC is 1'', the address signal from the input/output counter 31 is output. 〇〇 (1) is selected, and when it is “0”, the address signal device 〇D (2) from the trace counter 30 is selected and sent to the address input terminal of the path memory 4 and via the flip-flop 39. It is sent to the address input terminal of the trace memory 5.The Flipflop 39 functions as a delay circuit, and allows access to each memory 4.5 by the same address signal output from the selector 32 to the path memory 4. This is to ensure that access to trace memory 5 is delayed by one clock CLK compared to access to trace memory 5.

The shift register 33 functions as an arithmetic circuit that calculates node numbers for searching the maximum likelihood path.
A 3-bit node number signal NO indicating the node number of the surviving node determined by the trace calculation is sent to the selection control terminal SC of the selector 34, and the selector 34
From among the 8-bit input signals input to the node, one bit corresponding to the node subjected to the trace calculation is selected. On the input side of the selector 34, a path selection signal LP S (0) corresponding to the eight nodes read out from the path memory 4 is provided.
~PS (71) is guided through the output buffer 351. The 1-bit output symbol selected by the selector 34 is guided to the serial input terminal of the shift register 33.

In addition, the path selection signal P S (0) to PS (71) from the AC9 circuit 2 is input to the pass memo +j4.
is led to its data input/output terminal via.

In addition to being led to the shift register 33, the output signal from the selector 34 is also led to the data input/output terminal of the trace memory 5 via a flip-flop 38 that provides a timing delay of one clock CLK, and further via an input buffer 362. It will be destroyed. The contents of trace memory 5 are read out via output buffer 361 and used as decoded signal DEC.

A mode switching signal MC is introduced to the control input terminal of the buffer circuit 35, and a mode switching signal MC is introduced to the control input terminal of the buffer circuit 36 via a flip-flop 40 that provides a timing delay of one clock CLK. It will be destroyed. As a result, when the signal applied to the control input terminal of the buffer circuit 35 is "L", the input buffer 35
2 is in the enabled state, and the output cover sofa 351 is in the disabled state, and the state is reversed at 0''.

Further, when the signal applied to the control input terminal of the buffer circuit 36 is "L", the output buffer 361 is enabled and the output buffer 362 is disabled, and when the signal is "0", the output buffer 361 is enabled and the output buffer 362 is disabled.

The operation of the embodiment device shown in FIG. 2 will be explained below, but in order to facilitate understanding of the operation of this embodiment device, we will first explain the path trace method and the divided path trace method, which are the basis of the present invention. The operating principle of decoding is shown in Figures 4 and 5.
This will be explained with reference to the figures.

Here, an example is taken where the constraint length is -4 and the number of nodes is 8.

Path Trace T's 1W Figure 4 is an explanatory diagram of path trace operation, and in the figure, the node numbers θ to 7 of each node (and their binary representation) are shown.
, the path metric value at that node, and the path selection signal in the path memory corresponding to that node are respectively drawn. Although it is desirable that the number of stages of the path memory be about 5 to 6 times the constraint length, here, to simplify the explanation, a case of 8 stages is shown.

First, the AC3 circuit 2 performs path metric calculation and selects a surviving path by comparing the calculation results, and the path selection signal P
S (01 to PS (7) (“0” or “1”) are output. This path selection signal P S (0) to PS (7
) is written to path memory. In this case, this path selection signal corresponds to the most significant bit MSB of the node number (binary representation) of the side selected as the survivor.

Although it is possible to start the trace from any node, preferably the node with the minimum path metric value is selected. In FIG. 4, the node with the path metric value 62 (node number 7) is the trace start node.

Now let the node number of the trace start node be No, (N, =
From O to 2''-'-1, the constraint length is set, and the coding rate R=〃), and the contents of the path memory corresponding to this node number N0 are set as PS. Here, the subscript corresponds to the number of stages of the trace. In Fig. 4, since the memory length is 8 stages, it can take values from O to 7.At the start of this trace, the AC3 circuit corresponding to node:No is at node:N.

Nl = 2'-"xPSo + N/2 where N
/2 means that the transition from the largest integer that does not exceed N/2 is selected as the surviving path. Therefore, next, the contents of the path memory (path selection signal) corresponding to node: N1: PS. This operation of reading is repeated and the decoding output is obtained from the node number of the node reached at the end by tracing over the entire length of the path memory. In that case, the last node number is expressed in binary and its M
Let SB be the decoded output.

To explain this in more detail using FIG. 4, in stage O, the node number N0=7 with the minimum path memory value is selected, and the latest path selection signal PS0 is set to "1" as the content of the corresponding path memory. are read out and based on them the old-style operation is performed, i.e. 4X1+3=7,
The node number N1 = 7 is obtained.

Therefore, in the next stage l, this node number N1 =
7, its corresponding path, and memory contents: PSL's “
1'', the node number N2=7 is calculated, and in the subsequent stage 2, the node number N:l''3 is calculated based on the node number NZ=7 and the contents of the path memory: PS!=0. Thereafter, the node number N is calculated in the same manner at stage 7. When this node number N,=4 is the last trace, the binary notation of node number 4 is "100", so the MSB "1" becomes the decoded output.Then, the node numbers at stages O to 7 are It is written to the trace memory 5 for each stage.

In this way, for example, node number N,
and the contents of its path memory: ps. If the node number is expressed in binary, this is the node:
By shifting N. one digit lower and setting the contents of the path memory of node: ps: ps to the highest position, the node: NI
For example, if the path selection signal is "0" in stage 2 of node number 7, the binary representation of node number 7 is "0".
111" from the most significant digit and shift the whole in the lower direction to obtain "011", which corresponds to 3 in decimal notation, so the node number to be traced in step 3 is 3. For these reasons, as will be described later, in the embodiment device, a circuit for performing old-style trace calculations can be configured with a shift register.

Note that in FIG. 4, the node number 4 (i.e. 100'') of the last reached node is derived from the last three bits of the traced path selection signal.Therefore, the last path selection signal is the MSB of the node number, This becomes the decoded output.Of course, other digit decoded outputs are also possible, and according to the Tavi decoding algorithm, the LSB is originally used as the decoded output.

2. Path tracing E ° ・ ・ U In the path tracing explanatory diagram in Figure 4, you can select any node to start path tracing, and even in that case, if the path memory length is long enough, the final The nodes reached are the same.

For example, when tracing is started from node number l, as shown by the dotted line in the figure, the path becomes the same as the above-mentioned maximum likelihood path in step 4, and thereafter the same path is followed to reach the final node. Further, as shown in FIG. 5, the same is true when a new received code is input and a new path selection signal is obtained from the AC3 circuit 2, and the latter half of the maximum likelihood path has the same shape.

In this way, for the maximum likelihood path to be traced, no matter which node the trace is started from as long as the path memory length is sufficient, the path trajectory differs only at the trace start side, and the path trajectory differs at the final stage. The trajectory is defeated. This means that it is not necessary to trace the maximum likelihood path from the trace start node to the final stage node every decoding cycle in order to obtain the decoded output. That is, once the maximum likelihood path is traced in one trace cycle, that information is stored, and this maximum likelihood path is sequentially updated by repeating the trace operation in the next trace cycle.

Then, decoding is performed multiple times within l trace cycle,
In each decoding, the final stage node information at the time of decoding is used to perform the decoding based on the maximum likelihood path information already stored. In this manner, the Tobi decoder of the divided path trace method performs decoding by dividing one trace cycle into a plurality of decoding cycles.

The detailed operation of the embodiment apparatus will be explained below using the time chart of FIG. 6. In FIG. 6, (a) shows the clock CLK, and (b) shows the soft-decision received code data D. Based on this, the AC3 circuit 2 outputs the path selection signal P.
Find S. (C) shows the write/continue output timing of the path selection signal to the path memory, (d) shows the write/continue output timing of the trace result information to the trace memory, (e) shows the mode switching signal MC, This mode switching signal MC switches the embodiment device between an input/output mode for writing path selection signals and reading decoded signals, and a trace mode for calculating maximum likelihood paths.

First, the input/output mode in which the path selection signal PS is written into the path memory 4 and the decoded signal DfiC is read from the trace memory 5 will be described.

Here, it is assumed that the path memory 4 and the trace memory 5 have already stored path selection signals and trace result information over the path history length through previous signal processing.

The input/output mode is performed by setting the mode switching signal MC to "L" for one clock cycle in response to the clock signal CLKI. As a result, the input/output counter 31 is enabled, the trace counter 30 and the shift register 33 are disabled, and the selector 32 receives the large address signal ADD"n-1" from the input/output counter 31.
Select and output. The path memory 4 contains data D”n
The path selection signal ps″n-1” obtained for the address signal ADD″n-1 is inputted via the human cover sofa 352, and this path selection signal PS″n-1” is applied to the address signal ADD″n-1.
” will be written to the address location specified.

On the other hand, the address signal ADD''n-1 from the selector 32
Since m is led to the address input side of the trace memory 5 via the flip-flop 39, the trace memory 5
From then on, at timing 2 of the next clock CL, trace result information is read out from the address position specified by the address signal ADD "n-1" via the output buffer 361, and this is the final stage node of the maximum likelihood path. Since this is information, a decoded signal DEC can be obtained from this.

Thus, the address of the trace memory 5 corresponding to the address of the path memory 4 where the path selection signal PS"n-1" is written, that is, ADD "n-1", the contents sold are the most likely. This is the final stage node information of the path. This is because after the path selection signal and trace result information have been written to the path memory 4 and trace memory 5 for one path history length, new contents are written from the beginning of the path so as to overwrite the previous contents. As a result, the content of the address location in the trace memory 5 corresponding to the address where the new path selection signal is written becomes the final stage node information of the previously traced maximum likelihood path.

(2) Trace mode The trace mode for tracing the maximum likelihood path is generated by setting the mode switching signal MC to "0" at the timing of the clock CLK2. As a result, the trace counter 30 and shift register 33 are enabled, the human output counter 31 is disabled, and the selector 32 receives the address signal ADD from the trace counter 30.
"+s" is selected and sent to path memory 4 and trace memory 5, respectively.

In trace state 1, an 8-bit path selection signal "l" is read from the address position of address signal ADD "m" in path memory 4 and is applied to selector 34 via output buffer sofa 351. Each of the 8 bits of the path selection signal corresponds to 8 nodes, and the selector 34 selects one of the 8 bits of path selection signal "I" designated by the node number signal from the shift register 33. The 1-bit path selection signal of the surviving node is selected and output. This selected l-bit path selection signal is input to the serial input terminal of the shift register 33 and is also sent to the trace memory 5 via the flip-flop 38.

The shift register 33 transfers the input path selection signal to the held contents (
Since the data is shifted in the MSB of the node number (node number), a trace calculation is performed on the node number of the cutting allowance (1), and the node number signal corresponding to the node number, which is the result of the calculation, is sent to the selector 34 again. This allows the selector 34 to select the path selection signal of the next surviving note in the next trace state 2.

On the other hand, since the path selection signal which is the trace result selected by the selector 34 is sent to the flip-flop 38,
The trace memory 5 includes flip-flops 38 and 4.
Due to the delay effect of 0, the trace result information T″m″ is written at the timing of the next clock CLK3.

At the next clock CL 3, the contents of the trace counter 30 are updated and its address signal becomes ADD'm+1'', and the path selection signals PS(0) to P S ( 71 is read out and the same operation as described above is performed.

In this way, in this trace mode, node numbers are traced twice in one decoding cycle. The number of times a node is traced in one decoding cycle can be adjusted by changing the period of the mode switching signal MC, and thereby the number of decodings in one trace cycle can be set to an appropriate value.

In the divided path tracing method of the present invention, when tracing one maximum likelihood path, the tracing is started from the node that the previous maximum likelihood path last reached. In this case, since the previous maximum likelihood path is uncorrelated with the current maximum likelihood path, it is not always possible to start tracing from the node with the minimum path metric value. As a result, it is possible that the error correction ability deteriorates, but in reality, if the path memory length is made somewhat longer, the path history will almost match at the final stage of the maximum likelihood path, so the error correction ability will hardly deteriorate. Not only does this eliminate the need for a minimum metric link value node detection circuit, but it also eliminates the need to know the starting position of a path when tracing it by dividing it into several symbols. The timing generation circuit for trace processing and the like can also be simplified.

〔Effect of the invention〕

According to the present invention, it is possible to realize a divided path trace method Tobi decoder which eliminates the need for additional circuits such as a minimum metric value node detection circuit and reduces the circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram according to the present invention, FIG. 2 is a diagram showing the overall configuration of a Tobi decoder as an embodiment of the present invention, and FIG. 3 is a path trace control section in FIG. 2. FIG. 4 and FIG. 5 are diagrams for explaining the path trace operation, FIG. 6 is a time chart for explaining the operation of the embodiment device of FIG. 2, and FIG. 7 is a diagram for explaining the address It is a figure explaining an access direction. l...Distributor 2...AC3 circuit 3.
...Path trace control unit 4...Path memory 5--Trace memory 30...Trace counter 31-
...Person output counter 32-selector 33...-
Shift register 34--Selector 35.36-
...Buffer circuit 37-...Inverter

Claims (1)

[Claims] 1. A distributor (71) that calculates branch metric values (3M(1) to 3M(n)) for each node from the received code.
, multiple units provided corresponding to each node (72(1)
~72(n)),
Each unit calculates path metric values for two paths leading to its corresponding node based on the branch metric values from the distributor, compares the calculation results, and calculates the path metric values for the two paths leading to its corresponding node.
A device configured to select a surviving path from two paths and output a path selection signal indicative of the surviving path; A path selection signal storage unit (73) that holds, for a given node, calculates the previous node on which the surviving path leads to the node based on the path selection signal corresponding to the node, and based on the calculation result, selects the previous node further on the basis of the calculation result. a trace calculation unit (74) that traces the surviving paths by repeating the calculation of A division control unit (76) that controls division into a plurality of decoding cycles, and a decoding unit (77) that obtains a decoding output (DEC) for each decoding cycle from the maximum likelihood path information held in the trace path storage unit. A Viterbi decoder comprising , .