KR100414152B1 - The Processing Method and Circuits for Viterbi Decoding Algorithm on Programmable Processors - Google Patents

Abstract

The present invention relates to a Viterbi decoding arithmetic circuit and a method for calculating the Viterbi decoding, which is one of the algorithms widely used for error correction for communication, in a programmable processor.

Description

The Viterbi Decoding Algorithm for Programmable Processors and the Computation Circuits for Performing the Computation Method

The present invention relates to a Viterbi decoding operation method and arithmetic circuit that can efficiently process Viterbi decoding, which is one of the widely used algorithms for communication error correction, in a programmable processor (digital signal processing processor, microprocessor, etc.). It is about.

Until now, a dedicated Viterbi processor is often used to correct communication errors, but there is an increasing need to implement a Viterbi decoder using a programmable processor in a dedicated hardware structure in order to reduce power consumption and ease correction.

In general, the overall configuration of the Viterbi decoding algorithm block consists of a branch metric calculation (BMC) block that calculates a difference between a received codeword and a codeword generated according to the state of the shift register of the encoder, and a branch metric generated from the BMC block. Add and Compare and Select (ACS) block that adds the current state value to the) value and compares the two values to select a smaller value, and finally a survivor path memory block that stores and decodes the path with the minimum distance selected from the ACS block. Etc. It is composed of three blocks.

The BMC block calculates a BM value from the data obtained by hard / soft decision. In a convolutional code having a code rate of 1/2, since the generated codeword is 2 bits, there are four types of BMs, which are classified into BM00, BM01, BM10, and BM11 according to codes generated by the encoder. Table 1 shows the BM values according to the steel sheet results.

BM code BM00 BM01 BM10 BM11 00 0 One One 2 01 One 0 2 One 10 One 2 0 One 11 2 One One 0

In case of using steel plate crystals, the input codeword and Hamming distance of each BM are calculated. In the case of soft decision, the Euclidean distance with the input data quantized in m bits is calculated and output. In the case of steel plate crystals, the maximum difference between each BM is 2, while in the case of soft crystals, the maximum difference is 14. Therefore, in case of using soft decision, even if an error occurs, the probability of wrongly selecting the survivor's path is reduced.

The soft decision Viterbi decoder has a structure in which the soft decision data S1 and S2 are input to the BMC operation block. If S1 and S2 are soft-determined data of 3 bits, the values of the respective BMs are obtained by Equation (1). Equation 1 is a method of calculating the BM value when using the soft decision.

Here, m is 3 since the soft-determined number of bits. That is, assuming that S1 is 5 (101 ₂ ) and S2 is 2 (010 ₂ ) as an input, each BM value is as shown in Table 2.

BM1 BM2 At the street BM00 5 2 7 BM01 5 5 10 BM10 2 2 4 BM11 2 5 7

As can be seen in Equation 1, when S1 and S2 are both 0 (000 ₂ ), it can be seen that the maximum difference is 14 and the value difference between BMs is larger than when using steel sheet.

The values of each BM on the grid are calculated through the BMC block. The calculated BMs are input to an ACS block to find a small value of a path input to the current state. In a code with a code rate of 1/2, two input paths exist in one state, so a path value having a smaller value by adding a previous path metric (PM) and the current BM becomes a PM of the next state.

1 is a butterfly structure showing a state transition relationship on a lattice diagram. S is the minimum distance to the current stage for calculating the PM, which is stored as SM (Survivor Memory). The ACS operation of a pair of butterfly structures that are continuously performed is represented by Equation (2). Equation 2 means to select the smaller of the two values.

For example, the first equation of Equation 2 is compared with the sum of S ₀ and BM _l and the sum of S ₁ and BM _h , and the smaller of these two values becomes the new S ₀ value.

When the length of the constraint field is K, there are 2 ^(K-1) states and it requires the ACS operation. That is, N becomes 2 ^(K-1) .

Figure 2 shows the ACS structure used in the dedicated Viterbi decoder, since one PE (Processing Element) performs an ACS operation in a state, theoretically, when a total of 2 ^(K-1) PEs are used, There is no correlation between, so all operations can be performed simultaneously. However, the actual DSP chip or dedicated ASIC chip is a heavy hardware burden, it does not have a number of PE. Each PE processes one of the states on the grid and performs an ACS operation to select a path with a smaller value by comparing the sum of the current path values and the accumulated path values. The current path value is obtained from data input in 3 bits in the BMC block. When the constraint field K = 7, since there are 2 ^(K-1) states in one stage, 64 PEs can be used to process one stage on the grid diagram every clock. And the PE compares the sum of the path value _h BM and cumulative value of the path, plus the value of the SM _h prior to the BM and the SM _{l l} from the higher value.

3 is a structure of a Viterbi-only traceback survivor path calculation circuit. The traceback method stores the decision bits obtained from the ACS operation in memory as much as the decoding depth, and then reads the values stored in the memory in a sequential manner and traces the survivor path of the previous stage from the current state value. .

As shown, the backtracking circuit consists of a memory, a multiplexer and a shift register. In case of using the convolutional encoder with the constraint length K = 7, the arbitrary state is selected as the current state value among the 64-bit data stored in the memory and used as the selection bit of the multiplexer. One bit selected as the multiplexer output is input to the shift register and used as a selection bit of the multiplexer for determining the next state value. The current state value to start backtracking can be chosen arbitrarily, but is usually used to start at zero in conjunction with the initialization of the shift register. The previous state is sequentially tracked in the same manner as described above, and then restored data is obtained after a decoding depth of a predetermined depth. Decoding depths are typically four to five times greater than the constraint field K, resulting in stable and reliable bit error rates. However, the greater the length of the constraint field, the more the number of operations becomes and the more the computational speed is constrained. That is, in order to decode 1-bit data each time, the operation corresponding to the decoding depth must be repeatedly performed. Indeed, the dedicated Viterbi decoder uses register swapping to solve this computational speed constraint. However, due to the hardware structure, the programmable DSP chip is not easy to implement.

The DSP chip developers are introducing new instruction structures in accordance with the trend of speeding up the Viterbi algorithm, but only limited instructions for performing some operations in the Viterbi algorithm do not significantly improve the execution speed. Commercially available DSP chips that support the acceleration of Viterbi decoding include the DSP Group's OakDSP, Texas Instruments' TMS320C55x and Motorola's DSP56600 family, all of which accelerate only the ACS computing portion. have.

4 shows hardware for performing an ACS operation in a conventional programmable processor (including a DSP). The ACS operation must undergo a pair of arithmetic operations, comparison, selection, and storage. That is, two pairs of PM and BM are added in the process of ①, the comparison is performed in the process of ②, and the signal is stored in the flag register. In the process (3), one bit of the comparison result signal is stored in the memory. In the process (4), the minimum distance determined during the comparison is shifted and stored in the memory. However, this series of steps can take several clock cycles each, depending on the specifications of the ALU and register file held by the DSP chip. In addition, in the case of ③, several cycles may be required because the selection signals of the ACS operation results for all states must be shifted and aligned before being stored in the memory in word units before the selection signals as the comparison results are stored in the memory.

The instructions of a commercial DSP having a specific specification for Viterbi decoding described above only support a comparison statement capable of comparing two pairs of data simultaneously. That is, the arithmetic operation before comparison and the selection and storage of the minimum distance after the comparison operation consume a large number of clock cycles by using several general DSP instructions. Therefore, the cycles taken in the process of ②, ③ of FIG. 4 are somewhat reduced. In addition, the VSL instruction of the DSP56600, which shifts and stores 1 bit when storing the survivor path, has no data dependency when pipelining and processing with the MAX instruction that performs the comparison. The calculations are done in different cycles, which does not take advantage of the VSL instruction. In particular, there are no specific instructions for calculating survivor paths that are the most difficult to handle on general-purpose DSP chips. In other words, no matter how fast ACS operation is performed, the bit rate at which data is restored depends on how fast the survivor path calculation is performed. Therefore, the conventional DSP chips are limited to low-speed data communication of less than 15kbps, such as voice service, and can not be used for high-speed data communication.

Accordingly, the present invention provides a calculation method and a circuit for executing the method to enable a fast Viterbi decoding operation on a programmable processor to eliminate the conventional inefficient aspects when implementing the Viterbi decoding algorithm based on a programmable processor. It aims to do it.

In addition, an object of the present invention is to achieve a one-chip of a multimedia terminal by enabling a high speed error correction algorithm of a portable terminal on a programmable processor by adding a minimum circuit to improve the performance of the programmable processor.

In order to achieve the above object, the present invention provides a Viterbi calculation method for processing four pairs of input data by two ACS operations, and after performing addition of each pair of input data, the resultant values are four 9-bit registers. Storing in the first step; Compares the result of the operation stored in the four 9-bit registers with the result output from the two 9-bit registers, and stores a small value in the shift register. A second step of storing bit by bit; At the same time, a third step of repeating the first step, inputting new four pairs of data, performing an addition, and storing the data in the 9-bit register; A fourth step of outputting two minimum values generated as a result of the ACS operation of the first four pairs of data from the shifter and storing them in a dual port memory through a bus; A fifth step of repeating the first to fourth steps to completely fill the 64-bit shift register and then transferring the output 64-bit value to the register file via the bus; If the register file has space to store 32 64-bit values, use a 64x1 multiplexer to select 1 bit of the 64-bits of the first address of the register file as 6-bit data of the destination register, and select the LSB of the destination register. And inserting the first bit into the left and shifting the existing six bits by one bit, wherein the Viterbi decoding operation method includes a sixth step of outputting one bit of the Viterbi decoded MSB.

In addition, four adders for performing addition of four pairs of 8-bit input data inputted to execute the Viterbi decoding calculation method; Four 9-bit registers for storing the result values of the operation performed in each adder; Two comparators for comparing arithmetic values output from two registers among the arithmetic values stored in the register and outputting a selection signal value for selecting a smaller value; Two multiplexers which receive two 9-bit data identical to the operation values output from the two registers input to the comparator and receive a bit of a comparison result of the comparator as a selection bit to select a small value; Two shifters for shifting the operation result of the multiplexer; A 64-bit shift register for storing the selection signal value output from the comparator and outputting the full signal when the comparator is full; A bus for passing the result value output from the shifter to the output value of the 64-bit shift register when the constraint length is 7; A dual port memory for storing shifted result values passed through the bus; A 32-bit register file that stores the value output from the 64-bit shift register passing through the bus and outputs the best value when the value is full; A 64x1 multiplexer for multiplying 64-bit data output from the 32-bit register file; The output of the 64x1 multiplexer selects and inserts 1 bit of the 64 bits of the first address of the register file into 6 bit data using the output, and shifts the existing 6 bits left by 1 bit to output MSB 1 bit out. And a Viterbi decoding arithmetic circuit in a programmable processor comprising a destination register.

1 is a diagram of a butterfly structure showing a state transition relationship on a general grid.

2 is a diagram showing an ACS structure used in a general dedicated Viterbi decoder.

3 is a diagram showing the structure of a general Viterbi-only traceback survivor path calculation circuit.

4 is a diagram illustrating a process of performing an ACS operation in a conventional programmable processor (including a DSP).

5 illustrates a dedicated Viterbi decoder architecture implemented with a conventional ASIC.

6 illustrates a block for performing a PACS instruction in accordance with the present invention.

7 illustrates the operation of an SLBIT instruction in accordance with the present invention.

Figure 8 is a view of the hardware structure for executing the PACS and SLBIT instruction in accordance with the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 shows the architecture of a dedicated Viterbi decoder implemented with an ASIC.

The programmable processor instruction set according to the present invention has a structure similar to that of a dedicated Viterbi decoder implemented with an ASIC and shows comparable performance. Instructions of the present invention are Packed Add and Compare and Select (PACS) and Shift Left BIT (SLBIT), which implement most of the Viterbi decoding algorithm with only two instructions. That is, one instruction for the ACS operation block and the survivor path calculation block of FIG. 5 is simultaneously executed in one clock cycle, so that the performance of the dedicated Viterbi structure is equal. For reference, as described in Equation 1, since the BMC operation block performs a simple arithmetic operation, the instruction for the BMC algorithm block can be easily implemented using the ALU of the general structure of conventional programmable processors without using any special instructions or hardware. Not taken into account.

FIG. 6 is a block diagram illustrating a PACS instruction for processing an ACS block of the Viterbi algorithm according to the present invention as one instruction. In the case of a 32-bit DSP chip, FIG. Two PE structures are shown. The computing unit can be implemented using conventional ones, with only the data path circuitry being implemented so that addition and comparison can be performed continuously by pipelining. Fig. 6 is a structure assuming that a register file is accessible in byte units (the latest DSP chips all have byte access), and two 32-bit word data are processed in byte units to perform two ACS PE roles. It is a structure. This instruction processing structure can output the results of four ACS operations every two cycles.

In operation, a, b, c, and d are the source operands of 8-bit registers containing BM values, and a ', b', c ', and d' are the Source operation of another 8-bit register. The result of the PM + BM operation is stored in the pipeline registers 1, 2, 3, and 4 through the adder Ex1, and the stored result is selected and selected after the comparison using the comparator (> / s). It performs the function of generating the signal 1 bit and outputs the selection result and selection signal. The selection result is shifted to the right by shifting 1 bit to the right by performing normalization to prevent the overflow caused by successive additions. It is stored in a large 64-bit shift register, which is shifted left by the number of PEs per clock cycle and sent to the PM.

Even in the case of programmable processors with multiple ALUs or 32-bit or later 64-bit or 128-bit programmable processors, the basic structure of FIG. 6 is simply extended in parallel to allow high-speed parallel processing because ACS operations are independent of each other. . For example, in the case of a 64-bit chip, four ACS PEs may be configured in one ALU, and in the case of a 128-bit chip, eight ACS PEs may be configured. In addition, more than two ALUs will eventually double the ACS PE.

Since a pair of ACS butterfly operation structures require four ACS PEs, the ACS operation source list of a commercially available programmable processor described above can be processed with two PACS instructions. As a result, ACS operation blocks can be processed three to five times faster in performance cycles than commercial programmable processors. The ALU structure processing method of the conventional programmable processor illustrated in FIG. 4 is a method in which arithmetic units having various functions in the ALU take arithmetic operations, but if the data flow path is released between the arithmetic units, the arithmetic flow of FIG. 6 is possible. . In other words, the structure of Fig. 6 is a data path structure and a 2 ^(K-1) bit shift register (shifter 0: selection) that allows continuous operation (comparison operation immediately after a pair of add operations) to the operation units of a conventional programmable processor. It can be implemented by adding only the signal storage, so the hardware burden is low and the operation of other DSP algorithms can be performed smoothly.

Next, SLBIT, another instruction according to the present invention, implements the output register for the traceback survivor path calculation circuit of FIG. 3 as it is, and FIG. 7 illustrates the operation of the SLBIT instruction. In other words, when the constraint length is K = 7, when 1 bit of the selection signal generated as a result of ACS operation gathers and fills the 2 ^(7-1) = 64 bit shift register, 64-bit data is stored in the register file serving as path memory (PM). The operation is performed as shown in Fig. 7 using the stored values as the source operand. By selecting a combination of the lower 6 bits of the destination, 2 ⁶ = 64 bits can be selected bit by bit, so that one bit of the source operand is selected and that 1 bit shifts to the left as it enters the destination sign bit (LSB) of the destination and is shifted to the left. Configure the bits, and repeat the same operation with these 6 bits. The iterative operation should be performed from the beginning (address 0) to the end (address 4 to 5 times of K). When the entire PM is traced back, a decoding result of 1 bit is output, and the output value is decoded. Raw data.

Referring to the operation of Fig. 7, first, the bit of the source operation indicated by the lower K bit of the destination operation is selected, then the original value of the destination operation is shifted by one bit, and the selected bit is targeted. Copy to LSB of.

In order to perform the operation of FIG. 7, it is possible to implement by simply adding a 2 ^(K-1) x1 multiplexer to a register file of a conventional DSP. The registers in the register file where the selection signals are stored must have access structures in units of 2 ^(K-1) bits or more (when K = 7, they must be accessible in 64-bit units by connecting two registers on a 32-bit chip). ). In general, the most restrictive K is 7, but it is better to configure the hardware by selecting enough K values so that it is easy to use even if it is not 7.

Through this, the conventional DSP can shift the data by shifting and index addressing, thereby reducing the processing of about 5 cycles to 1 cycle. However, in order to produce 1 bit of decoded data, the ACS operation is required since the constraint length K is generally 4 to 5 times, that is, 28 to 35 2 ^(7-1) = 64 bit PM values must all be traced back. Even if you do, it is difficult to perform fast operation. In the conventional DSP, it is not possible to store the PM values in the internal memory, move back one by one to the temporary registers, perform backtracking operations, and move 64-bits from the memory to the registers at a time, which consumes many execution cycles. As an example, if the memory access cycle is 3 and the number of bits of the memory data is 8, it takes approximately 8 x 3 + 5 = 29 cycles. Therefore, the PM values must be processed using a register file with an access cycle of 1. If the number of 64-bit registers in the register file is less than 28 to 35, the data between the internal memory and the register file must also be moved in parallel.

8 shows a circuit in the case of K = 7 for efficiently processing PACS and SLBIT instructions according to the present invention, comprising: four adders for adding four pairs of 8-bit input data to be input; Four 9-bit registers for storing the result values of the operation performed in each adder; Two comparators for comparing arithmetic values output from two registers among the arithmetic values stored in the register and outputting a selection signal value for selecting a smaller value; Two multiplexers which receive two 9-bit data identical to the operation values output from the two registers input to the comparator and receive a bit of a comparison result of the comparator as a selection bit to select a small value; Two shifters for shifting the operation result of the multiplexer; A 64-bit shift register for storing the selection signal value output from the comparator and outputting the full signal when the comparator is full; A bus for passing the result value output from the shifter to the output value of the 64-bit shift register when the constraint length is 7; A dual port memory for storing shifted result values passed through the bus; A 32-bit register file that stores the value output from the 64-bit shift register passing through the bus and outputs the best value when the value is full; A 64x1 multiplexer for multiplying 64-bit data output from the 32-bit register file; The output of the 64x1 multiplexer selects and inserts 1 bit of the 64 bits of the first address of the register file into 6 bit data using the output, and shifts the existing 6 bits left by 1 bit to output MSB 1 bit out. It consists of a destination resistor.

The upper structure of the system bus uses the PE structure of FIG. 6 as a detailed circuit for processing PACS commands and has two PEs. Therefore, it can be implemented with one ALU of 32-bit machine. The circuit arbitrarily represents the case where the constraint length K is 7, and the ACS operation unit can perform faster ACS operation if it is extended in parallel as described in the PACS instruction. In the first clock cycle, 8-bit data pairs are added from a pair of BMs and a pair of SMs to calculate the PMs to the current stage of both paths. In addition, the second clock cycle outputs a selection signal for selecting a small value by using a comparator for the magnitudes of the two pairs of PM values, and the selection signal is input to the multiplexer to select a smaller value among the input values. The selected result is stored in the LSB of the 64-bit register as 1-bit signals, respectively, and shifted to the right by 1 bit to normalize the survivors found to be small and stored in the SM.

FIG. 8 has a structure in which two small values output by independently processing two ACS operations are stored in a memory through a system bus, and such a memory serves as an SM for storing survivors and uses dual port memory. Reduce instruction execution cycles. The 64-bit shift register, which stores two bits of the select signal, also operates until it shifts left by two bits for every clock to fill the 64-bits. As shown in FIG. 8, when two ACS PEs are shifted in units of 2 bits (shifts in units of the number of ACS PEs), when 64 bits are filled, the data is divided into two 32-bit registers of a register file.

The stored PM is inserted through the hardware structure of the SLBIT instruction shown in the lower left part of FIG. 8 into a LSB into a destination register by selecting one bit of 64-bit data from the 64x1 multiplexer, which is simultaneously one bit to the left. Shifted. When the above operation is repeated and processed to the last data of the PM, the 7-1 = 6th bit value of the destination register becomes the last decoded 1-bit value.

The PACS instruction hardware can be implemented regardless of the number of bits of the programmable processor as long as the processing data can be accessed in 8-bit units, and the number of PEs when the processing bits of the programmable processor are large, that is, a 64-bit or 128-bit machine This increases the parallelism effect without adding special circuits. However, high speed operation is only possible in combination with the performance cycle of survivor path calculation.

As described above, no matter how fast the ACS is processed, if the survivor path calculation is late, the fast ACS operation cannot perform the performance. Therefore, survivor path calculation should be performed for storage media that can access 1 cycle, such as register file, and if there is not enough space for register file to act as the entire PM memory as shown in the lower part of Fig. 8, the internal RAM or cache The bottleneck can be eliminated by having a structure that allows easy parallel movement between the memory and the register file. In addition, the 6-bit shift register for calculating the survivor path at the bottom of FIG. 8 may use a general shift register, and must be processed in parallel with an ACS operation to perform high speed.

In addition, when the constraint field K is 7, 64 states exist, and since the ACS PE is 2 in the calculation circuit of the present invention, it takes 32 cycles. At the same time, the select signals are shifted left by two bits to fill the 64-bit shift register. The full 64-bit value is stored in two 32-bit registers in the register file, and the PACS operations continue in the same order.

On the other hand, if the register file has 4-5 times the space of K, the depth of PM, that is, 28-35 registers or a structure that can move data in parallel with memory, the SLBIT operation is processed in 28-35 cycles. As a result, one bit of data is decoded and output. Therefore, since PACS and SLBIT are independent of operations and have similar execution cycles, two commands can be executed simultaneously in the form of PACS∥SLBIT using the symbol '∥' (parallel operation) as in the case of TMS320C54x.

The shifter may be implemented by generating a data path to a shifter existing in a general arithmetic unit. The multiplexer receives a 6-bit selection signal and inserts it into the lower bits of the PM register that contains the data in the path memory. The multiplexer shifts the register to the left and performs the backtracking process. That is, since 1-bit data is output every 32 cycles, even a DSP chip having an operating frequency of 100 MHz can achieve 100,000,000 / 32 = 3.125 Mbps decoding performance, and since the code rate is 1/2, communication having a high data rate of 6.25 Mbps Can also be used in an environment.

Table 3 is a comparison table of Viterbi decoding performance cycles with the existing DSP chip when the constraint length K = 7. In the case of ACS operation, only the ACS butterfly operation program and execution cycle are described in the benchmark program of commercial DSP chips. Actually, 64/4 = 16 pairs of butterfly operations are repeated, and the result data is stored and branched when loop statement is operated. The number of data delay cycles consumed is denoted by α, which consumes approximately one third of the butterfly operation cycle.

Structure calculation block OakDSP ^TM TMS320C55x DSP56600 Structure of the present invention ACS Operation Block About 152 + α About 96 + α About 128 + α 32 Survivor Path Calculation 910 (= 26 x 7 x 5) 35 all About 1062 + α About 1006 + α About 1038 + α 35

Table 3 compares the performance cycles when the constraint length K = 7.

In addition, the conventional programmable processor performs ACS operation and survivor path calculation separately, but in the present invention, it is possible to simultaneously perform ACS and survivor path calculation, and thus the overall performance improvement may be about 30 times or more. The Viterbi dedicated programmable processor instruction circuit of the present invention is a computational unit that is widely used in existing DSP except for 2 ^(K-1) bit shift register, 2 ^(K-1) x1 multiplexers, indicated by the @ symbol in FIG. Consists of

As described above, the present invention is economical in terms of design cost because only the pipelining data path circuits that allow most of the existing calculation modules to be reusable and continuous operation are added to the chip fabrication. In addition, in the case of ACS operation blocks, the same structure can be easily extended by simply repeating the same structure.In case of survivor path calculation, considering enough K values, only 2 ^(K-1) × 1 multiplexer bits are larger and PM in a state It is a very flexible structure that only needs to increase the number of registers (2 for K = 7, 4 for K = 8 and 8 for K = 9) that are combined with each other to store a value.

In addition, the present invention shows that the transmission rate of 15Kbps in the DSP technology has a structure proposed by the present invention when operating on a DSP chip having a 100MHz operating frequency has a transmission rate of 6.25 Mbps, which is the required transmission rate of wireless multimedia services such as IMT-2000, 2Mbps Can also be used in an environment. In fact, the recent DSP process technology enables operation of hundreds of MHz or more, and the integration of register files is also very large. As the semiconductor process technology is further developed, the throughput can be higher, and the structures proposed in the present invention are parallel. It can be scaled up to several tens of Mbps. Therefore, the DSP technology, which is limited to voice data transmission, can be pushed to the area that can implement multimedia communication services such as CATV or VOD that meet the standards such as LMDS (Local Multipoint Distribution Systems) service or Multimedia Cable Network System (MCNS). There will be.

In addition, it is possible to reduce costs and reduce power consumption and downsizing of portable terminals by manufacturing and solving DSPs capable of performing this with communication modulation and demodulation in the FEC (Forward Error Correction). Can be achieved.

Claims (7)

In order to execute the Viterbi decoding algorithm, Four adders for adding four pairs of input 8-bit input data; Four 9-bit registers for storing the result values of the operation performed in each adder; Two comparators for comparing arithmetic values output from two registers among the arithmetic values stored in the register and outputting a selection signal value for selecting a smaller value; Two multiplexers which receive two 9-bit data identical to the operation values output from the two registers input to the comparator and receive a bit of a comparison result of the comparator as a selection bit to select a small value; Two shifters for shifting the operation result of the multiplexer; A 64-bit shift register for storing the selection signal value output from the comparator and outputting the full signal when the comparator is full; A bus for passing the result value output from the shifter to the output value of the 64-bit shift register when the constraint length is 7; A dual port memory for storing shifted result values passed through the bus; A 32-bit register file that stores the value output from the 64-bit shift register passing through the bus and outputs the best value when the value is full; A 64x1 multiplexer for multiplying 64-bit data output from the 32-bit register file; The output of the 64x1 multiplexer selects and inserts 1 bit of the 64 bits of the first address of the register file into 6 bit data using the output, and shifts the existing 6 bits left by 1 bit to output MSB 1 bit out. A Viterbi decoding arithmetic circuit in a programmable processor comprising a destination register. The method of claim 1, A Viterbi decoding arithmetic circuit in a programmable processor, characterized in that when the number of bits of input data increases, the circuits can be used in parallel. The method of claim 1, When the storage space of the 32-bit register file is insufficient, Viterbi decoding arithmetic circuit in the programmable processor, characterized in that it uses an internal RAM or cache memory, and has a structure that can move several at the same time. The method of claim 1, A Viterbi decoding operation circuit in a programmable processor having the same configuration as the circuit of claim 1 even if the number of bits of the first input / output data changes. The method of claim 1, Viterbi decoding arithmetic circuit in the programmable processor, characterized in that the same configuration as the circuit even if the number of the constraint field is changed delete A Viterbi decoding operation method of processing four pairs of input data by two ACS operations using the Viterbi decoding operation circuit of claim 1, A first step of performing addition of each pair of input data and storing the result in four 9-bit registers; Compares the result values stored in the four 9-bit registers with the result values output from the two 9-bit registers, and stores a small value in the shift register, and stores two bits of the comparison result selection bits in two bits in a 64-bit shift register. A second step; At the same time, a third step of repeating the first step, inputting new four pairs of data, performing an addition, and storing the data in the 9-bit register; A fourth step of outputting two minimum values generated as a result of the ACS operation of the first four pairs of data from the shifter and storing them in a dual port memory through a bus; A fifth step of repeating the first to fourth steps to completely fill the 64-bit shift register and then transferring the output 64-bit value to the register file via the bus; If the register file has space to store 32 64-bit values, use a 64x1 multiplexer to select 1 bit of the 64-bits of the first address of the register file as the 6-bit data of the destination register. And inserting into the LSB and shifting the existing six bits by one bit to the left, and outputting one bit of the Viterbi-decoded MSB.