JPS62151031A - Data processor - Google Patents

Data processor

Info

Publication number
JPS62151031A
JPS62151031A JP29425185A JP29425185A JPS62151031A JP S62151031 A JPS62151031 A JP S62151031A JP 29425185 A JP29425185 A JP 29425185A JP 29425185 A JP29425185 A JP 29425185A JP S62151031 A JPS62151031 A JP S62151031A
Authority
JP
Japan
Prior art keywords
parity
latch
barrel shifter
shifter
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29425185A
Other languages
Japanese (ja)
Inventor
Katsuhiko Nakagawa
克彦 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29425185A priority Critical patent/JPS62151031A/en
Publication of JPS62151031A publication Critical patent/JPS62151031A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the easiness of test such as decrease in test pattern by conducting the test of a barrel shifter at the inside only not using an external instruction data. CONSTITUTION:A constant generator 8 generates a constant data on a bus 1 at first. The data are latched in an input latch 2. Further, the data are shifted by a shifter 3 and the result is latched by an output latch 4. The parity for the value of the output latch is generated and if only one bit of the generated constant is brought into '1', the propriety of the barrel shifter is decided. That is, when a switching element or wire of the barrel shifter is not formed, the output is all '0' and the parity is made different. Further, when switching elements are short-circuited or two switching elements are conducted, the parity is made different. Moreover, the operation above is executed to all switching elements by the repetitive control of a shifter controller 7 and when a parity other than the object takes place, a parity latch 6 is set. After the repetition of the operation above, the parity latch is checked by a controller to check the propriety of the barrel shifter.

Description

【発明の詳細な説明】 （技術分野） 本発明はバレルシフタを有するデータ処理装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a data processing device having a barrel shifter.

（従来技術） 近年の集積回路技術の進歩に伴ない、マイクロプロセッ
サ等に代表される、データ処理装置は、よシ高速のもの
が求められている。(Prior Art) With recent advances in integrated circuit technology, data processing devices, typified by microprocessors, are required to be faster.

この高速化の要求によりマイクロプロセッサでもバレル
シフタが多用される様になった。Due to this demand for higher speeds, barrel shifters have come to be used frequently in microprocessors.

しかし、バレルシフタの検査をする場合、ｎｂｉｔのバ
レルシフタであればｎ２回シフト命令を実行する必要が
あり、テスト容易性の要請に反する事になる。これはｎ
ｂｉｔのバレルシフタは　ｎ２個のスイッチング素子に
より実現されるため、ｎ通りのデータに対し、ｎ通りの
シフト量でシフトする必要があるためである。この為長
大なテストパターンを必要とする。However, when inspecting a barrel shifter, if it is an n-bit barrel shifter, it is necessary to execute the shift command n2 times, which goes against the requirement for testability. This is n
This is because the bit barrel shifter is realized by n2 switching elements, so it is necessary to shift n types of data by n types of shift amounts. For this reason, a long test pattern is required.

（発明の目的）　　　・ 本発明の目的は、テスト容易性を向上させたバレルシフ
タを提供する事にある。(Object of the Invention) - An object of the present invention is to provide a barrel shifter with improved testability.

（発明の構成） 本発明の構成を第１図を用いて説明する。(Structure of the invention) The configuration of the present invention will be explained using FIG. 1.

第１図において、１・・・・・・内部データバス、２・
・・・・・シフタ入力ラッチ、３・・・・・・バレルシ
フタ、４・・・・・・シフタ出力ラッチ、５・・・・・
・パリティ生成器、６・・・・・・パリティラッチ、７
・・・・・・シフタ制御装置、８・・・・・・定数発生
器である。In FIG. 1, 1...internal data bus, 2...
...Shifter input latch, 3...Barrel shifter, 4...Shifter output latch, 5...
・Parity generator, 6... Parity latch, 7
. . . Shifter control device, 8 . . . Constant generator.

まず定数発生器で定数をデータバス上ｅこ発生する。こ
のデータを入力ラッチにラッチする。更にこのデータを
シ７りでシフトし、結果を出力う。First, a constant is generated on the data bus by a constant generator. Latch this data into the input latch. Furthermore, this data is shifted in a series and the result is output.

チにラッチする。latch on.

この出力ラッチの値のパリティを生成するが、もし、発
生する定数を１　ｂｉｔのみ”１″にしておけば、パリ
ティの値でバレルシフタの良否を決定出来る。つマシ、
バレルシフタのスイッチング素子又は配線が形成されて
いなければ出力は全て０になりパリティの値は異なる。Parity is generated for the value of this output latch, but if only one bit of the generated constant is set to "1", the quality of the barrel shifter can be determined based on the parity value. Tsumashi,
If the switching element or wiring of the barrel shifter is not formed, all outputs will be 0 and the parity value will be different.

又、スイッチング素子間がシ目−ト又は、２個のスイッ
チング素子が導通している場合も又、パリティは異なる
。Furthermore, the parity also differs when there is a gap between the switching elements or when two switching elements are electrically connected.

（以上の事は、１ｂｉｔのみ０の定数を使っても実現出
来る） 更に１以上の操作を全てのスイッチング素子に対して実
行する様に、シフト制御装置で繰返しの制御を行ない同
時に、目的外のパリティが発生した時にパリティラッチ
をセットする。以上の繰返し後に、パリティラッチを制
御装置で調べる事により、バレルシフタの良、否をチェ
ック出来る。(The above can also be achieved by using a constant with only 1 bit being 0.) Furthermore, the shift control device performs repeated control so that one or more operations are performed on all switching elements, and at the same time, Sets the parity latch when parity occurs. After repeating the above steps, by checking the parity latch with the control device, it is possible to check whether the barrel shifter is good or not.

（発明の効果） 本発明は、バレルシフタのテストを外部からの命令デー
タによらず、内部のみで行なう事が出来、テストパター
ンの減少、等、テスト容易性の向上に効果がある。′ （実施例） 次に第１、第２図を用いて本発明の一実施例を示す。(Effects of the Invention) The present invention is capable of testing the barrel shifter only internally without relying on external command data, and is effective in improving testability, such as reducing the number of test patterns. (Example) Next, an example of the present invention will be described using FIGS. 1 and 2.

今、第１図のデータ処理装置のシック制御装置・・・・
・・７が、第２図のフローチャート通シに動作すル事で
、バレルシフタのチェックが可能となる。Now, the thick control device of the data processing device shown in Fig. 1...
By following step 7 according to the flowchart shown in Figure 2, it is possible to check the barrel shifter.

第２図によると、まずｎｂｉｔの定数（ｎはバレルシフ
タのｂｉｔ長）を（ＯＯ・・・・・・０１）にする。According to FIG. 2, first, the nbit constant (n is the bit length of the barrel shifter) is set to (OO...01).

この定数に対し、シフト量をＯ−ｎまで（ｎは、バレル
シフタのｂｉｔ長）変化させシフトする。以上の繰返し
を（００・・・・・・０１）から（１０・・・・・・０
０）のｎ通シの定数に対して繰返す。The shift amount is changed to O-n (n is the bit length of the barrel shifter) with respect to this constant. Repeat the above from (00...01) to (10...0
Repeat for n constants of 0).

以上の操作の途中でパリティに異常があれば、第１図の
パリティラッチ・・・・・・６をセットする。更に、最
後にパリティラッチをチェックすれば、バレルシフタが
正常か異常かを判定出来る。If there is an abnormality in parity during the above operation, set parity latch 6 shown in FIG. Furthermore, by checking the parity latch at the end, you can determine whether the barrel shifter is normal or abnormal.

（発明のまとめ） 以上の様に本発明を用いる事により、長大なテストパタ
ーンを用いずにバレルシフタのテストが可能となりテス
ト容易性が改善される。(Summary of the Invention) As described above, by using the present invention, a barrel shifter can be tested without using a long test pattern, and testability is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例のブロック図、第２図はその動
作を示すフローチャート図である。 １・・・・・・内部データバス、２・・−・・・シフタ
人力ラッチ、３・・・・・・バレルシフタ、４・・・・
・・シフタ出力う。 チ、５・・・・・・パリティ生成器、６・・・・・・パ
リティラ。 チ、７・・・・・・シフタ制御装置、８・・・・・・定
数発生器。 第１図 開始 ７．・バレルンフタａｈｌ）ｉｔ長 第？図FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flowchart showing its operation. 1...Internal data bus, 2...Shifter manual latch, 3...Barrel shifter, 4...
...Shifter output. 5. Parity generator, 6. Parity generator. H, 7... Shifter control device, 8... Constant generator. Figure 1 Start 7.・Barrel lid ahl) IT chief? figure

Claims (1)

【特許請求の範囲】[Claims] バレルシフタを有する、データ処理装置において、シフ
トするデータを定数発生器で発生させシフト結果のパリ
ティを生成するパリティ生成器と、該パリティがあらか
じめ設定された値以外の時にセットされるラッチを有し
、かつ前記ラッチの値をデータ処理装置の制御部で検査
する手段を設け、更に、任意回数シフトを繰返す様に構
成した事を特徴とするデータ処理装置。A data processing device having a barrel shifter, including a parity generator that generates data to be shifted using a constant generator and generates parity as a shift result, and a latch that is set when the parity is a value other than a preset value, A data processing device further comprising means for checking the value of the latch by a control unit of the data processing device, and further configured to repeat the shift an arbitrary number of times.
JP29425185A 1985-12-25 1985-12-25 Data processor Pending JPS62151031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29425185A JPS62151031A (en) 1985-12-25 1985-12-25 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29425185A JPS62151031A (en) 1985-12-25 1985-12-25 Data processor

Publications (1)

Publication Number Publication Date
JPS62151031A true JPS62151031A (en) 1987-07-06

Family

ID=17805304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29425185A Pending JPS62151031A (en) 1985-12-25 1985-12-25 Data processor

Country Status (1)

Country Link
JP (1) JPS62151031A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04352518A (en) * 1991-05-30 1992-12-07 Matsushita Electric Ind Co Ltd Arithmetic unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04352518A (en) * 1991-05-30 1992-12-07 Matsushita Electric Ind Co Ltd Arithmetic unit

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