JP2875364B2 - Gain control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain control circuit, and more particularly to a gain control circuit in a semiconductor integrated circuit.

2. Description of the Related Art In the conventional example shown in FIG. 9, among the transistors Q3 to Q8 constituting the double-balanced differential amplifier 1, the bases of the transistors Q4 and Q5 of the upper differential pair transistors Q3 and Q4 and Q5 and Q6. Connect the variable current source 3 and
Connects the emitter of Q2. On the other hand, transistor Q3
The base of Q6 is connected to the constant current source 2 and to the emitter of the transistor Q1. Transistors Q1, Q2
Is connected via a terminal 5 to a reference voltage source, to which a reference voltage Vref is applied. Input signals of the double-balanced differential amplifier 1 enters the terminals 5 and 6, after being amplified by the differential amplifier 1, is outputted as a current I ₅ from the current mirror circuits 7 and 8 to the current mirror circuit 10, Q10 together is output as a current I ₄ from the current mirror circuit 9, Q9, their current difference (I ₄ -I ₅₎ the output voltage Vo is taken out by flowing through the resistor 11. During that time, the input signal is subjected to gain control in the upper differential pair transistors Q3, Q4 and Q5, Q6.

Here, explaining the gain control operation with respect to the transistors Q3, Q4, firstly, by increasing the current value I ₂ of the variable current source 3, the smaller the ratio of I ₁ / I _2, low emitter potential of the transistor Q2, the transistor The emitter potential of Q1 rises and passes through transistor Q3 to make current mirror circuits 7, 8
The level of the input signal output to is increased, resulting in an increase in gain. On the other hand, when the current value I ₂ of the variable current source 3 is reduced, the ratio of I ₁ / I ₂ increases, and the transistor
The input signal level output to the current mirror circuits 7 and 8 through Q3 decreases, and the gain decreases.

Problems to be Solved by the Invention In the above embodiment, even when the current I _{2 is set} to 0, the transistor
Current flows because Q2 must supply the base current of transistors Q4 and Q5. Therefore, when setting the amount of gain attenuation, the base current of the transistors Q4 and Q5 must be taken into consideration, and there is a disadvantage that the setting becomes more difficult. In addition, there is a disadvantage that the attenuation ratio between the transistors Q1 and Q2 cannot be sufficiently obtained.

To explain the latter disadvantage in more detail, first, generally, the Vf of a transistor is represented by k being the Boltzmann constant, T being the absolute temperature,
Assuming that q is a charge, I is a forward current of the diode characteristic of the transistor shown in FIG. 10, and Is is a reverse current, Vf = (kT / q) ln (I / Is). Even when the gain is reduced to the maximum, the current of the transistor Q2 is
The current flows as much as the base current of Q4 and Q5 is supplied (for example, 0.2 μA in FIG. 10). At this time, assuming that the current of the transistor Q1 is 100 μA in FIG. 10, the voltages Vf1 and Vf2
Is small as shown in FIG. If the current of the transistor Q2 does not flow, the difference increases as shown in (b).

Therefore, if R1 = R2 = R3, the attenuation ATT is expressed by the following equation: ATT = 20log (Vo / Vi) = 20log [2 / {1 + exp (qVc / kT)}] Due to the small Vc, the attenuation ATT cannot be made sufficiently large. Incidentally, in FIG. 9, if I ₁ ′ = I ₁ = I ₂ = I ₂ ′ and I _b = I _1/2 , the maximum attenuation ATT becomes ATT = 20 log [2 / (1 + I _1/2 I _b) )] Where I ₁ = 100 μA and I _b = 100 / β (β is the current amplification factor of the transistor = 120), ATT = −29.7
In dB, only a maximum attenuation of -29.7 dB can be obtained.

The present invention has been made in view of such a point,
It is an object of the present invention to provide a gain control circuit that enables easy setting of a gain attenuation amount and obtains sufficient attenuation, and does not change the attenuation amount with respect to variations in _hfe of a transistor or a change in temperature.

Means for Solving the Problems To achieve the above object, a gain control circuit according to the present invention comprises: a first differential pair comprising first and second transistors of an NPN type having emitters connected in common; A second differential pair comprising third and fourth NPN transistors, a fifth NPN transistor having a collector connected to the emitters of the first and second transistors, and a third transistor and a fourth transistor 6th NPN type with collector connected to emitter
A third differential pair of transistors; a constant current source connected to the emitters of the fifth and sixth transistors; an input signal terminal connected to the bases of the fifth and sixth transistors; An NPN-type seventh transistor in which the emitter is connected to the collector and the collector is connected to the power supply line; an NPN-type eighth transistor in which the emitter is connected to the collector of the third transistor and the collector is connected to the power supply line; A ninth transistor of a PNP type connected to the bases of the second and third transistors and having the collector connected to the ground, a collector connected to the emitter of the ninth transistor, the base connected to the bases of the seventh and eighth transistors, and the emitter Is based on the PNP type tenth transistor connected to the power supply line and the collector outputs of the first and fourth transistors. Means for extracting the output signal, an eleventh transistor having a base connected to a voltage source and an output connected to the bases of the first and fourth transistors, and a second and third transistor having a base connected to the voltage source and having an output And a variable means for varying the potential difference between the outputs of the eleventh and twelfth transistors.

Operation According to such a configuration, it is possible to realize a state in which the output currents of the eleventh and twelfth transistors do not supply the base currents of the second and third transistors. This is because the base currents of the second and third transistors are supplied from the ninth transistor even if the base currents of the second and third transistors are not supplied from the eleventh and twelfth transistors. Accordingly, the output current of the twelfth transistor connected to the bases of the second and third transistors of the eleventh and twelfth transistors can be made zero, and the first and fourth transistors of the eleventh and twelfth transistors can be made zero. The ratio of the output current to the transistor connected to the transistor becomes large, and the potential difference between the bases of the first and fourth transistors and the bases of the second and third transistors increases accordingly, and the differential amplifier The gain attenuation increases.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment> In FIG. 1 embodying the present invention, the same parts as those in the conventional example of FIG. In this embodiment, the second differential pair transistor Q4 of the NPN type is used.
And the base of the first PNP transistor Q13 is connected to the base of Q5, and the collectors of the second differential pair transistors Q4 and Q5 are connected to the emitters of NPN transistors Q14 and Q15. The collectors of the transistors Q14 and Q15 are connected to the power supply line 50, and the base is connected to the second PNP transistor Q
Connected to 16 bases. Second PNP transistor Q
The 16 emitters are connected to the power supply line 50, while the collector is connected to the emitter of the first PNP transistor Q13. The collector of the first PNP transistor Q13 is connected to the ground potential point.

According to this circuit, there is an advantage that the base current of the second differential pair transistors Q4 and Q5 can be ignored for setting the gain attenuation. That is, in FIG. 2 which shows a main part of FIG. 1 when the currents I _1a and I _1b are determined, the currents I _2a and I _2b flowing into the bases of the transistors Q14 and Q15 are determined accordingly.
It is determined, eventually resulting in the current I ₃ flowing through the collector of transistor Q16 is determined. The base currents I _2a and I _2b flowing through the transistors Q14 and Q15 and the second differential pair transistors Q4 and Q5
Base current I _2a flowing through ', I _2b' is approximately equal, the first, the base current flowing through the second differential pair of transistors Q4, Q5 for the base current of the second opposite conductivity type transistors Q13, Q16 are equal the It is supplied by the base current of one reverse conductivity type transistor Q13. When this is calculated, I _1a ′ = I _1b ′ = I _1a · (β _N +1) / β _N I ₃ ′ = I ₃ · (β _P −1) / β _{P. 2a} ′ = I _2b ′ = I ₃ ′ / 2β _P = I ₃ (β _P −1) / (2β
² _P) the base current to be supplied to the transistors Q4, Q5 _{are, I1a '/ β N = I1a} · (β N +1) / β N 2 where, beta _N is of the same conductivity type transistors beta, beta _P is reversed Β of a conduction type transistor, β _N = 120, β _P = 60, I
_{If 1a} = 100 μA, I ₃ = 50 μA, and the difference between the current to be supplied to the same conductivity type transistor Q4 and the current to be supplied from the second opposite conductivity type transistor Q13 is 100 μ × 121/12
0 ² −50 × 59/60 ² = 0.021 μA, and transistors Q12 and Q12
It is negligibly small compared to the conventional example (0.833 μA) not using 14, Q15 and Q16. Transistors Q3, Q
The same applies to the base currents of Q6 and Q5.

In this circuit, the maximum attenuation ATT is also 61.5dB,
It is larger than that of the conventional example (29.7 dB). Returning to FIG. 1, in the present embodiment, the first differential pair transistors Q3 and Q6
A similar circuit is connected to the side. Transistors Q17, Q1
8, Q19 and Q20 show that.

<Second Embodiment> Next, FIG. 3 shows a second embodiment of the present invention.
Here, the only difference from FIG. 1 is that a variable current source 15 is provided as shown, the emitters of a pair of transistors Q1 and Q2 are connected to a constant current source, and that transistors Q17 to Q20 are not present. And the others are substantially the same.

As shown, the constant current sources are transistors Q11 and Q12, resistors R1 and R2 connected between the emitters and ground, and transistor Q11.
11, a constant current source 12 for applying a constant bias to Q12, a diode D2, and a resistor R3.

<Third Embodiment> FIG. 4 shows a third embodiment.
It differs from the embodiment (FIG. 3) in that the diode D1 is connected between the emitter and the base of the second transistor Q2 with the illustrated polarity. In the circuit of FIG. 3 (second embodiment) equal the current value I ₂ of the maximum current value and the transistor Q12 of the variable current source 15, but attenuation, can be increased, but in fact there is a slight, this circuit Even if it is used, the base current flows through the second differential pair transistors Q4 and Q5 and the current may vary. Therefore, when designing, the maximum current value of the variable current source 15 is larger than the current value I of the transistor Q12. Must be greater than ₂ .

Therefore, in this embodiment a diode D1 provided, the excess current flows through the diode D1 when the current value of the variable current source 15 is larger than the current value I ₂ of the transistor Q12,
The potential difference between (a) and (b) becomes 2V _F , and the output signal is attenuated to 462dB at room temperature in theoretical value. Thus when the current value I ₂ of the variable current source 15 and the transistor Q12 become equal, (i) and (ii) the difference between the V _F,
It will occur a difference of 2V _F when the current of the variable current source 15 is larger than the current value I ₂ of the transistor Q12. V _F
(0.7 V) gain just different output signals since the difference more than 220dB is considered noise level, therefore, the circuit of this embodiment the current I _X of the variable current source of the transistor Q12 as shown in Figure 5 first when the current I ₂ value less than a second
Determines the output voltage of the transistors Q1, Q2 emitter current ratio, it current I _X of the variable current source 15 is equal to the current I ₂ of the transistor Q12, an output signal if large characteristic such that the noise level is obtained become.

<Fourth embodiment> As shown in FIG. 6, when the two channels 51 and 52 are simultaneously controlled by one control current, if there is no base current compensation circuit including the transistors Q13 to Q16, as shown in FIG. current I _X of the left and right by the constant current source 15 to the base current in one channel and current I ₂ of the transistor Q12 in the second
The characteristics change abruptly before and after becoming equal to the sum of the base current supplied to the differential pair transistors Q4 and Q5.
Channels are not practical, as they further exacerbate the problem.

However, in this embodiment, a base current compensation circuit including transistors Q13 to Q16 is provided in each of the channels 51 and 52 so that the base current can be substantially ignored.
Even when the channels are controlled simultaneously, a smooth attenuation characteristic can be obtained as shown in FIG. An advantage of controlling two channels at the same time is that variations between channels can be eliminated.

Effects of the Invention As described above, according to the present invention, it is possible to realize a state in which the output currents of the eleventh and twelfth transistors do not supply the base currents of the second and third transistors. This is because the base currents of the second and third transistors are the eleventh and twelfth.
This is because the base currents of the second and third transistors are supplied from the ninth transistor even if not supplied from the transistor side. Accordingly, the output current of the twelfth transistor connected to the bases of the second and third transistors of the eleventh and twelfth transistors can be made zero, and the first and fourth transistors of the eleventh and twelfth transistors can be made zero. The ratio of the output current to the transistor connected to the transistor becomes large, and the potential difference between the bases of the first and fourth transistors and the bases of the second and third transistors increases accordingly, and the differential amplifier This has the effect of increasing the gain attenuation.

Further, since the base current can be neglected with respect to the setting of the gain attenuation, there is an effect that the design becomes easy.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the gain control circuit of the present invention, and FIG. 2 is a circuit diagram of a main part thereof. FIG. 3 is a circuit diagram of a second embodiment of the present invention, FIG. 4 is a circuit diagram of the third embodiment, FIG. 5 is an explanatory diagram thereof, FIG. 6 is a circuit diagram of the fourth embodiment, and FIG. 7 and 8 are explanatory diagrams thereof, FIG. 9 is a circuit diagram of a conventional example, and FIG. 10 is an explanatory diagram thereof. 1 ... differential amplifier, Q1 ... first transistor, Q2 ... second transistor, Q3, Q6 ... first differential pair transistor, Q
4, Q5: second differential pair transistor, Q13: first reverse conductivity type transistor, Q14, Q15: same conductivity type transistor, Q16: second reverse conductivity type transistor.

Continuation of the front page (56) References JP-A-1-125109 (JP, A) JP-A-61-239707 (JP, A) JP-A-57-127311 (JP, A) JP-A-60-21617 (JP) JP-A-59-185413 (JP, A) JP-A-57-152709 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03G 3/10 H03F 3/45

Claims (1)

(57) [Claims] 1. An NPN type first having emitters connected in common.
A first differential pair composed of a second transistor; a second differential pair composed of NPN-type third and fourth transistors having emitters connected in common; and a collector connected to the emitters of the first and second transistors A third differential pair composed of an NPN-type fifth transistor, an NPN-type sixth transistor having collectors connected to the emitters of the third and fourth transistors, and an emitter connected to the fifth and sixth transistors, respectively. A constant current source, an input signal terminal connected to the base of each of the fifth and sixth transistors, and an NPN-type seventh transistor whose emitter is connected to the collector of the second transistor and whose collector is connected to the power supply line. An eighth transistor of an NPN type having an emitter connected to the collector of the third transistor and a collector connected to the power supply line, and a base having bases of the second and third transistors. A ninth transistor of a PNP type having a collector connected to the ground, a collector connected to the emitter of the ninth transistor, a base connected to the base of the seventh and eighth transistors, and an emitter connected to the power supply line. A PNP-type tenth transistor, means for extracting an output signal based on the collector outputs of the first and fourth transistors, and an eleventh transistor whose base is connected to a voltage source and whose output is connected to the bases of the first and fourth transistors. A transistor, a twelfth transistor having a base connected to the voltage source and an output connected to the bases of the second and third transistors, and variable means for varying a potential difference between the outputs of the eleventh and twelfth transistors. Gain control circuit.