JP2861406B2 - Manufacturing method of ceramic multilayer wiring board - Google Patents

Manufacturing method of ceramic multilayer wiring board

Info

Publication number
JP2861406B2
JP2861406B2 JP417091A JP417091A JP2861406B2 JP 2861406 B2 JP2861406 B2 JP 2861406B2 JP 417091 A JP417091 A JP 417091A JP 417091 A JP417091 A JP 417091A JP 2861406 B2 JP2861406 B2 JP 2861406B2
Authority
JP
Japan
Prior art keywords
multilayer wiring
manufacturing
ceramic multilayer
wiring board
laminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP417091A
Other languages
Japanese (ja)
Other versions
JPH04243196A (en
Inventor
良昌 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP417091A priority Critical patent/JP2861406B2/en
Publication of JPH04243196A publication Critical patent/JPH04243196A/en
Application granted granted Critical
Publication of JP2861406B2 publication Critical patent/JP2861406B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はセラミック多層配線基板
の製造方法、特にグリーンシート法により製造されるセ
ラミック多層配線基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ceramic multilayer wiring board, and more particularly to a method of manufacturing a ceramic multilayer wiring board manufactured by a green sheet method.

【0002】[0002]

【従来の技術】従来のセラミック基阪の製造方法は、特
開昭62−134997号に示されるように、アルミ
ナ、ガラス等の粉体と溶剤とをして泥紫とし、この泥漿
をスリップキャスティング法にて成膜しグリーンシート
とし、これを所定の形状に切断する。そして、パンチン
グにてグリーンシートの上下間を接続するためのスルー
ホールを形成し、このスルーホールに印刷法により導体
パターンペースト及びビアフィルペーストを埋め込み、
更に、このグリーンシートを所定数積層し、加圧・加温
して圧着した後、脱バインダー及び焼成を実施して製造
していた。
2. Description of the Related Art A conventional method of manufacturing a ceramic substrate is disclosed in Japanese Patent Application Laid-Open No. 62-134997, in which powder such as alumina or glass is mixed with a solvent to obtain mud purple, and this mud is slip-cast. A green sheet is formed by a method, and this is cut into a predetermined shape. Then, a through hole for connecting the upper and lower sides of the green sheet is formed by punching, and a conductor pattern paste and a via fill paste are embedded in the through hole by a printing method.
Further, a predetermined number of the green sheets are laminated, pressurized and heated and pressed, and then debinding and firing are performed.

【0003】[0003]

【発明が解決しようとする課題】上述した従来のセラミ
ック多層配線基仮の製造方法は、スルーホール形成・ビ
アフィル工程を行なっているため、1.スルーホール形
成もれ2.積層前に導体ベ―スト抜けによるアビオープ
ン3.導体ペーストが柱の役割をしてしまうため、ホー
ルビアが湾曲し、グリーンシート自体に圧力がかから
ず、収縮率がばらつくなどの欠点がある。
[SUMMARY OF THE INVENTION The method of manufacturing a conventional ceramic multilayer wiring base provisional described above, since the performing Suruho Le shaped formation, via fill process, 1. 1. Through-hole leakage 2. Avi open due to missing conductor base before lamination. Since the conductive paste acts as a pillar, the via holes are curved, the green sheet itself is not pressed, and the shrinkage ratio varies.

【0004】[0004]

【課題を解決するための手段】本発明は、回路バターン
が形成されたグリーンシートを複数枚積層し、これを熱
圧着して積層体を形成し、所定の前記回路パターン間に
導体ピンを挿入して導通させてなるセラミック多層配線
基坂の製造方法において、前記積層体を加熱する第1の
工程と、加熱した前記導体ピンを挿入る第2の工程と
を含んで構成されている。
Means for Solving the Problems The present invention, the green sheet circuit Bataan is formed by laminating a plurality, which was thermocompression bonding to form a laminate, between predetermined said circuit pattern
Ceramic multilayer wiring made by inserting conductive pins and conducting
The method of manufacturing a group slope is configured to include a first step of heating the laminated body, and a second step to insert the conductor pins heated pressurized.

【0005】[0005]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0006】図1は本発明は一実施例を示す断面図であ
る。
FIG. 1 is a sectional view showing an embodiment of the present invention.

【0007】図2は本実施例のグリーンシートの積層
例を示す斜視図である。図1および図2において、グリ
ーンシート1は導体配線2を施されたシートであり、こ
のグリーンシート1を複数枚積層し、熱プレス機により
熱圧着し積層体3を形成する。このとき、スル―ホール
形成工程がないためスルーホール形成もれがない。ま
た、ビアフィル工程がないためグリーンシート1自体に
かかる圧力の安定化が図れる。そして、導体ピン4を積
層体に挿入する。このとき、導体ピンは予め高温に加熱
されており、積層体も同様に加熱しているため、容易に
ピンを挿入することができる。
[0007] FIG. 2 is a perspective view showing an <br/> example of a laminated green sheet of the present embodiment. 1 and 2, a green sheet 1 is a sheet provided with a conductor wiring 2, and a plurality of the green sheets 1 are laminated and thermocompressed by a hot press machine to form a laminate 3. At this time, there is no through-hole formation step because there is no through-hole formation step. Further, since there is no via-filling step, the pressure applied to the green sheet 1 itself can be stabilized. Then, the conductor pins 4 are inserted into the laminate. At this time, since the conductor pins are heated to a high temperature in advance and the laminate is also heated in the same manner, the pins can be easily inserted.

【0008】以上の工程の後、上下にはみ出した余分な
導体ピン4を切断し、更に、この積層体3を脱バインダ
ー及び焼成を行う。
After the above steps, the excess conductor pins 4 protruding up and down are cut, and the laminate 3 is subjected to binder removal and firing.

【0009】[0009]

【発明の効果】以上説明したように本発明は、積層・熱
圧着後に導体ピンを挿入することによってスルーホール
形成・ビアフィルを行なう必要がなくなる。そのため、
スルーホールの形成もれ、ビア抜け・ビアオープン、ビ
アペーストの湾曲によりプレス圧がグリーンシートにか
からないため収縮率のばらつき等の問題点をなくする効
果がある。
As described above, according to the present invention, there is no need to form a through hole and to fill a via hole by inserting a conductor pin after lamination and thermocompression bonding. for that reason,
Since the press pressure is not applied to the green sheet due to the formation of through holes, via holes missing, via openings, and via paste curvature, there is an effect of eliminating problems such as variations in shrinkage.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】本実施例のグリーンシートの積層の例を示す斜
視図である。
FIG. 2 is a perspective view showing an example of lamination of green sheets of the present embodiment.

【符号の説明】[Explanation of symbols]

1 グリーンシート 2 導体配線 3 積層体 4 導体ピン 1 green sheet 2 conductor wiring 3 laminate 4 conductor pin

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 回路バターンが形成されたグリーンシー
トを複数枚積層し、これを熱圧着して積層体を形成し、
所定の前記回路パターン間に導体ピンを挿入して導通さ
せてなるセラミック多層配線基坂の製造方法において、
前記積層体を加熱する第1の工程と、加熱した前記導体
ピンを挿入る第2の工程とからなるセラミック多層配
線基坂の製造方法。
1. A green sheet on which a circuit pattern is formed is laminated in plural, and the green sheets are thermocompression-bonded to form a laminate .
Conductive pins are inserted between the predetermined circuit patterns to
In the method for manufacturing a ceramic multilayer wiring base slope,
The first step and the ceramic multilayer wiring base slope method for producing comprising a second step to insert the conductor pins hot pressurized heating said laminate.
JP417091A 1991-01-18 1991-01-18 Manufacturing method of ceramic multilayer wiring board Expired - Lifetime JP2861406B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP417091A JP2861406B2 (en) 1991-01-18 1991-01-18 Manufacturing method of ceramic multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP417091A JP2861406B2 (en) 1991-01-18 1991-01-18 Manufacturing method of ceramic multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH04243196A JPH04243196A (en) 1992-08-31
JP2861406B2 true JP2861406B2 (en) 1999-02-24

Family

ID=11577263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP417091A Expired - Lifetime JP2861406B2 (en) 1991-01-18 1991-01-18 Manufacturing method of ceramic multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2861406B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4850356B2 (en) * 2000-10-23 2012-01-11 イビデン株式会社 Interlayer connection structure and manufacturing method

Also Published As

Publication number Publication date
JPH04243196A (en) 1992-08-31

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A01 Written decision to grant a patent or to grant a registration (utility model)

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Effective date: 19981110