JP2859784B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate used for a liquid crystal display device and the like and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal display device, an active matrix type display device having advantages such as high contrast and unlimited number of picture elements has been used. In an active matrix substrate used in this active matrix display device, pixel electrodes arranged in a matrix on an insulating substrate are formed of thin film transistors (TFs).
Independently driven using an active element such as T).

FIG. 5 shows an example of an active matrix substrate using a TFT as an active element. In this active matrix substrate, a plurality of gate bus lines 1 and a plurality of source bus lines 2 are provided on a substrate 11. Near the intersection of each gate bus line 1 and each source bus line 2, a TFT 26 connected to both lines is provided. A picture element electrode is connected to the TFT 26, and liquid crystal is sealed between the picture element electrode and the counter electrode to form a picture element 57. The TFT 26 is controlled by a gate signal sent from the gate drive circuit 54 through the gate bus line 1. The video signal sent from the source drive circuit 52 through the source bus line 2 is T
The data is written to the picture element 57 when the FT 26 is on. The written video signal is held in the picture element 57 while the TFT 26 is off. Further, the additional capacitance wiring 8 is connected in parallel with the picture element 57.
Is formed, and the retention of the video signal is improved.

The active matrix substrate is specifically, for example, as shown in FIG. In this active matrix substrate, the TFT 26 has a semiconductor layer 30 formed on the insulating substrate 11. A gate insulating film 13 is formed on the semiconductor layer 30, and a gate electrode 3 branched from a gate bus line is formed on the gate insulating film 13. A first interlayer insulating film 14 is formed on almost the entire surface of the substrate in that state.

[0005] Contact holes 7 a and 7 b are opened through the first interlayer insulating film 14 and the gate insulating film 13. On the first layer insulating film 14, the source electrode 9 and drain electrode 10 which is branched from the source bus line is formed, a contact hole 7a, and is connected to the semiconductor layer 30 through 7b.

Further, a second interlayer insulating film 17 is formed over substantially the entire surface of the substrate, and a contact hole 7c is opened in the second interlayer insulating film 17. Contact hole 7
Metal film 25 is formed so as to fill c, and pixel electrode 4 is formed on second interlayer insulating film 17 so as to be connected to metal film 25. The formation of the metal film 25 (the hatched portion in the drawing) allows an ohmic contact to be made.

On the gate insulating film 13, an additional capacitance electrode 6 branched from the additional capacitance wiring 8 is provided in parallel with the gate bus line 1 to form an additional capacitance.

In this active matrix substrate,
The TFT 26 has an LDD (Lightly Doped Drain) structure. In this structure, the semiconductor layer 30 made of polycrystalline silicon has five regions, and the channel portion 12 and the high-concentration impurity regions serving as a source region and a drain region.
24, a medium-concentration impurity region 23 having a lower impurity concentration than the high-concentration impurity region is formed with a width of 1.5 to 2 μm. The resistance in the medium-concentration impurity region 23 is higher than that in the high-concentration impurity region 24, and the generation of off-current of the TFT can be reduced. Further, since the area of the TFT can be reduced as compared with the TFT having the dual gate structure, the aperture ratio of the liquid crystal display device can be increased. Therefore,
The liquid crystal display device can be reduced in size and definition.

[0009]

However, in the above-described active matrix substrate, when used in a liquid crystal display device, the characteristics of the channel portion 22 of the semiconductor layer 30 change due to light irradiation, and the off-current of the TFT is reduced. And the display contrast of the liquid crystal display device may be reduced. In order to prevent light irradiation, a light-shielding film may be formed on the opposite substrate of this substrate, but in this case, the aperture ratio of the liquid crystal display device may be reduced.

An object of the present invention is to solve the above problems, and an object of the present invention is to provide an active matrix substrate which can prevent an increase in the off-state current of a TFT and can realize a liquid crystal display device having a large aperture ratio. is there.

[0011]

In the active matrix substrate of the present invention, picture element electrodes are formed in a matrix on the substrate, and a plurality of scanning wirings and a plurality of signal wirings pass through the periphery of the picture element electrodes. And an active matrix substrate in which a thin film transistor for driving a pixel electrode is formed in the vicinity of the intersection of the two wirings, wherein the thin film transistor comprises a semiconductor layer having a channel portion, and an insulating layer covering the thin film transistor A first metal film is formed at least at a position corresponding to the channel portion, and a second metal film connecting between the picture element electrode and a drain region of the thin film transistor is formed through the insulating layer. The first metal film is provided with a voltage applying means.
Provided , thereby achieving the above objectives. The semiconductor layer of the thin film transistor may be an outermost layer.
High-concentration regions where the regions become the source and drain regions, respectively.
A pure region, the inside of which is a medium concentration impurity region,
Even if the central part has five regions that are channel portions
Good.

[0012]

[0013]

[0014]

In the present invention, since the metal film is formed on the thin film transistor so as to cover at least the channel portion, the channel portion can be shielded from light without being irradiated with light. Therefore, an increase in off-state current of the TFT during light irradiation can be prevented . Et al is, in the case of using the substrate in a liquid crystal display device, the portion where the metal film is formed, it is not necessary to form a light shielding film on the counter substrate of the substrate is eliminated, the aperture ratio of the liquid crystal display device Can be bigger. In the present invention, a metal film is formed on the thin film transistor so as to cover at least the channel portion, and the metal film is provided with voltage applying means. That is, when a voltage is applied to this metal film, the metal film acts as a sub-gate of the TFT.
The off-state current of the TFT can be reduced, and the on-state current can be increased.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing an active matrix substrate according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA 'of FIG. In this active matrix substrate, a gate bus line 1 and a source bus line 2 are vertically and horizontally formed on an insulating substrate 11,
The picture element electrode 4 is formed in a region surrounded by both lines. Further, a TFT is connected to drive the picture element electrode 4.

In this active matrix substrate,
The TFT has an LDD structure as in FIG. 5 and has a semiconductor layer 30 formed on the insulating substrate 11. A gate insulating film 13 is formed on almost the entire surface of the substrate so as to cover the semiconductor layer 30, and a gate electrode 3 branched from the gate bus line 1 is formed on the gate insulating film 13. A first interlayer insulating film 14 is formed on substantially the entire surface of the substrate in that state.

Contact holes 7a and 7b are opened through first interlayer insulating film 14 and gate insulating film 13. On the first layer insulating film 14, the source electrode 9 and drain electrode 10 which is branched from the source bus line 2 is formed, contact holes 7a, 7b
Through the semiconductor layer 30.

On the first interlayer insulating film 14, a second interlayer insulating film 17 is further formed, and a contact hole 7c is opened in the second interlayer insulating film 17. A metal film 25 (shaded portion in the figure) is formed so as to fill contact hole 7c, and a metal film is formed on second interlayer insulating film 17 as well.
15 (shaded portions in the figure) are formed. Further, the pixel electrode 4 is formed so as to be connected to the metal film 25. Metal film
As shown in FIG. 2, reference numeral 15 covers the channel portion 12 and the medium-concentration impurity region of the semiconductor layer 30, so that an independent voltage can be applied.

On the gate insulating film 13, an additional capacitance electrode 6 branched from the additional capacitance wiring 8 is provided in parallel with the gate bus line 1 to form an additional capacitance.

This active matrix substrate is manufactured as follows.

First, on the insulating substrate 11, a thickness of 40 to 80
A semiconductor layer 30 made of a polycrystalline silicon film of nm is formed by a CVD method. Next, an insulating film made of SiO ₂ or SiN _X and having a thickness of about 100 nm is laminated by a CVD method or sputtering, and is patterned to form a gate insulating film 13. The gate insulating film 13 may be formed by oxidizing the polycrystalline silicon film by heat.

On top of this, a layer made of polycrystalline silicon doped with phosphorus is deposited to a thickness of 450 nm by CVD or sputtering, and is patterned to form a gate bus line 1, a gate electrode 3, and a wiring 6 for additional capacitance. I do. Next, the semiconductor layer is formed by photolithography.
A resist pattern is formed in a region other than 30 and the semiconductor layer 30 is formed using the resist pattern and the gate electrode 3 as a mask.
Was implanted under the conditions of 80 keV and 1 × 10 ¹³ cm ⁻² . Further, in the semiconductor layer 30, a resist removal pattern is formed in a region 1.5 to 2.0 μm away from the gate electrode 3, and phosphorus is applied at 30 keV and 1.0 × 10 ¹⁵ cm ⁻²
Was injected under the following conditions. As a result, a channel portion 12, a medium-concentration impurity region 23 having a width of 1.5 to 2 μm, and a high-concentration impurity region 24 serving as a source region and a drain region are formed in the semiconductor layer 30.

Next, S is deposited on the entire surface of the substrate by CVD.
The first interlayer insulating film 14 of iO _{2 is} formed to a thickness of about 300 nm.
And contact holes 7a, 7b by wet etching or dry etching.
Is provided. Then, using a low-resistance metal such as Al,
A source bus line 2, a source electrode 9, and a drain electrode 10 having a thickness of about 600 nm are formed by VD. Source electrode 9 and drain electrode 10 are formed to fill contact holes 7a and 7b, respectively.

Further, the entire surface of the substrate is formed by a CVD method.
A _second layer made of SiO ₂ or SiN _X and having a thickness of about 600 nm;
Is formed, and a contact hole 7c is provided by wet etching or dry etching.
Then, metal films 25 and 15 made of TiW, WSi, etc.
Was deposited to a thickness of about 120 to 150 nm by sputtering, and then a pattern was formed by dry etching. As a result, the metal film filled in the contact hole
25 and a metal film 15 which covers the channel portion 12 of the semiconductor layer 30 and overlaps the medium-concentration impurity region by 1 μm in the width direction are simultaneously formed. The metal films 25 and 15 are made of Al alloy, W, M
It may be made of o or Ti, or may be a silicide of Mo or Ti. The thickness of the metal film 15 varies depending on the material, but is set to a thickness that can prevent light transmission. In the case of TiW, if the thickness is 150 nm, almost light can be shielded. Preferably, the thickness is from 100 angstroms to several thousand angstroms.

Next, a picture element electrode 4 made of ITO and having a thickness of 100 nm to 200 nm is formed by sputtering to form an active matrix substrate. When the metal film 25 is damaged during the etching of ITO,
The ITO pattern may be formed so as to overlap the metal film 25.

Embodiment 2 FIG. 3 is a plan view showing an active matrix substrate according to another embodiment of the present invention.
FIG. 4 is a sectional view taken along line AA ′ of FIG. In this active matrix substrate, a metal film 16 (hatched portion in the figure) is formed instead of the metal films 25 and 15 of the first embodiment, and as shown in FIG.
12, the medium concentration impurity region 23 and the high concentration impurity region 24 are completely covered. The metal film 16 is in contact with the edge of the picture element electrode 4 as shown in FIG. As a manufacturing method, it can be performed in the same manner as in Example 1.

The results of a TFT characteristic test performed on the active matrix substrates of Examples 1 and 2 manufactured as described above are shown below. FIG. 7 is a diagram illustrating current-voltage characteristics of the active matrix substrates of the first and second embodiments. Here, the horizontal axis is the gate voltage, the vertical axis is the drain current, and the voltage between the source and the drain is 10V. Table 1 shows the ON current I _on and off current I _off of the TFT with respect to the voltage V _b being subjected to the metal film. Here, the off current is a current value at a gate voltage = −10 V, and the on current is a current value at a gate voltage of 15 V.
Table 1 also shows, as a comparative example, a conventional active matrix substrate in which a metal film is not provided in a TFT portion as shown in FIG.

[0029]

[Table 1]

As can be understood from FIG. 7 and Table 1, in the active matrix substrates of Examples 1 and 2, the off-state current of the TFT at the time of light irradiation could be reduced. Further, by applying a voltage to the metal film 15, the on-current of the TFT can be increased and the off-current can be reduced.

In the second embodiment, the metal film 16 is formed in contact with the edge portion of the picture element electrode 4 and has the same potential as the picture element electrode 4. Therefore, when used in a liquid crystal display device, it is also possible to suppress the alignment disorder of the liquid crystal molecules at the edge.

[0032]

As described above, according to the present invention, the TFT
Since the channel portion is sufficiently shielded from light, the characteristics of the channel portion do not change when light is irradiated, and the off current does not increase. Also, when used in a liquid crystal display device, it is not necessary to form another light-shielding film on the counter substrate of this substrate in the portion where the metal film is formed, so that the aperture ratio of the liquid crystal display device is reduced. Can be bigger. Therefore,
A liquid crystal display device having excellent display characteristics can be obtained.
Further, by applying a voltage to the metal film, the ON current of the TFT can be increased and the OFF current can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of an active matrix substrate according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line A-A 'of FIG.

FIG. 3 is a plan view of an active matrix substrate according to a second embodiment of the present invention.

FIG. 4 is a sectional view taken along line A-A 'of FIG.

FIG. 5 is a schematic view of a general active matrix substrate.

FIG. 6 is a cross-sectional view of a conventional active matrix substrate.

FIG. 7 is a diagram showing the result of conducting a characteristic test of a TFT.

[Explanation of symbols]

 Reference Signs List 3 gate electrode 4 picture element electrode 6 additional capacitance electrode 7a, 7b, 7c contact hole 9 source electrode 10 drain electrode 12 channel section 13 gate insulating film 14 first interlayer insulating film 15, 16, 25 metal film 17 second Interlayer insulating film 23 Medium concentration impurity region 24 High concentration impurity region 30 Semiconductor layer

Continuation of the front page (56) References JP-A-63-292115 (JP, A) JP-A-3-163529 (JP, A) JP-A-3-163530 (JP, A) JP-A-3-288824 (JP) JP-A-4-283729 (JP, A) JP-A-4-291240 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/136 500

Claims (2)

(57) [Claims] 1. A pixel electrode is formed in a matrix on a substrate, and a plurality of scanning lines and a plurality of signal lines are formed through a peripheral portion of the pixel electrode. In an active matrix substrate on which a thin film transistor for driving a pixel electrode is formed, the thin film transistor includes a semiconductor layer having a channel portion. together with first metal film is formed, the result second metal film for connecting the pixel electrode and the TFT drain region is formed through on the insulating layer, the first metal film
Is an active matrix substrate provided with voltage applying means . 2. The semiconductor layer of the thin film transistor according to claim 1 ,
The outer region becomes the source region and the drain region, respectively.
Impurity region, and the inside is a medium concentration impurity region.
And the central part has five regions which are channel portions.
The active matrix substrate according to claim 1, characterized in that that.