JP2843006B2 - エミュレーション手段を有するプログラマブル集積回路メモリ - Google Patents

エミュレーション手段を有するプログラマブル集積回路メモリ

Info

Publication number
JP2843006B2
JP2843006B2 JP20651695A JP20651695A JP2843006B2 JP 2843006 B2 JP2843006 B2 JP 2843006B2 JP 20651695 A JP20651695 A JP 20651695A JP 20651695 A JP20651695 A JP 20651695A JP 2843006 B2 JP2843006 B2 JP 2843006B2
Authority
JP
Japan
Prior art keywords
memory
bus
signal
internal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP20651695A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0864000A (ja
Inventor
ゴルティエ ジャン−マリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ESU TEE MIKUROEREKUTORONIKUSU SA
Original Assignee
ESU TEE MIKUROEREKUTORONIKUSU SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ESU TEE MIKUROEREKUTORONIKUSU SA filed Critical ESU TEE MIKUROEREKUTORONIKUSU SA
Publication of JPH0864000A publication Critical patent/JPH0864000A/ja
Application granted granted Critical
Publication of JP2843006B2 publication Critical patent/JP2843006B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14Implementation of control logic, e.g. test mode decoders
    • G11C29/16Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines

Landscapes

  • Read Only Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Storage Device Security (AREA)
JP20651695A 1994-07-20 1995-07-20 エミュレーション手段を有するプログラマブル集積回路メモリ Expired - Fee Related JP2843006B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9409202A FR2722907B1 (fr) 1994-07-20 1994-07-20 Memoire integree programmable comportant des moyens d'emulation
FR9409202 1994-07-20

Publications (2)

Publication Number Publication Date
JPH0864000A JPH0864000A (ja) 1996-03-08
JP2843006B2 true JP2843006B2 (ja) 1999-01-06

Family

ID=9465729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20651695A Expired - Fee Related JP2843006B2 (ja) 1994-07-20 1995-07-20 エミュレーション手段を有するプログラマブル集積回路メモリ

Country Status (5)

Country Link
US (1) US5651128A (fr)
EP (1) EP0696031B1 (fr)
JP (1) JP2843006B2 (fr)
DE (1) DE69500112T2 (fr)
FR (1) FR2722907B1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9417297D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Method and apparatus for testing an integrated circuit device
US5893135A (en) * 1995-12-27 1999-04-06 Intel Corporation Flash memory array with two interfaces for responding to RAS and CAS signals
US5787484A (en) * 1996-08-08 1998-07-28 Micron Technology, Inc. System and method which compares data preread from memory cells to data to be written to the cells
US5754567A (en) 1996-10-15 1998-05-19 Micron Quantum Devices, Inc. Write reduction in flash memory systems through ECC usage
EP0935195A2 (fr) 1998-02-06 1999-08-11 Analog Devices, Inc. Circuit intégré avec convertisseur analogique-numérique à haute résolution, un microcontrolleur et une mémoire à haute densité et émulateur correspondant
US6289300B1 (en) 1998-02-06 2001-09-11 Analog Devices, Inc. Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit
US6701395B1 (en) 1998-02-06 2004-03-02 Analog Devices, Inc. Analog-to-digital converter that preseeds memory with channel identifier data and makes conversions at fixed rate with direct memory access
US6385689B1 (en) * 1998-02-06 2002-05-07 Analog Devices, Inc. Memory and a data processor including a memory
JP3472123B2 (ja) * 1998-02-24 2003-12-02 沖電気工業株式会社 シーケンスコントローラ
DE69832609D1 (de) 1998-09-30 2006-01-05 St Microelectronics Srl Emulierte EEPROM Speicheranordnung und entsprechendes Verfahren
JP4124692B2 (ja) 2003-04-25 2008-07-23 シャープ株式会社 不揮発性半導体記憶装置
EP1473739A1 (fr) 2003-04-29 2004-11-03 Dialog Semiconductor GmbH Mémoire flash avec pré-détection de la perte de données
PL363945A1 (en) 2003-12-08 2005-06-13 Advanced Digital Broadcast Polska Spółka z o.o. Software method for eeprom memory emulation
CN102750980B (zh) * 2012-07-20 2015-02-11 中国科学院上海微系统与信息技术研究所 一种具有配置电路的相变存储器芯片

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2684365B2 (ja) * 1987-04-24 1997-12-03 株式会社日立製作所 半導体記憶装置
US5222046A (en) * 1988-02-17 1993-06-22 Intel Corporation Processor controlled command port architecture for flash memory
CA1286803C (fr) * 1989-02-28 1991-07-23 Benoit Nadeau-Dostie Methode de verification serie pour memoires intercalaires
US5224070A (en) * 1991-12-11 1993-06-29 Intel Corporation Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory
JPH05290185A (ja) * 1992-04-13 1993-11-05 Yokogawa Electric Corp 特定用途向け集積回路
JPH0612900A (ja) * 1992-06-29 1994-01-21 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US5410544A (en) * 1993-06-30 1995-04-25 Intel Corporation External tester control for flash memory
US5509134A (en) * 1993-06-30 1996-04-16 Intel Corporation Method and apparatus for execution of operations in a flash memory array
JPH0778499A (ja) * 1993-09-10 1995-03-20 Advantest Corp フラッシュメモリ試験装置

Also Published As

Publication number Publication date
JPH0864000A (ja) 1996-03-08
FR2722907A1 (fr) 1996-01-26
US5651128A (en) 1997-07-22
DE69500112D1 (de) 1997-01-30
DE69500112T2 (de) 1997-04-17
EP0696031B1 (fr) 1996-12-18
EP0696031A1 (fr) 1996-02-07
FR2722907B1 (fr) 1996-09-06

Similar Documents

Publication Publication Date Title
US5790459A (en) Memory circuit for performing threshold voltage tests on cells of a memory array
US5675540A (en) Non-volatile memory system having internal data verification test mode
JP2843006B2 (ja) エミュレーション手段を有するプログラマブル集積回路メモリ
US6999353B2 (en) Semiconductor memory device including page latch circuit
US5825782A (en) Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns
US5825783A (en) Semiconductor integrated circuit device with large-scale memory and controller embedded on one semiconductor chip and method of testing the device
US6052321A (en) Circuit and method for performing test on memory array cells using external sense amplifier reference current
KR950006865A (ko) 반도체 불휘발성 메모리장치
KR100273179B1 (ko) 비휘발성 메모리 회로의 메모리 셀 검증 수행 방법 및 장치
EP0811989B1 (fr) Procédé et dispositif pour tester un circuit intégré de mémoire
US20030128590A1 (en) Non-volatile memory having a control mini-array
US5459733A (en) Input/output checker for a memory array
US6019501A (en) Address generating device for memory tester
JP2748335B2 (ja) テスト機能を内蔵する電気的に変更可能な不揮発性メモリ
JP2002203398A (ja) 不良な列にあるアドレスでプログラミングするのに時間を消費することを回避する方法
US5748939A (en) Memory device with a central control bus and a control access register for translating an access request into an access cycle on the central control bus
US20020174394A1 (en) External control of algorithm execution in a built-in self-test circuit and method therefor
US7573765B2 (en) Semiconductor memory device
EP0632464B1 (fr) Méthode de lecture, en cours de cellule mémoire d'un microcontrÔleur
US20020093862A1 (en) Semiconductor memory device for reducing number of input cycles for inputting test pattern
US5771191A (en) Method and system for inspecting semiconductor memory device
JP6255282B2 (ja) 半導体装置
JPH0210598A (ja) 記憶装置
JP3039400B2 (ja) 不揮発性半導体記憶装置及び不揮発性半導体記憶装置におけるブロック消去のテスト方法
EP0393626B1 (fr) Microcalculateur à prom incorporé

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19981006

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees