JP2822675B2 - LSI chip design system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI chip design system, and more particularly to an LSI chip design system capable of simultaneously verifying assembly conditions between one chip and a plurality of existing LSI packages.

[0002]

2. Description of the Related Art Conventionally, a chip design is first performed by an LSI chip layout CA as a system for designing the inside of the chip.
D, and it is possible to design a chip that matches the various conditions such as the chip manufacturing process, such as the arrangement of the transistors and chip pads in the chip and the circuit wiring.

Next, after the layout design of the chip is completed, assembly verification as to whether the chip and an existing LSI package can be assembled has been performed using a dedicated CAD for designing the package. In addition, conventional LSI package design CA
In D, assembly verification of one chip and multiple types of LSI packages cannot be performed at the same time.
The assembly verification is performed for the number of types of the I package, and the defective point is repeatedly changed in the LSI chip layout CAD several times to design the LSI chip.

When it is desired to satisfy the assembling conditions with an existing LSI package, an LSI is newly added to the chip.
Design the package.

[0005]

In a conventional LSI chip design system, when designing a chip, the layout of pads, which is particularly important for satisfying the LSI package assembly conditions, does not take into account the assembly conditions with the LSI package. ,
Since the layout is determined only by the layout conditions such as the wiring in the chip, when the existing LSI package is next used, in most cases, the layout of the pads must be changed to satisfy the assembly conditions. ,
Since the layout of the pads is almost determined, it is difficult to re-layout because it is necessary to correct the wiring inside the chip, the arrangement of transistors, etc., which are integrated at high density. It is difficult to determine the layout of the pads suitable for the LSI package to be mounted before mounting, because the conditions of the wiring in the chip and the arrangement of the transistors cannot be considered, so the layout of the pads is changed later, and the assembly conditions are checked again. In order to mount one chip on a plurality of types of LSI packages, the conventional LSI
In the case of I-package design CAD, it is not possible to verify the assembly conditions with multiple LSI packages at the same time.
There is a drawback that it is difficult to calculate conditions that can be assembled simultaneously with the I package, and that there are many cases where an existing LSI package cannot be used and a new LSI package must be designed.

[0006]

An LSI package design system according to the present invention comprises: (A) an LSI package database in which a plurality of data on the shape , material, and characteristics of an already designed LSI package are stored; ) An LSI package search unit for searching for an LSI package that meets the conditions from the LSI package database based on the data of the chip being designed on CAD, the outer shape of the LSI package, and the number of external pins of the LSI package; work to assemble the LSI package (power
(D) an assembly check unit for simultaneously performing an assembly check with a plurality of LSI packages to verify whether or not assembly conditions are satisfied in an air connection operation ;
-Pin section that specifies the internal leads are connected to an external pin of the I package, (E) chip pads and the wiring in the chip, the chip layout section that performs chip layout of the transistor arrangement, the circuit in accordance with an instruction from the (F) User Layout part and
A user instructing each part of the pin connector to perform processing.
A user interface unit; and
Chip by the chip layout section through the base section
The layout is implemented, and the LSI
When the connection of the internal lead to the package is changed,
The chip and LSI package set in the chip layout section
The assembly check section verifies the assembly conditions between the cage and the cage.
It is characterized by that .

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. 1 is a processing device having a central processing unit (CPU) and a main storage device, 2 is a mouse, 3 is a keyboard, 4 is a display, and 5 is a magnetic recording device, which inputs and outputs data and work instructions with the processing device. . The user interface unit 10 receives input of work instructions and data from the mouse 2 and the keyboard 3 and gives work instructions and data to each unit,
A chip to be designed, an LSI package on which the chip is to be mounted, and various error indications are displayed on a display. The LSI package database 11 uses the existing LS
A plurality of data such as shape data of the I package are registered.

The LSI package selection unit 12 determines the L of 11 based on data such as the external condition of the LSI package specified by the user interface unit 10, the number of external pins, and the external shape of the LSI chip laid out at 13.
From the SI package database, package data matching the conditions is selected, and the selected data is stored in the main storage device of the processing device 1. The chip layout unit 13 interactively lays out the design of the LSI chip to be designed, and arranges the layout of the transistors, the arrangement of the chip pads, the internal wiring, etc. through the user interface unit 10 and sequentially stores the data in the main storage device. It has the function of a general LSI layout CAD.

The pin connector section 14 sets the connection between the internal leads of the LSI package stored in the main memory by the LSI package selecting section 12 and the chip pads being laid out by the chip layout section 13 through an instruction through the user interface section 10. Or change it. The assembling check unit 15 determines whether the chip layout unit 13 or the pin connection processing unit 14 changes the chip recorded in the chip layout unit 13 when the assembling conditions change (for example, when a pad is moved or a pin connection is performed). Is checked for assembly conditions with the LSI package, and the result is displayed on the display 4.

FIG. 2 shows a chip or LSI which is the object of the present invention.
It is a top view which shows a package, 20 is the LSI chip which is designing, 21 is the internal lead of the lead frame which is one kind of LSI package, 22 is the internal object which is the internal layout object of the internal lead 21 chip. Circuit, 23 is an island for mounting a chip in a lead frame, which is one type of LSI package, 24 is a chip pad of a chip for designing the LSI chip 20, 25
Is a bonding wire for electrically connecting the chip pad and the internal lead.

FIG. 2 is a view for explaining an example of a display screen of an embodiment of the present invention. A chip 20 to be designed, an internal circuit 22, and a chip pad 24 are displayed on the display. A bonding wire 25 indicating an electrical connection between the internal lead 21 of one of the plurality of LSI packages on which the LSI 20 is to be mounted, the island 23, and the LSI package indicated as the chip pad is displayed. The LSI package to be displayed and the bonding wire can be switched to an arbitrary LSI package.

FIG. 3 is a top view for explaining an example of assembly conditions related to the present invention.
The main assembly conditions with the lead frame are described, 31 is an LSI chip, 32 is an island of the lead frame, 33 is a bonding wire (hereinafter referred to as a wire) for electrically connecting the internal lead of the lead frame and the chip pad. ), 34 is a chip pad, and 35 is an internal lead of the lead frame.

The following 41 to 46 are assembling conditions for each wire, 41 is the condition of the length of the wire, 42 is the condition of the length of the wire on the internal lead, 43
Is the condition of the length of the wire on the chip, 44 is the condition of the angle between the wire and the outer side of the pellet where the wire intersects, 45 is the condition of the distance between the wire and the adjacent internal lead, 46 is the condition of the wire The conditions for the distance between adjacent chip pads are shown below.

Reference numerals 50 and 51 denote conditions for assembling each pad, 50 denotes a condition of a space between a chip pad and an adjacent chip pad, and 51 denotes a condition of a dimension of a chip pad. Numeral 60 denotes a condition relating to the distance between the outer shape of the chip and the island 32 of the lead frame.

Next, the operation will be described. Through the user interface 10, data such as the external shape of the chip 20 is input using the chip layout unit 13, and the layout of the internal circuit 22 including the arrangement of the chip pads 24 is interactively performed.
Also, at the initial stage of the chip layout, or when it is desired to change the LSI package to be mounted in the course of design, the LSI package on which the chip to be designed
An LSI package is selected from the SI package database 11 using an LSI package selection unit 12. A plurality of types of LSI packages to be mounted can be selected.

Further, the electrical connection between the chip pad of the chip under design and the internal lead of the selected LSI package is set by using the pin connector 14. Thereafter, assembling conditions of the chip and the LSI package are changed during the layout of the chip in the chip layout unit 13 and when the electrical connection between the chip pad in the pin connector unit 14 and the internal lead of the selected LSI package is changed. Immediately when the operation is performed, the assembly checking unit 15 operates, and an error is displayed on the display 4 through the user interface unit 10 with respect to a defect in assembly.

Thus, the layout inside the chip can be performed while satisfying the assembling conditions with a plurality of LSI packages on which the chip is to be mounted when designing the chip layout. Finally, the processing device 1 outputs the designed chip, the LSI package in consideration of the assembly conditions, and data on the electrical connection with the LSI package to the magnetic tape using the magnetic recording device 5.

[0019]

As described above, according to the present invention, when designing a chip, the layout of the internal circuit of the chip and the layout of the chip pads are simultaneously performed while verifying the assembly between a plurality of existing LSI packages on which the chip is to be mounted. This is a CAD system that can be implemented. By simultaneously verifying the circuit layout inside the chip and the multiple LSI packages to be mounted, the chip that can be mounted on the existing LSI package in a short time without re-layout Since the chip is designed while considering it so that it can be designed and mounted on an existing LSI package, a new design LSI
The effect of reducing the number of packages is to reduce the design, manufacturing time, and cost of the LSI product.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a top view showing the LSI package shown in FIG.

FIG. 3 is a top view for explaining an example of assembly conditions.

[Description of Signs] 11 LSI package database 12 LSI package selection unit 13 Chip layout unit 14 Pin connector unit

Claims (1)

(57) [Claims] 1. A design is performed on a CAD based on (A) an LSI package database in which a plurality of data of the shape , material, and characteristics of an already designed LSI package are stored, and (B) an LSI package database. chip data and which are, LSI package search unit for searching the LSI package that matches the LSI package outline, condition than the condition of the number of LSI package external pins, the work of assembling the (C) chips and LSI packages (electrostatic
(D) an assembly check unit for simultaneously performing an assembly check with a plurality of LSI packages to verify whether or not assembly conditions are satisfied in an air connection operation ;
-Pin section that specifies the internal leads are connected to an external pin of the I package, (E) chip pads and the wiring in the chip, the chip layout section that performs chip layout of the transistor arrangement, the circuit in accordance with an instruction from the (F) User Layout part and
A user instructing each part of the pin connector to perform processing.
A user interface unit, and the user interface unit.
The chip layout is implemented by the top layout section,
Internal lead to LSI package by the pin connector
When the connection change of
Assembling conditions between set chip and LSI package
Characterized in that the assembly check unit verifies
I-chip design system.