JP4256712B2 - Terminal arrangement apparatus and terminal arrangement method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a terminal arrangement apparatus and a terminal arrangement method for associating external connection pins of a logic circuit with terminals on a semiconductor package.
[0002]
[Prior art]
A semiconductor integrated circuit device includes a semiconductor chip called a die on which a logic circuit is mounted, and a semiconductor package covered with the semiconductor chip. As a semiconductor package, a BGA (Ball Grid Array) package or a PGA (Pin Grid Array) package that can be easily mounted on a circuit board incorporated in an electronic device is widely used. Such a semiconductor package includes a terminal (referred to as an external terminal) for connection to a circuit board of an electronic device, an internal terminal wire-bonded to a pad that is an external connection pin of a logic circuit mounted on a semiconductor chip. In addition, a wiring pattern in which these external terminals and internal terminals are connected is provided. On the other hand, the semiconductor chip is provided with a plurality of output buffer cells, and the plurality of output buffer cells are connected to the plurality of external terminals provided in the semiconductor package via the pads, bonding wires, and internal terminals. Has been.
[0003]
Here, when the plurality of output buffer cells simultaneously change from the OFF state to the ON state, the signals of the plurality of external terminals provided corresponding to the plurality of output buffer cells also simultaneously change from the “H” level to the “L” level. Change. Similarly, when the plurality of output buffer cells simultaneously change from the on state to the off state, the signals of the plurality of external terminals also change from the “L” level to the “H” level at the same time. Along with this, charging / discharging currents corresponding to the load capacities of the plurality of external terminal sides instantaneously simultaneously flow through the power supply line and the ground line. Then, noise is generated in the power supply line and the ground line.
[0004]
Therefore, in designing a semiconductor package, there has been proposed a terminal arrangement device that places a limit on the number of output buffer cells that can be operated simultaneously, and that arranges external terminals including a power supply terminal and a ground terminal in consideration of this restriction. For example, a first terminal information editing unit that displays a pad number of a semiconductor chip and performs an editing operation and a second terminal information editing unit that displays an external terminal number of a semiconductor package and performs an editing operation are provided. There has been proposed a terminal arrangement device that visually arranges external terminals by linking a terminal information editing unit and a second terminal information editing unit (see Patent Document 1).
[Patent Document 1]
JP 11-328240 A
[0005]
[Problems to be solved by the invention]
In designing a semiconductor integrated circuit device, the number of necessary power supply terminals and ground terminals is checked, and depending on the result, the size of the semiconductor package or semiconductor chip may change. For this reason, it is preferable to arrange the external terminals in the initial stage of designing the logic circuit mounted on the semiconductor chip.
[0006]
However, the terminal arrangement device proposed in Patent Document 1 is configured so that the correspondence between the external terminal number of the semiconductor package and the pad number of the semiconductor chip has already been assigned, and the design of the logic circuit is almost completed. Since the layout is performed, it is difficult to input the layout information of the external terminals at the initial design stage of the logic circuit. Accordingly, there is a lack of external terminal arrangement in consideration of noise generated due to charge / discharge currents according to load capacitances on the plurality of external terminal sides accompanying simultaneous operation of the plurality of output buffer cells.
[0007]
Further, the terminal arrangement device proposed in Patent Document 1 extracts a plurality of pieces of external terminal information corresponding to a plurality of output buffer cells operating simultaneously from the result of a simulation by applying a test pattern, and is therefore accurate. A considerable number of test patterns are required to obtain such information. However, in recent large-scale integrated circuits, such a simulation itself is difficult, and therefore there is a problem that it is not realistic.
[0008]
Furthermore, since the design of the logic circuit is almost completed, control for assigning a plurality of external terminals corresponding to a plurality of output buffer cells operating simultaneously to the same group (simultaneous operation group) is performed only from the result of the simulation. It is difficult to make an attempt to allocate an external terminal corresponding to an output buffer cell of a certain simultaneous operation group to another simultaneous operation group for simultaneous operation. Therefore, when associating the external connection pins of the logic circuit, which is the pad of the semiconductor chip, with the terminals on the semiconductor package, there is a problem that the terminal arrangement in consideration of the noise generated due to the simultaneous operation of a plurality of output buffer cells is lacking. There is.
[0009]
In view of the above circumstances, an object of the present invention is to provide a terminal arrangement device and a terminal arrangement method that can perform terminal arrangement in consideration of noise generated due to simultaneous operation of a plurality of output buffer cells.
[0010]
[Means for Solving the Problems]
The terminal arrangement device of the present invention that achieves the above object is a terminal arrangement device that associates external connection pins of a logic circuit with terminals on a semiconductor package.
An association function for associating a power supply pin, a ground pin, and an external connection pin of a circuit specification with a terminal on a semiconductor package;
A check function for checking whether or not the correspondence between the terminal on the semiconductor package and the external output pin is a correspondence that matches a predetermined output terminal simultaneous operation constraint;
A grouping function that divides the external output pins of the external connection pins of the logic circuit associated with the terminals on the semiconductor package into groups of external output pins that operate simultaneously according to the operation;
A group designating function for designating one or more groups out of the groups divided by the grouping function according to an operation;
The check function is characterized in that the check is performed on the assumption that external output pins belonging to any one or more groups designated by the group designation function operate simultaneously. The external output pins referred to here include external input / output pins having a bidirectional function.
[0011]
The terminal arrangement apparatus according to the present invention associates terminals on a semiconductor package with external connection pins of a logic circuit specification, and checks whether or not the correspondence matches a predetermined output terminal simultaneous operation constraint. Therefore, it is possible to associate the external connection pins of the logic circuit with the terminals on the semiconductor package while checking the consistency with the circuit information from the initial stage of the circuit design. Accordingly, it is possible to perform an appropriate terminal arrangement in consideration of noise generated due to the arrangement of the power supply terminal and the ground terminal and the simultaneous operation of a plurality of output buffer cells.
[0012]
In this way, the combination of groups of external output pins operating simultaneously can be checked.
[0013]
The association function associates the terminal with a power supply pin, a ground pin, and the external connection pin, and further associates the terminal with the external output pin, and further has an output buffer having driving capability information. To associate cells,
The check function is based on the output buffer cell drive capability information further associated with the association between the terminal and the external output pin, and the association between the terminal, the power supply pin, and the ground pin. It is also a preferable aspect that the above check is performed.
[0014]
In this way, the external connection pins of the logic circuit can be associated with the terminals on the semiconductor package in accordance with the drive capability of the output buffer cell.
[0015]
Further, whether or not the name and the input / output attribute match between the external connection pin associated with the terminal by the association function and the external connection pin on the logic circuit designed based on the circuit specification. It may have a confirmation function for checking.
[0016]
With such a confirmation function, the external connection pins of the logic circuit can be reliably associated with the terminals on the semiconductor package.
[0017]
Further, the terminal arrangement method of the present invention that achieves the above object is a terminal arrangement method in which external connection pins of a logic circuit are associated with terminals on a semiconductor package.
An association step of associating a power supply pin, a ground pin, and an external connection pin of a circuit specification with a terminal on a semiconductor package;
A check step for checking whether the correspondence between the terminal on the semiconductor package and the external output pin is a correspondence that matches a predetermined output terminal simultaneous operation constraint;
A grouping step that divides the external output pins of the external connection pins of the logic circuit associated with the terminals on the semiconductor package into groups of external output pins that operate simultaneously according to the operation;
A group designation step for designating one or more groups among the groups divided by the grouping step according to an operation;
In the check step, the check is performed on the assumption that external output pins belonging to any one or more groups specified in the group specifying step operate simultaneously.
[0018]
According to the terminal arrangement method of the present invention, external connection pins of a logic circuit can be associated with terminals on a semiconductor package while checking consistency with circuit information from the initial stage of circuit design. Accordingly, it is possible to perform an appropriate terminal arrangement in consideration of noise generated due to the arrangement of the power supply terminal and the ground terminal and the simultaneous operation of a plurality of output buffer cells.
[0019]
In this way, the combination of groups of external output pins operating simultaneously can be checked.
[0020]
The associating step associates the terminal with the power supply pin, the ground pin, and the external connection pin, and further associates the terminal with the external output pin, and further includes an output buffer having driving capability information. The step of associating cells,
The checking step is based on information on the driving capability of the output buffer cell further associated with the association between the terminal and the external output pin, and the association between the terminal, the power supply pin, and the ground pin. It is also a preferred aspect that it is a step of performing the above check.
[0021]
In this way, the external connection pins of the logic circuit can be associated with the terminals on the semiconductor package in accordance with the drive capability of the output buffer cell.
[0022]
Furthermore, whether or not the name and input / output attribute match between the external connection pin associated with the terminal in the association step and the external connection pin on the logic circuit designed based on the circuit specification. It may have a confirmation step for checking.
[0023]
With such a confirmation step, the external connection pins of the logic circuit can be reliably associated with the terminals on the semiconductor package.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0025]
FIG. 1 is a block diagram of a terminal arrangement apparatus according to an embodiment of the present invention.
[0026]
A terminal arrangement device 10 shown in FIG. 1 is an apparatus to which a terminal arrangement method according to an embodiment of the present invention is applied. The terminal arrangement apparatus 10 includes a template sheet generation unit 11 and a terminal arrangement sheet editing unit 12. A simultaneous output operation group name combination generation unit 13, a simultaneous output operation terminal number constraint check unit 14, a circuit port information extraction unit 15, and a circuit information comparison unit 16.
[0027]
The template sheet generation unit 11 generates a template sheet based on information from the package library file 21. The terminal arrangement sheet 22 is generated when the operator inputs desired data to the generated template sheet. Hereinafter, a detailed description will be given with reference to FIGS. 2, 3, and 4.
[0028]
FIG. 2 is a diagram showing the structure of the package library file.
[0029]
The package library file 21 shown in FIG. 2 includes a pad number (PAD) of a semiconductor chip which is an external connection pin of a logic circuit, a terminal number (PIN) of a semiconductor package, a name of a power supply or ground (power / ground), It is composed of Here, numbers (PAD) 1 to 14, terminal numbers A1 to A14 corresponding to the numbers (PAD) 1 to 14, and names indicating that the terminals represented by the terminal numbers A1, A10, and A14 are power terminals. OVDD is shown. Thus, the terminal arrangement of the power supply terminals among the terminals of the semiconductor package is determined in advance.
[0030]
FIG. 3 is a diagram showing two fields and a template sheet.
[0031]
FIG. 3 shows a first field 26, a second field 27, and a template sheet 28. The first field 26, the second field 27, and the template sheet 28 are displayed on a display unit (not shown) of the terminal arrangement device 10. At the first time, only the first field 26 and the second field 27 are displayed.
[0032]
The first field 26 includes a template button (Template) 26_1, a group button (Group) 26_2, and a check button (Check) 26_3.
[0033]
The template button 26_1 is a button for generating the template 28. When the template button 26_1 is operated by the operator, the template sheet 28 is generated based on the information from the package library file 21 shown in FIG. Is done.
[0034]
The group button 26_2 functions as a grouping function that divides the external output pins among the external connection pins of the logic circuit associated with the terminals on the semiconductor package into groups of external output pins that operate simultaneously according to operations. It is a button that bears.
[0035]
The check button 26_3 checks whether or not the correspondence between the terminal on the semiconductor package and the external output pin is a correspondence that matches a predetermined output terminal simultaneous operation constraint. 14 is a button for causing the user to perform the operation.
[0036]
The second field 27 includes a pad part (PAD) 27_1, a terminal part (PIN) 27_2, a signal part (SIGNAL) 27_3, a cell part (CELL) 27_4, an input / output part (IN / OUT) 27_5, a group Section (GROUP) 27_6, power supply coefficient section (OVDD) 27_7, ground coefficient section (OVSS) 27_8, and message section (Message) 27_9.
[0037]
The pad portion 27_1 and the terminal portion 27_2 are portions for displaying the pad number (PAD) and the terminal number (PIN) constituting the package library file 21 shown in FIG. The signal portion 27_3 is a portion for displaying the signal names of the terminals of the semiconductor package.
[0038]
When the template button 26_1 is operated, a template sheet 28 is generated. Here, the contents of the package library file 21 shown in FIG. 2 are displayed on the pad portion 27_1, the terminal portion 27_2, and the signal portion 27_3 of the template sheet 28.
[0039]
The cell part 27_4 is a part for displaying the name of the IO cell connected to the pad of the semiconductor chip.
[0040]
The input / output unit 27_5 is a part for displaying input / output attributes of signals displayed on the signal unit 27_3.
[0041]
The group part 27_6 is a part for displaying the group name of the output buffer cells operating simultaneously.
[0042]
The power supply coefficient section 27_7 is a section for displaying the cumulative value of the drive coefficient on the power supply side of the output buffer cell (corresponding to an example of drive capability information in the present invention).
[0043]
The ground coefficient part 27_8 is a part for displaying the accumulated value of the drive coefficient on the ground side of the output buffer cell (corresponding to another example of information on the driving ability in the present invention). The accumulated values of these drive coefficients will be described later.
[0044]
The message part 27_9 is a part for displaying an operation check result (OK / NG) of simultaneously operating output buffer cells. The description will be continued with reference to FIG.
[0045]
The terminal arrangement sheet editing unit 12 constituting the terminal arrangement apparatus 1 shown in FIG. 1 is an association function for associating power supply pins, ground pins, and external connection pins of circuit specifications with terminals on a semiconductor package according to the present invention. The terminal arrangement sheet editing unit 12 corresponds to the terminal number (or the pad number of the semiconductor chip) and corresponds to the signal part 27_3, the cell part 27_4, and the input part of the template sheet 28 shown in FIG. A signal name, an IO cell name, and an input / output attribute are assigned to the output unit 27_5. Thereby, the template sheet 28 which is a template is edited, and the terminal arrangement sheet 22 is generated.
[0046]
FIG. 4 is a diagram illustrating a terminal arrangement sheet generated by being edited by the terminal arrangement sheet editing unit.
[0047]
In the terminal arrangement sheet 22 shown in FIG. 4, signal names N1 to N8 and N9 to N11 assigned to terminal numbers A2 to A9 and A11 to A13 are displayed. In addition, IO cell names OBT1, OBT2, OBT3, and OBT4 assigned to terminal numbers A2 to A5, A6 to A8, A11 to 12, and A13 are displayed. In addition, input / output attributes OUT assigned to terminal numbers A2 to A9 and A11 to A13 are displayed.
[0048]
Here, the operator operates the group button 26_2. Then, a group name of output buffer cells that operate simultaneously is assigned. In other words, group names of output buffer cells are defined for output signals and bidirectional signals output from terminals corresponding to simultaneously operating output buffer cells.
[0049]
FIG. 5 is a diagram showing a state in which the group name of the output buffer cell that operates simultaneously when the group button is operated is assigned to the terminal arrangement sheet shown in FIG.
[0050]
The group portion 27_6 of the terminal arrangement sheet 22 shown in FIG. 5 includes a group name A for four output buffer cells OBT1 that operate simultaneously, a group name B for three output buffer cells OBT2 that operate simultaneously, A state in which a group name C is assigned to one output buffer cell OBT2, two output buffer cells OBT3, and one output buffer cell OBT4 that are operating is displayed.
[0051]
Further, the simultaneous output operation group name combination generation unit 13 shown in FIG. 1 plays a role of the group designation function according to the present invention, and one or more of the groups assigned by operating the group button 26_2. Specify the group according to the operation. Here, all combinations (A, B, C, AB, BC, AC, ABC) of the three groups are designated.
[0052]
Furthermore, the output simultaneous operation terminal number constraint check unit 14 shown in FIG. 1 plays the role of the check function referred to in the present invention. It is checked whether or not the correspondence with the output pin is a correspondence that matches a predetermined output terminal simultaneous operation constraint. More specifically, the output simultaneous operation terminal number constraint check unit 14 considers that external output pins belonging to one or more groups designated by the output simultaneous operation group name combination generation unit 13 operate simultaneously. And check.
[0053]
Further, the terminal arrangement sheet editing unit 12 described above associates the terminal with the power supply pin, the ground pin, and the external connection pin, and further associates the accumulated value of the drive coefficient with the association between the terminal and the external output pin. The output simultaneous operation terminal number constraint check unit 14 has a role of associating output buffer cells with the output buffer cell drive coefficient further associated with the association between the terminal and the external output pin. The check is performed based on the accumulated value and the correspondence between the terminal, the power supply pin, and the ground pin. Hereinafter, a description will be given with reference to FIG.
[0054]
FIG. 6 is a diagram showing a state in which the cumulative value of the drive coefficient is displayed on the terminal arrangement sheet shown in FIG.
[0055]
The drive coefficients of the output buffer cells OBT1, OBT2, OBT3, and OBT4 are defined in the output simultaneous operation rule file 23 shown in FIG. 1, and are 3, 2, 3, and 4, respectively. Between the terminal number A1 and the terminal number A10 in the power supply coefficient section 27_7 of the terminal arrangement sheet 22 shown in FIG. 6, the cumulative value (3, 6, 9) of the drive coefficient on the power supply side of each output buffer cell OBT1, OBT2 , 12, 14, 16, 18, 20) are displayed. Further, between the terminal number A10 and the terminal number A14 in the power supply coefficient section 27_7, the cumulative value (3, 6, 10) of the drive coefficient on the power supply side of each output buffer cell OBT3, OBT4 is displayed.
[0056]
Here, the simultaneous output operation terminal number restriction check unit 14 checks (calculates) all combinations of the simultaneous output operation groups, and displays an error display (NG) in the following cases.
[0057]
Allowable drive coefficient of OVDD (OVSS) <drive coefficient of output buffer cell between ΣOVDD (OVSS) / 2
However, OVDD / OVSS indicates the power supply / ground of the output buffer cell.
[0058]
Here, since OVDD (OVSS) exists on both sides of the output buffer cell to be calculated, the addition result (cumulative value) is divided by two.
[0059]
The allowable drive coefficient and the output buffer cell drive coefficient are defined in the output simultaneous operation rule file 23.
[0060]
FIG. 7 is a diagram illustrating a terminal arrangement sheet for explaining the calculation by the simultaneous output operation terminal number constraint check unit.
[0061]
In the terminal arrangement sheet 22 shown in FIG. 7, combinations of all output simultaneous operation groups (A, B, C, AB, BC, AC, ABC) are displayed.
[0062]
Here, when the output simultaneous operation group name = ABC is targeted, NG (output simultaneous operation terminal number error) is displayed in the field of the message part (Message) 27_9 of PAD = 10. This output simultaneous operation terminal number error is calculated as follows.
[0063]
As a calculation target, among output buffer cells arranged on both sides of a PAD = 10 power source in a semiconductor chip, an output simultaneous operation group name is defined as A, B, or C, PAD = 2 to 9, PAD = Output buffer cells assigned to 11-13.
[0064]
Here, the allowable drive coefficient (spec shown in FIG. 7) of OVDD is 8 (from the simultaneous output operation rule file 23).
[0065]
The drive coefficient ΣOVDD (val shown in FIG. 7) of the output buffer cell between PAD1 and PAD10 is
ΣOVDD = (drive coefficient of OBT1 × number of OBT1 + drive coefficient of OBT2 × number of OBT2) / 2 + (drive coefficient of OBT3 × number of OBT3 + drive coefficient of OBT4 × number of OBT4) / 2 = 10.
[0066]
Therefore, NG (spec = 8, val = 10) is displayed in the part corresponding to PAD10 in the message part 27_9. Since the drive coefficient ΣOVDD of the output buffer cell between PAD10 and PAD14 is 10/2 = 5, OK is displayed in the part corresponding to PAD14 in message part 27_9. Further, the drive coefficient ΣOVDD of the output buffer cell between PAD14 and PAD1 is 0, so that OK is displayed in the part corresponding to PAD1 in message part 27_9. When NG is displayed (when an error occurs), the power supply / ground is added and the terminal arrangement is changed, and the above calculation is repeated until there is no error.
[0067]
Thereafter, the circuit port information extraction unit 15 shown in FIG. 1 extracts circuit port information 25 connected to the external connection pins from the circuit data 24.
[0068]
Further, in the circuit information comparison unit 16, whether the circuit port information 25 matches the terminal allocation information of the terminal arrangement sheet 22, and the number of signals in those files is checked. And whether the input / output attributes match is checked.
[0069]
As described above, the terminal arrangement device 10 of the present embodiment associates the terminals on the semiconductor package with the external connection pins of the logic circuit specifications, and the correspondence is a correspondence that matches the predetermined output terminal simultaneous operation restriction. Since it is checked whether or not there is, the external connection pins of the logic circuit can be associated with the terminals on the semiconductor package while checking the consistency with the circuit information from the initial stage of circuit design. Accordingly, it is possible to perform an appropriate terminal arrangement in consideration of noise generated due to the arrangement of the power supply terminal and the ground terminal and the simultaneous operation of a plurality of output buffer cells.
[0070]
【The invention's effect】
As described above, according to the terminal arrangement device and the terminal arrangement method of the present invention, it is possible to perform terminal arrangement in consideration of noise generated due to simultaneous operation of a plurality of output buffer cells.
[Brief description of the drawings]
FIG. 1 is a block diagram of a terminal arrangement device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a package library file.
FIG. 3 is a diagram showing two fields and a template sheet.
FIG. 4 is a diagram illustrating a terminal arrangement sheet generated by being edited by a terminal arrangement sheet editing unit.
5 is a diagram showing a state in which group names of output buffer cells that operate simultaneously when a group button is operated are assigned to the terminal arrangement sheet shown in FIG. 4; FIG.
6 is a diagram showing a state in which the cumulative values of drive coefficients are displayed on the terminal arrangement sheet shown in FIG.
FIG. 7 is a diagram showing a terminal arrangement sheet for explaining calculation by the simultaneous output terminal number restriction check unit;
[Explanation of symbols]
10 Terminal arrangement device
11 Template sheet generator
12 Terminal layout sheet editor
13 Output simultaneous operation group name combination generator
14 Output simultaneous operation terminal number restriction check part
15 Circuit port information extraction unit
16 Circuit information comparator
21 Package library file
22 Terminal Arrangement Sheet
23 Output simultaneous operation rule file
24 Circuit data
25 Circuit port information
26 First field
26_1 Template button (Template)
26_2 Group button (Group)
26_3 Check button (Check)
27 Second field
27_1 Pad part (PAD)
27_2 Terminal (PIN)
27_3 Signal section (SIGNAL)
27_4 Cell part (CELL)
27_5 Input / output unit (IN / OUT)
27_6 Group Department (GROUP)
27_7 Power supply coefficient section (OVDD)
27_8 Ground coefficient part (OVSS)
27_9 Message part (Message)
28 Template sheet

Claims (2)

In a terminal arrangement device that associates external connection pins of a logic circuit, which is a pad of a semiconductor chip, with terminals on a semiconductor package,
A display unit that displays a terminal arrangement sheet that associates external connection pins of a circuit specification including power supply pins, ground pins, and external output pins with terminals on a semiconductor package;
Based on the correspondence between the terminal on the semiconductor package and the external connection pin, the allowable drive coefficient of the power supply pin or the ground pin corresponds to the external output pin arranged between the power supply pins or between the ground pins. An output simultaneous operation terminal number constraint check unit for checking whether or not the cumulative value of the drive coefficient is less than ½ ,
And an external output pin of the group of output co-operation group name combination generating unit for designating in response to operation of the operator to a combination of two or more groups that operate simultaneously,
Characterized in that said checking unit, it is assumed that the external output pins belonging to one of two or more groups specified by the output simultaneous operation group name combination generating unit operate simultaneously, and performs the check A terminal arrangement device. In a terminal arrangement method for associating an external connection pin of a logic circuit, which is a pad of a semiconductor chip, with a terminal on a semiconductor package,
A display step for displaying a terminal arrangement sheet for associating the external connection pins of the circuit specifications including the power supply pins, the ground pins, and the external output pins with the terminals on the semiconductor package on the display unit of the terminal arrangement device ;
Based on the correspondence between the terminal on the semiconductor package and the external connection pin, the allowable drive coefficient of the power supply pin or the ground pin corresponds to the external output pin arranged between the power supply pins or between the ground pins. Whether or not the cumulative value of the drive coefficient is less than ½ is checked by the simultaneous output terminal number constraint check unit of the terminal arrangement device by the operation of the button displayed on the terminal arrangement sheet by the operator. Check step and
Of group of the external output pins that operate simultaneously, the combination of two or more groups, by the operator, in response to operation of the button displayed on the terminal arrangement sheet, simultaneous output operation group of terminals arranged device A group specifying step specified by the name combination generation unit ,
The check step, it is assumed that the external output pins belonging to one of two or more groups specified by the group specifying step are operated at the same time, terminal arrangement wherein the and performs the check .

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