JP2933604B1 - Layout method of semiconductor integrated circuit - Google Patents

Abstract

Kind Code: A1 Provided is a layout method for improving a wiring efficiency in a layout design of a semiconductor integrated circuit having a plurality of power supply systems, improving a degree of integration, and realizing power supply separation by shortening a TAT. A power supply line for supplying power to a primitive cell is connected to a floor plan step and a primitive line.
This is performed between the cell placement step and the primitive cell placement step. In the primitive cell placement step, a region where the wiring name added to the power supply line matches the power supply information of the primitive cell is searched for and the cell is placed. Achieve separation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout method for a semiconductor integrated circuit, and more particularly to a layout method for a semiconductor integrated circuit having a plurality of power supply systems.

[0002]

2. Description of the Related Art Conventionally, a cell-based IC as shown in FIG.
As a layout method of a semiconductor integrated circuit of the system, a primitive cell 1 having power supply terminals 3 and 4 and a primitive cell 2 having power supply terminals 5 and 6 are sequentially arranged, and primitives are provided by power supply lines 7 and 8 of different power supply systems. -Power is supplied to cells 1 and 2 and primitive cells 1 and 2
There is known a method of connecting the two by wiring.

As a layout method of a semiconductor integrated circuit composed of a plurality of power supplies, for example, Japanese Patent Laid-Open No. 9-15354
Japanese Patent Application Laid-Open No. 8 (1999) -2000 discloses that a layout of a plurality of power supply systems can be easily realized by using a power supply separation macro, and even a plurality of power supply systems can be handled in the same manner as a single power supply cell-based IC including a macro. A layout method has been proposed.

FIG. 11 is a flow chart newly showing a processing flow of the layout method described in the publication. FIG.
Referring to, a step of identifying primitive cells connected to a plurality of power supply systems for each system, and a step of arranging a macro cell for power supply separation as an arrangement area of primitive cells connected to different power supply systems, It comprises a step of arranging primitive cells having different power supply systems inside the macro cell. Details are as follows.

First, as a step of identifying the power supply system,
Primitive cells are classified for each power supply based on circuit connection information (netlist) (step A1 in FIG. 11).

[0006] Primitives of the different power supply system classified next
In order to arrange cells, a macro cell for power supply separation is created (step A2 in FIG. 11).

Next, as a process of arranging primitive cells of different power supply system, the macro for power supply separation prepared in step A2
Primitive cells of different power supply systems are arranged inside the cells (steps A5-A7 in FIG. 11).

Next, as a step of arranging cells other than the primitive cells arranged inside the power supply separation macro cell, they are arranged outside the power supply separation macro cell (steps A9-A11 in FIG. 11).

Next, as a power supply line wiring step, a power supply line is wired on the chip to supply power to the arranged primitive cells (step A1 in FIG. 11).
2).

Next, as a wiring process, steps A5-A1
The primitive cells arranged in 1 are wired based on circuit connection information (netlist) (steps A13 to A15 in FIG. 11).

However, in step A14, it is determined whether or not all the nets can be wired. If it is determined that wiring is impossible in or near the power supply separation macro cell, the flow returns to step A2, and the power supply is returned to step A2. Change the size of the separation macro cell.

The layout design of a semiconductor integrated circuit composed of a plurality of power supplies has been performed by using the above method.

[0013]

However, the above-mentioned conventional layout method has the following problems.

The first problem is that there is a great deal of rework for optimizing the arrangement area of the different power supply cells (the size of the macro cell for power supply separation), and the TAT (turnaround time) increases. is there.

The reason is as follows. There are two factors that determine the size of the macro cell for power supply separation designating the placement area of the different power supply system: that a primitive cell can be placed and that it can be wired. In the above-described conventional layout method, the former determination is made in step A8 in FIG. 11, but the latter determination is made in step A1.
4 is performed. Therefore, in step A14 of FIG.
This is because when the size of the power supply separation macro cell needs to be changed, it is necessary to return to the previous step (step A2) of the floor plan.

The second problem is that since the primitive cells are arranged for each power supply system, the wiring efficiency deteriorates and the degree of integration decreases.

The reason is as follows. First, the primitive cells are arranged in consideration of circuit connection information. Therefore, chip size, power supply separation macro,
In order to determine the size of a cell (eg, 111 in FIG. 14), it is necessary to take into account the connection relationship of the entire circuit.

As shown in FIG. 12, in a region 102 and a region 103 divided into regions according to power supply systems, a primitive cell 104 having connection information between different regions, and a primitive cell 105 connected only within the same region. When the arrangement is performed in consideration of the connection information of the entire circuit, it is expected that the primitive cell 104 is arranged in the boundary area between the region 102 and the region 103. This is because primitive cells having a strong connection relationship are arranged close to each other when arranging primitive cells.

As shown in FIG. 13, in a region 107 and a region 108 divided into regions for each power supply system, a primitive cell 109 having connection information between different regions.
And primitive cell 1 connected only in the same area
When the area 107 and the area 108 are arranged in different steps, it is expected that the primitive cells 109 are arranged separately.

This is because wiring information between different regions is ignored because cells are arranged for each region. In the conventional layout method described above, since the inside and outside of the power supply separation macro cell are arranged in separate steps,
Primitive cells having connection information between different areas will be arranged separately.

Accordingly, the present invention has been made in view of the above problems, and has as its object to improve wiring efficiency and layout in a semiconductor integrated circuit having a plurality of power supply systems. Another object of the present invention is to provide a layout method for shortening the TAT and realizing power supply separation.

[0022]

In order to achieve the above object, the present invention provides a layout method of a semiconductor integrated circuit having a plurality of power supply systems, wherein a wiring of a power supply line for supplying power to a primitive cell is arranged in a floor plan. Process and
This is performed between the primitive cell placement step.In the primitive cell placement step, an area where the wiring name added to the power supply line matches the power supply information of the primitive cell is searched for and placed. , To realize power supply separation.

The layout method of the present invention preferably comprises the steps of:
(A) Primitives for each power system based on circuit connection information
A step of classifying cells, (b) a floor plan for each power supply system, (c) a wiring of a power supply line for supplying power to primitive cells, and (d) a circuit connection information. Searching for an area where the wiring name of the power supply line wired in the step (c) matches the power supply information of the primitive cell, determining the arrangement area of the primitive cell, and arranging the primitive cell; ,
(E) wiring the primitive cells.

[0024]

Embodiments of the present invention will be described below. According to the present invention, in a layout design of a semiconductor integrated circuit composed of a plurality of power supplies, a search is made for a region where a wiring name added to a power supply line and power supply information possessed by each primitive cell coincide with each other, and cells are arranged. This is to shorten the TAT of the layout design that realizes separation. That is, in the layout method of the present invention, in a preferred embodiment, wiring of a power supply line for supplying power to a primitive cell is performed between a floor plan step and a primitive cell arranging step.
In the cell placement process, the wiring name added to the power supply line,
Power supply separation is realized by searching for an area where the power supply information of the primitive cell matches and arranging the cell.

More specifically, referring to the flowchart of FIG. 1, in the layout method of the present invention, in a preferred embodiment, each primitive is set in step A5 after the floor plan process and before the primitive cell placement process. -Wiring a power supply line to supply power to the cell.

Then, in step A6 of the primitive cell arranging step, based on the circuit connection information, a region where the power supply information of the primitive cell and the wiring name of the power supply line wired in step A5 match is searched for. The determined area is determined as a primitive cell arrangement area (steps A7 and A8).

That is, in step A7, step A
It is checked whether or not the power supply line name matches the power supply information of the primitive cell for the arrangement area obtained in 6. In step A7, if it is confirmed that the power supply information matches, the arrangement area is determined (step A8). If not, the procedure returns to step A6 and the arrangement area is searched again.

Then, in step A9 of the primitive cell arranging process, it is checked whether there is any unarranged cell.
Step A until all primitive cells are placed
The processing from step 6 to step A8 is repeated.

Then, it is determined whether or not the wiring is possible based on the result of the schematic wiring. If the wiring is possible, detailed wiring is performed. If it is determined that the wiring is not possible, a fundamental review of the chip size is necessary. In the case where the wiring is strict in the area where the power supply is separated or in the vicinity thereof and it is necessary to review the expansion of the area, etc. The power supply line for supplying power to the primitive cells is adjusted.

[0030]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a flowchart showing a processing flow of an embodiment of the present invention. Referring to FIG. 1, one embodiment of the present invention includes a step of identifying a power supply system, a step of performing a floor plan for each power supply system, and a step of wiring a power supply line for supplying power to primitive cells. The method includes a step of arranging primitive cells for the net name of the power supply line, and a step of wiring the primitive cells.

As described above, a method of wiring a power supply line for supplying power to a primitive cell is well known in the related art, and a known method is used in an embodiment of the present invention. .

In one embodiment of the present invention, a wiring step of a power supply line for supplying power to a primitive cell (FIG. 1)
Step A5) is performed between the floor plan process and the primitive cell arranging process. In the primitive cell arranging process, the area where the wiring name added to the power supply line and the power information possessed by the primitive cell match is determined. By searching and arranging cells (steps A6-A9 in FIG. 1),
Power supply separation is achieved.

In the following, the operation of the embodiment in which the present invention is applied to a circuit having two power supplies, VDD1 and VDD2, will be described in detail with reference to the flowchart of FIG.

First, in one embodiment of the present invention, in a semiconductor integrated circuit composed of a plurality of power supplies, a VDD1-related circuit and a VDD2-related circuit are classified by power supply system as shown in FIG. 3 (steps in FIG. 1). A1).

Next, in step A4 of FIG. 1, an arrangement area is designated for each power supply system classified in step A1. As shown in FIG. 5, different arrangement areas are overlapped with each other, as shown in FIG. 5, in order to increase the degree of freedom of wiring in power supply line wiring (step A5) described later. In the example shown in FIG. 5, the primitive cells 21, 2 shown in FIG.
2 are arranged on the side of the arrangement region 23 on the one power supply system side, and the arrangement region 24 and the arrangement region 23 on the other power supply system side partially overlap each other.

Next, in the wiring step of the power supply line (step A5 in FIG. 1), as shown in FIG. 2, the power supply terminals 3 and 4 of the primitive cell 1 and the power supply line of the primitive cell 2 Wiring of power supply lines 7 and 8 for supplying power is performed on 5 and 6. Wiring of the power supply line is performed based on the floor plan specified in step A4. As shown in FIG. 6, by using a vertical path or the like,
Perform power line separation.

Next, a description will be given of the process of arranging primitive cells. An area where the wiring name of the power supply line wired in step A5 matches the power supply information of the primitive cell based on the circuit connection information is searched for. Determine the cell placement area (steps A6 to A6 in FIG. 1)
A9).

In the present embodiment, an example of a case where a power supply terminal of a primitive cell is used as power supply information of a primitive cell will be described.

As shown in FIG. 6, a VDD1 terminal 35,
When arranging the primitive cell 34 having the GND terminal 36, the terminal name of each power terminal included in the primitive cell 34 matches the line name of the power line wired in step A5 based on the circuit information. An area is searched (step A6 in FIG. 1).

Next, in step A7 of FIG. 1, it is confirmed whether the power supply line name matches the power supply terminal name of the primitive cell with respect to the arrangement position of the primitive cell determined by the search.

As a result of the confirmation, as shown in FIG. 7, the power supply terminal 42 of VDD1 of the primitive cell 41
When the primitive cell 41 is arranged on the power supply line 44 of VDD2, the arrangement position of the primitive cell 41 is searched again (return to step A6).

Also, as shown in FIG.
When the power supply terminals 52 and 53 of the cell 51 are arranged on the power supply lines 56 and 55, respectively, and the power supply systems match, the arrangement position is determined (step A in FIG. 1).
8) Perform the following steps.

In the next step A9, the presence or absence of unplaced cells is checked, and steps A6 to A9 are repeated until there are no unplaced cells.

Lastly, a description will be given of a step of wiring to the arranged primitive cells and macro cells such as RAM / ROM.

After the placement of all the cells is completed, a wiring plan is made as schematic wiring based on the circuit connection information (step A10 in FIG. 1).

In step A11 of FIG. 1, it is determined whether or not wiring is possible based on the result of the schematic wiring (step A10). Here, if it is determined that the wiring is impossible, the return destination of the flow differs depending on the situation described below.

As a first situation, when wiring is strict for the entire chip and a fundamental review of the chip size is required, the return destination is step A2, and the chip size is adjusted.

As a second situation, as shown in FIG. 9, when the wiring is strict in the area 61 where the power supply is separated or in the vicinity thereof, and it is necessary to review the expansion of the area or the like, a return is made. The first is step A5 in FIG. 1, and the wiring of the power supply line is adjusted. The power supply line VDD2 in FIG.
FIG. 10 shows an example of the result obtained by adjusting the wiring and arranging the primitive cells.

If it is determined in step 11 in FIG. 1 that wiring is possible, the last detailed wiring is performed to complete the layout.

In one embodiment of the present invention, the method
A layout design of a semiconductor integrated circuit composed of a plurality of power supplies is realized.

In one embodiment of the present invention, when the wiring in the area where the power supply is separated in the wiring step is severe and it is necessary to review the area (loop A when NO is determined in step A11 in FIG. 1), the floor The TAT can be shortened because it can be reviewed in the post-process of the plan (step A5 in FIG. 1).

This is because, in the conventional layout method, when the area is reviewed as described above, step A2 in FIG.
Returning to (pre-process of floor plan) and changing the macro cell for power supply separation, in one embodiment of the present invention, in step A5 of FIG. 1 (post-process of floor plan), This is because the arrangement area can be changed by changing the power supply line.

[0053]

As described above, according to the present invention,
The following effects are obtained.

The first effect of the present invention is that when the wiring in the area where the power supply is separated in the wiring step is strict and it is necessary to review the area, it can be reviewed in a later step of the floor plan. It means shortening.

The reason is as follows. With the conventional layout method, when reviewing the above-mentioned area,
For example, step A2 in FIG. 11 (pre-process of floor plan)
According to the present invention, the placement area can be changed by changing the power supply line in the post-process of the floor plan, while the power supply separation macro cell must be changed. is there.

The second effect of the present invention is that, regardless of the power supply system, it is possible to arrange the primitive cells in consideration of the connection of the entire circuit, to obtain a result with high wiring efficiency, and to achieve a high degree of integration. Is to contribute to the improvement of

The reason is that, in the present invention, the arrangement is performed for the entire circuit irrespective of the power supply system, so that the primitive cells can be arranged in consideration of the wiring of the entire circuit, and the primitive cells having different power supply systems can be arranged.・ Efficient wiring results can be obtained for wiring between cells.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a processing flow according to an embodiment of the present invention.

FIG. 2 is a layout diagram for explaining an embodiment of the present invention.

FIG. 3 is a layout diagram for explaining an embodiment of the present invention.

FIG. 4 is a layout diagram for explaining an embodiment of the present invention.

FIG. 5 is a layout diagram for explaining an embodiment of the present invention.

FIG. 6 is a layout diagram for explaining an embodiment of the present invention.

FIG. 7 is a layout diagram for explaining an embodiment of the present invention.

FIG. 8 is a layout diagram for explaining an embodiment of the present invention.

FIG. 9 is a layout diagram for explaining an embodiment of the present invention.

FIG. 10 is a layout diagram for explaining an embodiment of the present invention.

FIG. 11 is a flowchart for explaining a processing flow of a conventional layout method.

FIG. 12 is a layout diagram for explaining a problem of the conventional method.

FIG. 13 is a layout diagram for explaining a problem of the conventional method.

FIG. 14 is a layout diagram for explaining a conventional method.

[Explanation of symbols]

1, 2 Primitive cells 3, 4 Power supply terminals 5, 6 Power supply lines 11, 12 Groups of circuits divided by a power supply system 21, 22 Primitive cells 23, 24 Placement areas 31, 32, 33, 44, 45, 46 , 54, 55, 5
6 Power supply lines 34, 41, 51 Primitive cells 35, 36, 42, 43, 52, 53 Primitive cells
Cell power supply unit 61 Power supply separation area 101, 106 Chip 102, 103, 107, 108 Arrangement area 104, 105, 109, 110, 112, 113 Primitive cell 111 Power supply separation macro cell

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/82 H01L 21/822 H01L 27/04

Claims (7)

(57) [Claims] In a layout design of a semiconductor integrated circuit having a plurality of power supply systems, wiring of power supply lines for supplying power to primitive cells is performed between a floor plan step for each power supply system and a primitive cell arrangement step. In the primitive cell arranging step, a power supply separation is performed by searching for a region where the wiring name added to the power supply line matches the power supply information of the primitive cell and determining the arrangement of the primitive cell. A layout method characterized by realizing: 2. A method for laying out a semiconductor integrated circuit having a plurality of power supply systems, comprising: (a) grouping primitive cells by power supply system; and (b) connecting to each power supply based on grouping information for each power supply system. (C) wiring a power supply line for supplying power to the primitive cell based on the floor plan; and (d) wiring the power supply line. Above, primitive
When arranging the cells, arranging the primitive cells in an area that matches the power information of the primitive cells, including, when arranging the primitive cells connected to each power supply,
A layout method for a semiconductor integrated circuit, characterized in that the layout is suitable for wiring connection of the entire circuit. 3. A result of the rough wiring subsequent to the step (d) is checked whether wiring is possible or not, and if it is determined that wiring is impossible, the power supply separation area or its vicinity is determined. If the wiring is severe and it is necessary to make a change such as expansion of the area, the process returns to the power supply wiring step of the step (c), and the power supply line for supplying power to each primitive cell is adjusted. 3. The layout method for a semiconductor integrated circuit according to claim 2, wherein the method is performed. 4. A result of the general wiring subsequent to the step (d) is checked whether wiring is possible or not, and if it is determined that wiring is impossible, if a chip size review or the like is necessary, 3. The process returns to the floor planning step of the step (b) and starts with a chip size adjustment processing.
The layout method of the semiconductor integrated circuit described in the above. 5. A layout method for a semiconductor integrated circuit having a plurality of power supply systems, wherein: (a) a primitive integrated circuit for each power supply system based on circuit connection information;
A step of classifying cells; (b) a step of performing a floor plan for each power supply system; (c) a step of wiring a power supply line for supplying power to the primitive cells; and (d) based on circuit connection information. A search is made for a region where the wiring name of the power supply line wired in the step (c) matches the power supply information of the primitive cell, and
A layout method for a semiconductor integrated circuit, comprising: determining a cell arrangement region and arranging primitive cells; and (e) wiring the primitive cells. 6. The method according to claim 1, wherein the step (e) is a schematic wiring step, and a step of checking whether wiring is possible based on the result of the schematic wiring;
It consists of a detailed process. It is checked whether or not the wiring is possible based on the result of the general wiring. If a change such as is necessary, the process returns to the power supply wiring step of the step (c), and the wiring of the power supply line for supplying power to each primitive cell is adjusted. 6. The layout method for a semiconductor integrated circuit according to claim 5 , wherein: 7. A layout design of a semiconductor integrated circuit having a plurality of power supply systems, wherein (a) a primitive integrated circuit for each power supply system based on circuit connection information;
(B) floorplanning for each power supply system, (c) wiring a power supply line for supplying power to primitive cells, (d) processing based on circuit connection information ( A search is made for a region where the wiring name of the power supply line wired in c) matches the power supply information of the primitive cell, and
A process of deciding a cell placement area and arranging primitive cells; and (e) a process of wiring the primitive cells, the above-described processes (a) to (e) being performed by a computer. Recording medium on which the program of the above is recorded.