JPS59197189A - Printed board and lsi terminal assining system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to terminal allocation for printed boards and LSIs, and in particular, both internal wiring of printed boards and LSIs, and interconnection of printed boards or LSIs in upper layer components. This is a method to obtain a good wiring rate.

[Background of the invention]

Conventional terminal allocation methods for printed boards and LSIs determine terminals in such a way as to obtain a good wiring rate for the internal wiring of the printed boards and LSIs, or determine terminals in order to obtain good wiring rates for the internal wiring of the printed boards or LSIs, or One method was to determine the terminals so that the wiring rate could be obtained. Therefore, the above printed board and L
Either the internal wiring of the SI or the interconnection of the printed boards or LSIs in higher-level components has the disadvantage that a good wiring rate is not necessarily guaranteed.

[Purpose of the invention]

The purpose of the present invention is to improve the terminal damage state of printed boards and LSIs in order to obtain good wire rates for both the internal dark lines of printed boards and LSIs, and the interconnections of the printed boards or LSIs in higher-level components. Our goal is to provide the following.

[Summary of the invention]

The present invention deals with the terminal assignment of printed circuit boards and LSIs, and the terminal assignment state affects the ease of printing both terminal wiring of printed circuit boards and LSIs, the above-mentioned Grino) 8 in upper layer components, and interconnection of LSIs. From the fact that gives
Macroscopic terminal assignment so that the mutual shoulder lines of the terminals are the shortest?
In addition, detailed terminal assignments will be made so that the internal wiring of the printed board and LSI will be shortened. Both are based on the idea that printed wiring becomes easier.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. This embodiment is an example of terminal assignment of an LSI mounted on a printed board, and relates to an electronic component consisting of two levels. This embodiment consists of the following steps (1) to (5).

(1) Regarding LSIs 2 to 7 mounted on printed board 1 in Figure 1, by assuming that the mutual connections between LSIs 8 and 8 are connected from a certain point within the LSI, it is possible to connect LSIs 2 to 7. Mutual connection! Calculate the length a, and make sure that the two wires on the printed board 1 are connected so that the mutual connection length is the minimum.
The mounting positions of LSIs 7 to 7 are determined.

(2) In FIG. 2, 9 is an example of LSI 2 to 7 in FIG. Divide. In this embodiment, the LSI is divided into four groups according to the sides of the LSI where the terminals are located, but the number of groups can be set arbitrarily.

(31 (For the LSI shown in FIG. 3, whose mounting position on the printed board was determined in step 11,
The direction in which the other LSIs 21 and 22 to which the signal lines 17 and 19 connected to the outside from the SI exist is checked, and in the LSI 16, terminal groups 14 and 22 are located in the direction in which the LSIs 21 and 22 are present. 1 each to 13
Assign external connection signal lines 7 and 19. In the same way, connect all external connection signal lines 11 to 14 in the LSI.
Assign to any terminal group.

(4123 is the LSI for which external connection signal lines have been assigned to terminal groups in step (6).23
In this LSI, the 26 gate groups are arranged so that the interconnection of the gate groups is the shortest and the distance between the gate group to which the external connection signal line is connected and the terminal group to which the external connection signal line is assigned is the shortest. Place it on the LSI so that

(5) In the 23 LSIs for which the gate group arrangement has been completed, 27 external connection signal lines are allocated to the 25 terminals in the 11 terminal groups so that the 27 external connection signal lines are the shortest. At this time, if there is an electrical constraint such as prohibition of simultaneous switching signal lines adjacent to each other, terminals are determined in consideration of the constraint.

A similar operation is repeated for all external connection signal lines assigned to the terminal group, and then repeated for all terminal groups within the LSI.

Although this embodiment relates to a two-layer electronic component, the same procedure can be applied to a multi-layer electronic component. According to this embodiment, there is an effect that a good wiring rate can be obtained for internal wiring and interconnection between LSIs on a printed board.

〔Effect of the invention〕

According to the present invention, the layout of printed circuit boards and LSI nodes is carried out in such a way that both the internal connections between the printed circuit boards and LSIs and the interconnections of the printed circuit boards or LSIs in upper layer components are minimized. Also, there is an effect of improving the wiring rate of internal connections of LSIs and improving the wiring rate of mutual connections of the printed boards or LSIs in upper layer components.

[Brief explanation of drawings]

1 to 4 show embodiments of the present invention, FIG. 1 is a conceptual diagram of determining the mounting position of an LSI on a printed board, FIG. 2 is a terminal layout diagram of the LSI, and FIG. 6 is an external connection on the LSI. FIG. 4 is a conceptual diagram of the assignment of signal lines to terminal groups. FIG. 4 is a conceptual diagram of the assignment of external connection signal lines to terminals in a terminal group. 1 Printed board, 2-7...LSI, 8...L
Si mutual connection, 9-LSI, 10 ・Terminal, 1
1 to 14...terminal group to 15...printed board,
16,21.22...LSI, 17, 19
External connection signal line, 23...LSI, 25...terminal, 26
Gate, 27...External connection signal line. Representative patent attorney Akio Takahashi $ / Pu 2nd session

Claims (1)

[Claims] 1. In a printed board or LSI (lower layer component) of an electronic device that is hierarchically designed such that an LSI is mounted on a printed board and the printed board is further mounted on a motherboard, external connections are made from the lower layer component via terminals. When assigning signal lines connected to terminals to terminals, group the terminals according to their positions, and check the placement positional relationship of lower layer components in higher layer components.
Allocate the external connection signal line to a terminal group that exists in the direction in which other lower layer components to which the external connection signal line is connected are placed, and further ensure that the external connection signal line is the shortest within the lower layer component. By allocating the above external connection signal lines to the terminals in the terminal group so as to satisfy the electrical constraints, both the internal connections of lower layer components and the mutual connections between lower layer components in higher layer components can be achieved. A terminal allocation method for printed circuit boards and LSIs, which is characterized by obtaining a good wiring rate.