JP2817897B2 - Video signal processing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit suitable for an electronic endoscope.

[Prior Art and Problems to be Solved by the Invention] Conventionally, in a display device or the like, a video signal is converted into a digital signal and stored in an image memory, and screen data is read out from the image memory and converted into an analog video signal. In some cases, various types of image processing, for example, display of a still image, and the like are made possible. In this case, in order to reduce the memory capacity of the image memory, the video signal in the flyback period or the like is removed, and only the video signal in the image period is stored in the image memory. By the way, in the electronic endoscope device, it is necessary to reduce the diameter of the insertion portion of the endoscope, so that the resolution of an image pickup device such as a CCD provided at the distal end portion of the insertion portion cannot be increased. For this reason, the taken image of the body cavity is displayed on only a part of the display screen without using the entire area of the display screen. Therefore, as described above, by not storing the video signal in the non-image area in the image memory, the effect of saving the memory capacity is extremely high.

FIG. 5 is a block diagram showing such a conventional video signal processing circuit.

The video signal is converted into a digital signal, and only the signal in the image period is stored in the image memory 1 as described above. A video signal from the image memory 1 is input to a D / A conversion circuit 2, converted into an analog video signal, and applied to a terminal a of an analog switch 3. On the other hand, a predetermined reference voltage is applied to the terminal b of the switch 3 from the power supply 4. The switch 3 receives a switching signal such as a retrace pulse or the like, and switches and selects the terminals a and b. That is, the switch 3 outputs the video signal from the D / A conversion circuit 2 from the common terminal c during the image period of the scanning period, and applies a predetermined reference voltage to the common terminal c during the non-image period such as the retrace period.
Output from. The output from the switch 3 is output to the output terminal 6 via the output buffer circuit 5. Normally, the reference voltage of the power supply 4 is set to the black level.

As described above, by outputting the reference voltage in the non-image period such as the flyback period, the data in the non-image period not stored in the image memory 1 is complemented. However, since the analog switch 3 switches between the analog video signal and the reference voltage, the frequency characteristics and the S / N ratio of the video signal deteriorate. There is also a problem that spike noise is superimposed on the video signal during the switching operation of the analog switch 3.

Therefore, regarding switching between the video signal and the reference voltage,
A method of performing digital processing may be employed. FIG. 6 is a block diagram showing such a conventional video signal processing circuit.

From the image memory 1, a digital video signal during the image period is output to the multiplexer 7. Multiplexer 7
Operate when an operation voltage of 5 V is applied from the power supply terminal 8.
The multiplexer 7 outputs a digital signal indicating a black level when the switching signal from the switching signal input terminal 9 indicates a non-image period, and outputs a digital signal indicating a black level when the switching signal indicates the image period. A digital video signal from the image memory 1 is output. The signal from the multiplexer 7 is supplied to the D / A conversion circuit 2 to be converted into an analog signal, and output to the output terminal 6 via the output buffer circuit 5.

With such a configuration, digital processing is performed at the time of switching, so that frequency characteristics and S / N ratio do not deteriorate. However, since the multiplexer 7 is used to switch the output between the image period and the non-image period, there is a problem that the circuit becomes complicated.

The present invention has been made in view of such a problem, and provides a video signal processing circuit that can be configured with a simple circuit and that can prevent deterioration of characteristics of a video signal. The purpose is to:

[Means for Solving the Problems] A video signal processing circuit according to the present invention includes a control signal output circuit that outputs a control signal in a predetermined period corresponding to a predetermined region of a screen, and stores a digital video signal in an image period. An image memory for sequentially outputting data stored based on the control signal or for setting an output terminal to a high impedance state, and a resistance means connected between the output terminal of the image memory and a reference potential point or a power supply; Connected to an output terminal of the image memory, inputting data stored in the image memory during the predetermined period, and inputting data indicating a predetermined level during a period when the output terminal of the image memory is in a high impedance state. D / A that converts the data of the
And a conversion circuit.

[Operation] In the present invention, a video signal of an image period is stored in the image memory, and the video signal is output in a predetermined period corresponding to a predetermined region of the screen. Thereby, the video of the image period is displayed in a predetermined area on the screen. On the other hand, during a period other than the predetermined period, the output terminal of the image memory is in a high impedance state, and the D / A conversion circuit has a value determined by a resistor connected between the output terminal of the image memory and the reference potential point or the power supply. Is input. Therefore, during this period, for example, a digital signal indicating a black level can be supplied to the D / A conversion circuit, and a video in a non-image period that is not stored in the image memory can be complemented.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a video signal processing circuit according to a first embodiment of the present invention, and FIG.
FIG. 4 is a block diagram showing a control signal output circuit 18 that outputs a control signal to be supplied to the control signal generator 1.

The input terminal 10 receives an analog video signal of an image period. The input terminal 10 is connected to the collector of the clamping transistor Q1 via the coupling capacitor C1. A pulse in a pedestal period is applied to the base of the transistor Q1 via the terminal 11. The emitter of the transistor is connected to the reference potential point via the capacitor C2 and to the output terminal of the buffer circuit 12.
An input end of the buffer circuit 12 is connected to a sliding end of a variable resistor R1 connected between the power supply 13 and a reference potential point. The connection point between the capacitor C1 and the collector of the transistor Q1 is connected to the A / D conversion circuit 15 via the buffer circuit 14.

The A / D conversion circuit 15 outputs an analog video signal based on a high-level (hereinafter, referred to as “H”) and low-level (hereinafter, referred to as “L”) reference voltages supplied to the HR terminal and the LR terminal, respectively. Is converted into a digital signal and output to the image memory 17. The HR terminal is supplied with a reference voltage of “H” from the power supply 13, and the LR terminal is connected via a buffer circuit 16 from a connection point of resistors R 2 and R 3 connected between the power supply 13 and a reference potential point. An "L" reference voltage is provided.

The image memory 17 sequentially stores the video signals from the A / D conversion circuit 15, and controls the control signal output circuit 18 shown in FIG.
Is supplied to an output enable terminal (not shown) to output the stored screen data from each output terminal.
The data is output to the D / A conversion circuit 19. Further, each output terminal of the image memory 17 is connected to a reference potential point via a resistor R4, R5, R6, respectively, or a power terminal 20 via a resistor R7.
, And when the control signal is “L”, a high impedance state is established. The D / A conversion circuit 19 is provided with a reference voltage of “H” from the power supply 13 at the HR terminal, and a resistor connected between the power supply 13 and the reference potential point at the LR terminal.
A reference voltage of “L” is supplied from a connection point of R4 and R5 via a buffer circuit 21, and the input digital signal is converted into an analog signal and output. The output of the D / A conversion circuit 19 is led to an output terminal 23 via a capacitor C3 and a buffer circuit 22.

The input terminal 24 of the control signal output circuit 18 shown in FIG.
The sampling clock of the D conversion circuit 15 is input, the horizontal synchronization signal is input to the input terminal 25, and the vertical synchronization signal is input to the input terminal 26. The 10-bit counter 27 counts the clock input to the clock terminal CK and outputs a count output to the ROM 29. The 8-bit counter 28 counts the horizontal synchronization signal input to the clock terminal CK and outputs a count output to the ROM 30. The counter 27 is cleared by inputting a horizontal synchronization signal from the input terminal 25 to the clear end CL, and the counter 28 is cleared by inputting a vertical synchronization signal from the input terminal 26 to the clear end CL.

The ROM 29 supplies the data stored with the address specified by the count output of the counter 27 to one end of the AND circuit 31. The ROM 30 supplies the data stored with the address specified by the count output of the counter 28 to the other end of the AND circuit 31. AND circuit 31 is ROM29,30
The control signal of "H" is supplied to the output enable terminal of the image memory 17 via the output terminal 32 only when all the outputs are "H".

Next, the operation of the video signal processing circuit thus configured will be described with reference to FIG. FIG. 3 is an explanatory diagram for explaining the relationship between the control signal of the control signal output circuit 18 and the display on the screen 35.

A video signal for an image period is input via the input terminal 10. During the pedestal period of the video signal, the transistor Q1 is turned on. Thus, the video signal input via the coupling capacitor C1 is clamped based on the voltage at the sliding end of the variable resistor R1. The A / D conversion circuit 15 converts the clamped video signal into a digital signal based on the "H" and "L" reference voltages and outputs the digital signal to the image memory 17. The image memory 17 sequentially stores the digital video signals.

On the other hand, the clock supplied to the A / D conversion circuit 15 is also supplied to the clock terminal CK of the counter 27 via the input terminal 24. The counter 27 counts the clock and supplies a count output to the ROM 29. As a result, the address is sequentially specified in the ROM 29, and the stored data is sequentially output to the AND circuit 31. The count value of the counter 27 is cleared in a 1H cycle (one horizontal cycle), and each count in one horizontal period is indicated by the count value. The ROM 29 stores "H" data at a predetermined series of addresses and "L" data at other addresses. When the count value of the counter 27 indicates the period A in FIG. , “H” data is output. On the other hand, the counter 28 counts the horizontal synchronizing signal until it is cleared by the vertical synchronizing signal, and the count value indicates a predetermined timing in a 1 V period (one vertical period). ROM 30 is third based on the count value of count 28
When the period B in the drawing is shown, the data of “H” is output only during this period. In the AND circuit, both outputs of ROM29 and 30 are "H"
In this case, the control signal of "H" is given to the output enable terminal of the image memory 17.

The image memory 17 sequentially outputs the stored data by receiving a control signal of “H” from the control signal output circuit 18 and, when the control signal is “L”, sets the output terminal to a high impedance state. . That is, in the D / A conversion circuit 19,
Data stored in the image memory 17 is input during periods A and B in FIG. 3, and data (for example, data indicating a black level) determined by the resistors R4 to R7 is input during the other periods. The D / A conversion circuit 19 converts the input digital signal into an analog signal based on the “H” or “L” reference voltage and outputs the analog signal. The display screen 35 is driven by the video signal output from the output terminal 23 to display an image. Thus, the image memory 17 is stored in the shaded area on the display screen 35.
Is displayed on the basis of the screen data from, and a black level image is displayed in other areas.

As described above, in the present embodiment, the control signal is applied to the output enable end of the image memory 17 at a predetermined timing corresponding to the display area of the screen, and the screen data is output during this period and the output signal is output during another period. The end is set to a high impedance state to complement data in a non-image period that is not stored in the image memory 17, thereby enabling switching with a simple configuration without deteriorating the characteristics of a video signal.

Although the level of the video signal input via the input terminal 10 is 0, it is necessary to adjust the variable resistor R1 so that the video signal of the level 0 is output from the output terminal 23. If there is an offset in the preceding circuit that is not performed, the output level may be adjusted to be 0 when the input level of the preceding circuit is set to 0. Further, it is easier to adjust the variable resistor R1 if each output terminal of the image memory 17 is connected to the reference potential point or the power supply terminal 20 via the resistors R4 to R7. The “L” reference voltage applied to the A / D converter circuit 15 is obtained by the voltage division of the resistors R2 and R3, and the “L” reference voltage of the D / A converter circuit 19 is the resistance voltage of the resistors R8 and R9. The difference between the “H” reference voltage and the “L” reference voltage is the resistance R
Since it is determined by R2, R3, R8, and R9, the influence on the output can be reduced even when the power supply voltage of the power supply 13 fluctuates.

In the present embodiment, the output terminal of the image memory 17 has been described as being capable of being in a high impedance state. A tristate buffer circuit may be provided between the circuit 19 and the circuit 19 to control the tristate buffer circuit. Even in this case, the circuit scale can be reduced as compared with the configuration in which the multiplexer is provided.

FIG. 4 is a circuit diagram showing a video signal processing circuit according to a second embodiment of the present invention. In FIG. 4, the same components as those in FIG.

In the present embodiment, by using the FETs Q ₂ in place of the transistor Q1 for clamping, constant clamping voltage resistors R10, R
Obtained with a partial pressure of 11. Further, the voltage from the power supplies 13 and 33 is supplied to the LR terminal of the A / D conversion circuit 15 via the buffer circuit 16, and the voltage from the power supplies 13 and 34 is supplied to the LR terminal of the D / A conversion circuit 19 through the buffer circuit 21. Have given through. The image memory 17
Are connected to reference potential points via resistors R12 to R15, respectively.

In the embodiment configured as described above, it is not necessary to consider the collector-emitter voltage VCE as in the case of the transistor Q1, and the clamp voltage can be set by a constant voltage by the resistors R10 and R11. Also, by using high-precision power supplies 33 and 34, the A / D conversion circuit 15 and D / A
The accuracy of the reference voltage applied to the conversion circuit 19 is improved, and highly accurate A / D conversion and D / A conversion can be performed.

[Effects of the Invention] As described above, according to the present invention, it is possible to configure with a simple circuit and to prevent deterioration of characteristics of a video signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a video signal processing circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram showing a control signal output circuit for outputting a control signal supplied to an image memory, and FIG. 3 is a control signal. FIG. 4 is an explanatory diagram for explaining the relationship between the control signal of the output circuit 18 and the display on the screen, FIG. 4 is a circuit diagram showing a video signal processing circuit according to a second embodiment of the present invention, and FIGS. FIG. 1 is a block diagram showing a conventional video signal processing circuit. 15: A / D conversion circuit, 16: Image memory, 19: D / A conversion circuit, R4 to R7: Resistance.

Claims (1)

(57) [Claims] 1. A control signal output circuit for outputting a control signal during a predetermined period corresponding to a predetermined area of a screen, and storing a digital video signal during an image period and sequentially outputting stored data based on the control signal. Or an image memory for setting an output terminal to a high impedance state; a resistance means connected between the output terminal of the image memory and a reference potential point or a power supply; Is a D / A converter that inputs data stored in the image memory, inputs data indicating a predetermined level during the period when the output end of the image memory is in a high impedance state, converts these data into analog signals, and outputs them. And a video signal processing circuit.