JPH0771244B2 - Video signal level control circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a level control circuit for a video signal in a liquid crystal television.

[Prior art and its problems] Conventionally, a liquid crystal television using a liquid crystal display panel converts a video signal amplified by a video amplification circuit into a digital signal by an A / D conversion circuit and displays the liquid crystal display panel by this digital signal. I'm trying to drive. In this case, the light-> dark level of the video signal is displayed in, for example, 16 gradation levels.
However, the liquid crystal display panel has a problem in that the gradation range from the white level to the black level is narrow due to its nature, and it is difficult to obtain an image with good contrast.

[Object of the Invention] The present invention has been made in view of the above points, and provides a level control circuit for a video signal, which can effectively use the dynamic range of gradation in a liquid crystal display panel and obtain an image with good contrast. The purpose is to

SUMMARY OF THE INVENTION According to the present invention, a substantially minimum value in a certain period of a video signal is clamped to a preset lower limit reference voltage, and a substantially maximum value is set as an upper limit reference voltage which is a peak value in the period. , A video signal can be A / D converted according to its level.

[Examples of the Invention] Details of the present invention applied to a color liquid crystal television will be described below. First, the overall schematic configuration will be described with reference to FIG. In FIG. 1, reference numeral 11 is an analog switch circuit, to which the color signals R, G, B sent from a video signal processing circuit (not shown) in the preceding stage are inputted. The analog switch circuit 11 has three components, as shown in detail in FIG.
The switching operation is controlled by sampling clocks CKR, CKG, CKB provided from a timing generation circuit (not shown). The analog switch circuit 11 samples the primary color signals R, G, B in time division by the sampling clocks CKR, CKG, CKB, that is, sequentially at different timings, and then synthesizes the serial color signals S-RG.
It is converted to B and output to the automatic level control circuit 12 whose details will be described later. Further, 13 is a blanking signal generation circuit 13, which produces a blanking signal ▲ ▼ by a horizontal synchronizing signal φ _H and a vertical synchronizing signal φ _V sent from a synchronizing signal separating circuit (not shown). This blanking signal ▲
▼ is a signal that becomes high level only during the effective screen and becomes low level during the blanking period, and is sent to the automatic level control circuit 12. The auto level control circuit 12 controls the level of the serial color signal S-RGB in accordance with the blanking signal ▲ ▼ from the blanking signal generating circuit 13 and outputs the video input signal I to the A / D conversion circuit 14.
Create n and upper limit reference voltage Vr ++. Further, the A / D conversion circuit 14 has a video signal input signal In and an upper limit reference voltage Vr ++
At the same time, the lower limit reference voltage Vr- is given. The A / D conversion circuit 14 sequentially converts the signal from the auto level control circuit 12 into a 4-bit digital signal and outputs it to the multiplexer 15. The multiplexer 15 synchronizes the signals A / D converted by the A / D conversion circuit 14 with sampling clocks CKR, CKG, CKB and digital signals DR1 to DR4, DG1 to DG4 for the respective primary colors of R, G, B. Separated into DB1 to DB4 and output to a liquid crystal display (not shown).

Next, details of the automatic level control circuit 12 will be described with reference to FIG. The auto level control circuit 12 includes a switching element such as an NPN transistor Tr1, a PNP transistor Tr2, and diodes D1 and D2.
It is mainly composed of. Then, Vcc power is supplied to the collector of the transistor Tr1 and the blanking signal (1) from the blanking signal generating circuit 13 of FIG. 1 is input to the base of the transistor Tr1 via the resistor R1. The emitter of the transistor Tr1 is grounded via the resistors R2 and R3. In this case, the blanking signal ▲
When ▼ becomes high level and the transistor Tr1 is turned on, a constant potential V _A (V _A = Vr) is applied to the connection point A between the resistors R2 and R3.
Set the circuit constants so that −− + 0.7 (v)) occurs. The Vr−− is a lower limit reference voltage and is set to a value slightly higher than the pedestal level of the video signal. The connection point A between the resistors R2 and R3 is connected to the output line 21 via the diode D1. The serial color signal S-RGB from the analog switch circuit 11 is applied to the output line 21 via the capacitor C1. Also, the above capacitors
The connection point between C1 and the diode D1 is connected to the base of the transistor Tr2 and is also grounded via the resistor R4. The transistor Tr2 constitutes a clamp circuit 22 with a diode D2, resistors R5 and R6, and a capacitor C2, the collector is grounded, and the emitter is connected to the Vcc power supply via the resistor R5. The emitter of the transistor Tr2 is connected to the output line 23 via the diode D2 in the forward direction, and the parallel circuit of the capacitor C2 and the resistor R6 is connected between the output line 23 and the ground. Then, the signal output from the output line 21 becomes the video input signal In of the A / D conversion circuit 14, and the signal output from the clamp circuit 22 through the output line 23 is the upper limit reference of the A / D conversion circuit 14. The voltage becomes Vr ++.

Next, the operation of the above embodiment will be described. In FIG. 1, an analog switch circuit 11 time-divisionally, that is, sequentially, color signals R, G, B sent from a video signal processing circuit (not shown) at a preceding stage by sampling clocks CKR, CKG, CKB. Sampling at different timing, after this,
Combined and converted to serial color signal S-RGB, 3rd
Output to the auto level control circuit 12 shown in detail in the figure. As shown in FIG. 4, the auto level control circuit 12 operates in accordance with the blanking signal ▲ ▼ from the blanking signal generating circuit 13 to output the serial color signal S-RG.
The level of B is controlled to create the video input signal In and the upper limit reference voltage Vr ++ for the A / D conversion circuit 14. That is, the serial color signal S-RGB sent from the analog switch circuit 11 to the auto level control circuit 12 passes through the transistor Tr via the capacitor C1 as shown in FIG.
Entered into the base of 2. At this time, if the blanking signal ▲ ▼ sent from the blanking signal generating circuit 13 is at high level, the transistor Tr1 is turned on, and the potential V _A divided by the resistors R2 and R3 is generated at the point _A , Apply forward bias to diode D1. As a result, the capacitor C1 is charged through the diode D1, and the base of the transistor Tr1, that is, the potential at the point D is the potential V _{A at the} point _A.
As a result, the potential becomes Vr --- which is decreased by "0.7 (v)" (voltage drop of the diode D1). In this case, since the diode D1 is interposed between the point D and the point A in the opposite direction, the time constant of the discharge path of the capacitor C1 is sufficiently larger than the charge time constant, and its charge potential is to some extent. For example, it is held for one vertical period. Therefore, one of the serial color signals S-RGB is
The minimum value during the vertical period is the potential at point A as shown in Fig. 4.
It is clamped to the lower limit reference voltage Vr−− that is “0.7 (v)” lower than V _A , that is, “V _A −0.7 (v)”.

Next, the biased serial color signal S-RGB
Is amplified by the transistor Tr2 of the emitter follower in the clamp circuit 22, a voltage of about 0.7 (v) is added, and appears at the emitter, that is, at the point B. Then, the voltage at the point B is held by the diode D2, the capacitor C2, and the resistor R6 on the cathode side of the diode D2, that is, at the point C at the peak voltage in one vertical period. In this case, the diode
Since the voltage drop of D2 is about 0.7 (v), D at the D point and C
The C level is kept at the same value. Then, the potential at the point C becomes the upper limit reference voltage Vr ++ shown in FIG. 4, and is supplied to the A / D conversion circuit 14. That is, the auto level control circuit 12 clamps the minimum value in a certain period of the video signal sent from the video signal processing circuit, for example, one vertical period, to the lower limit reference voltage Vr-- which is slightly above the pedestal level. , Clamp the highest value to the upper reference voltage Vr ++.

Then, the video signal output from the auto level control circuit 12 is sent to the A / D conversion circuit 14 and is A / D converted according to the upper limit reference voltage Vr ++ and the lower limit reference voltage Vr--. The signal A / D converted by the A / D conversion circuit 14 is sent to the multiplexer 15 and separated into R, G, and B primary color signals DR1 to DR4, DG1 to DG4, and DB1 to DB4. Sent to.

In addition, in the above-described embodiment, the case where the present invention is applied to the color liquid crystal television is explained, but the present invention can be applied to a black and white liquid crystal television in the same manner and the same effect can be obtained.

Further, in the above-mentioned embodiment, the clamp period of the minimum value and the maximum value of the video signal is set to be approximately one vertical period, but it is not limited to one vertical period and may be set to other values. Is.

[Effect of the Invention] As described in detail above, according to the present invention, almost the minimum value in a certain period of a video signal is clamped to a preset lower limit reference voltage, and the almost maximum value is set as the peak value in the above period. Since a certain upper limit reference voltage is output to the A / D conversion circuit, the conversion range can be changed in the A / D conversion circuit according to the signal level of the video signal, and the dynamic range of gradation in the liquid crystal display panel is effective. Can be used to obtain a screen with good contrast.

[Brief description of drawings]

The drawings show one embodiment of the present invention. FIG. 1 is a block diagram showing the overall circuit configuration, FIG. 2 is a diagram showing details of the analog switch circuit in FIG. 1, and FIG. 3 is FIG. Figure showing the details of the auto level control circuit in
FIG. 4 is a signal waveform diagram for explaining the automatic level control operation. 11 ... Analog switch circuit, 12 ... Auto level control circuit, 13 ... Blanking signal generation circuit, 14 ...
… A / D conversion circuit, 15 …… Multiplexer, 21,23 …… Output line, 22 …… Clamp circuit.

Claims (1)

[Claims] 1. A switching element which is turned on every set period in synchronism with a timing signal, and an operating voltage is supplied through the switching element, and an almost minimum value of the video signal during the period is A / D converted. And a means for clamping and outputting to a lower limit reference voltage, and a means for detecting an almost maximum value of the video signal during the above period and outputting it as an upper limit reference voltage for A / D conversion. Video signal level control circuit.