JPS62188477A - Level control circuit for video signal - Google Patents

Abstract

PURPOSE:To improve the contrast of a picture by forming a means for detecting a maximum value in a video signal period and outputting the detected value as an upper limit reference voltage for A/D conversion. CONSTITUTION:A biased serial color signal S-RGB is amplified by an emitter follower transistor (TR) 2 in a clamping circuit 22 so that about 0.7V voltage is applied to the signal and the added voltage on a point B is held on a point C on the cathode side of a diode D2 as a peak voltage in one vertical period through a diode D2, a capacitor C2 and a resistor R6. Since the voltage drop of the diode D2 is about 7V, the DC levels of both the points D, C are held at the same value and the potential of the point C is supplied to an A/D converting circuit 14 as an upper limit reference voltage Vr++. A video signal outputted from an auto level control circuit 12 is sent to the A/D converter 14 and A/D converted in accordance with the upper limit reference voltage Vr++ and a lower limit reference voltage Vr--. Consequently, a picture with high contrast can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a level control circuit for a video signal in a liquid crystal television.

[Prior art and its problems] Conventionally, LCD televisions using an LCD panel convert a video signal amplified by a video amplification circuit into a digital signal by an A/'D conversion circuit, and use this digital signal to control the LCD panel. It's like driving a display. In this case, the level of the video signal from bright to dark is displayed in, for example, 16 gradations. However, due to its nature, the liquid crystal display panel has a narrow gradation range from the white level to the black level, making it difficult to obtain images with good contrast.

[Object of the Invention] The present invention has been made in view of the above points, and provides a video signal level control circuit that can effectively utilize the dynamic range of gradations in a liquid crystal display panel and obtain images with good contrast. The purpose is to

[Summary of the Invention] The present invention clamps the lowest value of a video signal during a certain period to a preset lower limit reference voltage, and clamps the highest value to an upper limit reference voltage that is the peak value during the above period. This allows A/D conversion of video signals according to their levels.

[Embodiments of the Invention] The details of the present invention will be described below with reference to the case where it is applied to a color liquid crystal television. First, the overall schematic configuration will be explained with reference to FIG. In FIG. 1, reference numeral 11 denotes an analog switch circuit, into which color signals R, G, and B sent from a previous-stage video signal processing circuit (not shown) are input. The analog switch circuit 11 is composed of three analog switches 118 to 11C, as shown in detail in FIG. 2, and its switching operation is controlled by sampling clocks CKR, CKG, and CKB supplied from a timing generation circuit (not shown). Ru. The analog switch circuit 11 converts the primary color signals R, G, and B into a sampling clock C.
The samples are time-divisionally sampled using KR, CKG%CKB, that is, sequentially at specific timings, and then synthesized and converted into a serial color signal 5-RGB, which is output to an auto-level control circuit 12, the details of which will be described later. Further, 13 is a blanking signal generation circuit 13, which is a horizontal synchronization signal φH sent from a synchronization signal separation circuit (not shown).
A blanking signal BL is generated using the vertical synchronizing signal φV. This blanking signal BL is a signal that is at a high level only during the effective screen and is at a low level during the retrace period, and is sent to the auto level control circuit 12. The auto level control circuit 12 controls the level of the serial color signal 5-RGB according to the blanking signal IBL from the blanking signal generation circuit 13, and controls the level of the serial color signal 5-RGB.
A video input signal jNn and an upper limit reference voltage V r++ for the D variation detection circuit 14 are created. In addition, the A/D conversion circuit 14
, the video signal input signal in and the upper limit reference voltage V r+
Along with 10, a lower limit reference voltage y r- is given.

The A/D conversion circuit 14 sequentially converts the signal from the auto level control circuit 12 into a 4-bit digital signal and outputs it to the multiplexer 15. This multiplexer 15 uses the A/D converted signal by the A/D conversion circuit 14 as sampling clocks CKR, CKG1CK8.
Digital signal DRI for each primary color of R501B in synchronization with
Separated into DR4, DG1-DG4, DB1-084,
Output to a liquid crystal display section (not shown).

Next, details of the auto level control circuit 12 will be explained with reference to FIG. The auto level control circuit 12 includes switching elements such as an NPN transistor Tri, a PNP transistor Tr2,
It is mainly composed of diodes [)1 and ()2. The transistor Tr1 has V at its collector.
cCI! At the same time, the blanking signal BL from the blanking signal generating circuit 13 of FIG. 1 is supplied to the base.
is input via resistor R1. Also, the transistor T
The emitter of r1 is grounded via resistors R2 and R3. In this case, when the blanking signal ■τ becomes high level and the transistor ■r1 turns on, a constant potential VA (VA-Vr-+
Set the circuit constants so that 0.7 (V)) occurs.

The above-mentioned vr- is a lower limit reference voltage, and is set to a value slightly higher than the pedestal level of the video signal. The connection point A between the resistors R2 and R3 is connected to the output line 21 via the diode D1. This output line 21 receives a serial color signal 5- from the analog switch circuit 11.
RGB is provided via capacitor C1. Further, the connection point between the capacitor C1 and the diode D1 is connected to the base of the transistor Tr2 and grounded via a resistor R4. The transistor Tr2 constitutes a clamp circuit 22 with a diode D2, resistors R5 and R6, and a capacitor C2, and its collector is grounded.
The emitter is connected to the vccm source via resistor R5.

The emitter of the transistor Tr2 is connected to the output line 23 via the diode D2 in the forward direction, and a capacitor C2 is connected between the output line 23 and the ground.
and a resistor R6 are connected in parallel. Then, the signal outputted from the output line 21 is transmitted to the A/D conversion circuit 14.
The movie input signal In becomes the movie input signal In, and the signal outputted from the clamp circuit 22 via the output line 23 becomes the upper limit reference voltage Vr+10 of the A/D conversion circuit 14.

Next, the operation of the above embodiment will be explained. In Figure 1 -
The analog switch circuit 11 receives the color signal R1G sent from the previous stage video signal processing circuit (not shown).
, B are time-divisionally sampled using sampling clocks CKR1CKG and CKB, that is, sequentially at specific timings, and then synthesized to produce a serial color signal 5-
The signal is converted into RGB and output to the auto level control circuit 12 whose details are shown in FIG. The auto level control circuit 12 controls the level of the serial color signal 5-RGB according to the blanking signal πT from the blanking signal generation circuit 13, as shown in FIG.
A video input signal in and an upper limit reference voltage V r++ for the conversion circuit 14 are created. That is, the serial color signal 5-RGB sent from the analog switch circuit 11 to the auto level control circuit 12 is input to the base of the transistor Tr2 via the capacitor C1 as shown in FIG.

At this time, when the blanking signal sent from the blanking signal generation circuit 13 is at a high level, the transistor Tr1 is turned on, and a potential VA divided by the resistors R2 and R3 is generated at the point A, and the diode D1 As a result, the capacitor C1 is charged through the diode D1, and the base of the transistor Tr1, that is, the potential at point D becomes 10.0% lower than the potential VA at point A.
V decreased by 7(v)J (voltage drop of diode D1)
The potential becomes r-. In this case, between point D and point A,
Since the diode D1 is interposed in the opposite direction, the time constant of the discharging path of the capacitor C1 is sufficiently large compared to the charging time constant, so that its charging potential is maintained to some extent, for example for one vertical period. Therefore, serial color signal 5-1 of RGB
The minimum value during the vertical period is the lower limit reference voltage vr, which is ro, 7 (V) J lower than the potential VA at point A, as shown in Figure 4.
, -1, that is, rVx-0,7(v)J.

Next, the biased serial color signal 5-RG
B is amplified by the emitter follower transistor Tr2 in the clamp circuit 22, and a voltage of approximately 0.7 (V) is added to the emitter, which appears at the B point. Then, the voltage at point B is applied to diode D2, capacitor C2,
The peak voltage in one vertical period is held at the cathode side of the diode D2, that is, at the 0 point, by the resistor R6. In this case, the voltage drop across diode D2 is approximately 0.7 (Vl), so the DC levels at point D and point 0 are held at the same value.The potential at point 0 is the upper limit reference shown in Figure 4. The voltage becomes r+10 and is supplied to the A/D conversion circuit 14.

That is, the auto level control circuit 12 has the following functions:
The lowest value in a certain period of the video signal sent from the video signal processing circuit, for example, one vertical period, is clamped to the lower limit reference voltage Vr-, which is slightly higher than the pedestal level, and the highest value is clamped to the upper limit reference voltage Vr+10. Clamp on.

The video signal output from the auto level control circuit 12 is sent to the A/D conversion circuit 14, where it is A/D converted according to the upper limit reference voltage (r+10) and the lower limit reference voltage vr-1. And the above A/D conversion circuit 1
The signal A/D converted in step 4 is sent to the multiplexer 15, and the primary colors of RlG and B @ D R1 to DR are sent to the multiplexer 15.
4, separated into DG1 to DG4 and DB1 to DB4 and sent to the display section.

In the above embodiment, a case where the present invention is applied to a color liquid crystal television has been described, but the present invention can be similarly applied to a black and white liquid crystal television, and similar effects can be obtained.

Further, in the above embodiment, the clamp period for the lowest value and the highest value of the video signal is set to approximately one vertical period, but it is not limited to one vertical period, and it goes without saying that it may be set to other values. It is.

[Effects of the Invention] As described in detail above, according to the present invention, the lowest value of a video signal during a certain set period is clamped to the lower limit reference voltage yr-, and the highest value is clamped to the upper limit which is the peak value during that period. Reference voltage■
Since r→10 is clamped and output to the A/D conversion circuit, the conversion range can be varied in the A/D conversion circuit according to the signal level of the video signal, and the dynamic range of gradation on the liquid crystal display panel can be changed. You can use this effectively to get a screen with good contrast.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing the overall circuit configuration, FIG. 2 is a diagram showing details of the analog switch circuit in FIG. 1, and FIG. 3 is a diagram showing the details of the analog switch circuit in FIG. 1. FIG. 4 is a signal waveform diagram for explaining the auto level control operation. DESCRIPTION OF SYMBOLS 11... Analog switch circuit, 12... Auto level control circuit, 13... Blanking signal generation circuit, 14... A/D'& conversion circuit, 15... Multiplexer, 21.23...・Output line, 22...
clamp circuit. Applicant's agent Patent attorney Suzue Takehiko CKRCKG
CKB Figure 2 Figure 3

Claims (1)

[Claims] A switching element is turned on every set period in synchronization with a timing signal, and an operating voltage is supplied through this switching element, and the lowest value of the video signal during the above period is set to A/
It is characterized by comprising means for clamping and outputting the lower limit reference voltage for D conversion, and means for detecting the highest value of the video signal during the above period and outputting it as the upper limit reference voltage for A/D conversion. Level control circuit for video signals.