JPH0326957B2 - - Google Patents
Info
- Publication number
- JPH0326957B2 JPH0326957B2 JP2752184A JP2752184A JPH0326957B2 JP H0326957 B2 JPH0326957 B2 JP H0326957B2 JP 2752184 A JP2752184 A JP 2752184A JP 2752184 A JP2752184 A JP 2752184A JP H0326957 B2 JPH0326957 B2 JP H0326957B2
- Authority
- JP
- Japan
- Prior art keywords
- color difference
- converter
- signal
- image
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Processing Of Color Television Signals (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、受信中のテレビジヨン画像の一部に
他の番組の画像を挿入して表示するテレビジヨン
受像機に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television receiver that inserts and displays images of other programs into a portion of the television image that is being received.
従来例の構成とその問題点
近年、親画像の一部に子画像を挿入して表示す
るいわゆる多画面テレビジヨンが発表されてい
る。まず、この方式のテレビジヨンの原理を以下
に示す。Configuration of Conventional Example and its Problems In recent years, so-called multi-screen televisions have been announced in which a child image is inserted into a part of a parent image and displayed. First, the principle of this type of television will be explained below.
第１図はその多画面テレビジヨンの画像の概念
図であり、Ａはテレビジヨン受像機、Ｂは親画
像、Ｃは他のテレビ画面を縮小して挿入した子画
像である。 FIG. 1 is a conceptual diagram of an image of the multi-screen television, where A is a television receiver, B is a parent image, and C is a child image into which another television screen is reduced and inserted.
第２図は従来例の多画面テレビの構成を示すブ
ロツク図である。図中、１はアンテナ、１１及び
２１，１２及び２２はそれぞれ親画像用及び子画
像用のチユーナ選局回路とVIF映像検波回路であ
る。映像信号処理回路２３で処理された子画像用
信号は、同期分離回路２４で子画像用に同期分離
された同期信号によつてタイミング同期された書
込クロツクでメモリ２５に記憶される。メモリ２
５に書込まれた映像信号は、同期分離回路１４の
親画像用に同期分離された同期信号につてタイミ
ング同期された読出しクロツクで読出され、子画
像挿入回路３１により親画像用の映像信号と合成
されてCRT３２に加えられ、これを駆動する。
これにより、画面上には第１図のように親画像の
一部に子画像が挿入されて映出される。なお１３
は親画像用の映像信号処理回路である。 FIG. 2 is a block diagram showing the configuration of a conventional multi-screen television. In the figure, 1 is an antenna, 11 and 21, 12 and 22 are tuner selection circuits and VIF video detection circuits for parent images and child images, respectively. The child image signal processed by the video signal processing circuit 23 is stored in the memory 25 with a write clock whose timing is synchronized with the synchronization signal which is synchronously separated for the child image by the synchronization separation circuit 24. memory 2
The video signal written in 5 is read out by a readout clock whose timing is synchronized with the synchronization signal separated in synchronization for the parent image by the synchronization separation circuit 14, and is read out by the readout clock synchronized with the synchronization signal for the parent image by the child image insertion circuit 31. It is synthesized and added to the CRT 32 to drive it.
As a result, the child image is inserted into a part of the parent image and displayed on the screen as shown in FIG. Note 13
is a video signal processing circuit for the parent image.
第３図に第２図の点線で囲んだ部分の詳細を示
す。 FIG. 3 shows details of the portion surrounded by dotted lines in FIG. 2.
子画像用の映像信号処理回路２３で得られた
Ｙ，Ｒ−Ｙ，Ｂ−Ｙの各信号はマルチプレツクス
４３で時系列化され、Ａ／Ｄ変換器４４に供給さ
れる。時系列化されＡ／Ｄ変換された３つの信号
はデジタル信号処理回路４５で再び同時化され、
Ｄ／Ａ変換器４７で時間圧縮されたＹ，Ｂ−Ｙ，
Ｂ−Ｙの各信号が得られる。４５はデイジタル信
号処理回路、４６はメモリである。４１，４２
は、Ｙ，Ｒ−Ｙ，Ｂ−Ｙ各信号のDCレベルシフ
ト回路である。 The Y, RY, and BY signals obtained by the child image video signal processing circuit 23 are time-seriesized by a multiplex 43 and supplied to an A/D converter 44. The three time-series and A/D-converted signals are again synchronized by the digital signal processing circuit 45.
Y, B-Y, time-compressed by the D/A converter 47
Each signal of B-Y is obtained. 45 is a digital signal processing circuit, and 46 is a memory. 41, 42
is a DC level shift circuit for Y, RY, and BY signals.
子画像用の信号をデイジタル化する方法は種々
提案されていが、Ａ／Ｄ変換器はコストの高いも
のであり、上記の様にＹ，Ｒ−Ｙ，Ｂ−Ｙ信号を
時系列化すれば一個のＡ／Ｄ変換器を用いるだけ
で容易に２画面画像が得られる。 Various methods have been proposed to digitize signals for child images, but A/D converters are expensive, and if the Y, R-Y, B-Y signals are digitized as described above, Two-screen images can be easily obtained by using one A/D converter.
この場合、方式の異なるＹと色差信号（Ｒ−Ｙ
及びＢ−Ｙ）を１個のＡ／Ｄ変換器で処理するた
めに、従来には、DCレベルシフト回路が必要で
あつた。第７図にその波形例を示す。Ｙ信号は電
圧VLを基準に負方向へ変化するが、色差信号は
あるレベルを基準に正負に変化する。いま、電圧
VLとVHの間がＡ／Ｄの入力ダイナミツクレンジ
であり、Ｙ信号は、ペデスタルレベル又は、黒レ
ベルをVLに、また色差信号はVL＋VH／２である電
圧Vrefにその基準を合わせるのが、理想的なＡ／
Ｄ変換器の使い方である。この場合、明らかに、
Ｙ信号と色差信号で独立のDCDCレベルシフト回
路（第３図の４１，４２）が必要である。 In this case, Y and color difference signals (R-Y
and B-Y) with one A/D converter, conventionally, a DC level shift circuit was required. FIG. 7 shows an example of the waveform. The Y signal changes in the negative direction with reference to the voltage V L , but the color difference signal changes in the positive and negative directions with a certain level as the reference. Now the voltage
The input dynamic range of the A/D is between V L and V H , and the Y signal is set to the pedestal level or black level to V L , and the color difference signal is set to the voltage V ref , which is V L + V H /2. The ideal A/
This is how to use the D converter. In this case, obviously
Independent DCDC level shift circuits (41 and 42 in FIG. 3) are required for the Y signal and color difference signal.
近年の２画面テレビは、メモリ効率を高めた方
式、つまり、メモリに信号期間（第４図のtSIG）
のみを記憶する方式である。このため、色差信号
の基準が、Ａ／Ｄ変換用の基準電圧VL，VH及び
DCレベルシフト回路の調整誤差や温度等の要因
によるずれを生じ、子画像のホワイトバランスを
大きく劣化させる問題点があつた。６ビツトの
Ａ／Ｄ変換器の場合を考えると、仮にＡ／Ｄ変換
入力のダイナミツクレンジでは
１／2LSB＝2V／26×１／２≒15.6mV
の範囲内に、誤差やバラツキ等による変動等を抑
えなければならないという欠点があつた。 Recent two-screen TVs use a system that increases memory efficiency, that is, the signal period (t SIG in Figure 4) is stored in the memory.
This method stores only the Therefore, the color difference signal standards are the A/D conversion reference voltages V L , V H and
There was a problem in that deviations occurred due to adjustment errors in the DC level shift circuit and factors such as temperature, which significantly degraded the white balance of the child image. Considering the case of a 6-bit A/D converter, if the dynamic range of the A/D conversion input is within the range of 1/2 LSB = 2 V/2 6 × 1/2 ≒ 15.6 mV, due to errors and variations, etc. The drawback was that fluctuations, etc. had to be suppressed.
発明の目的
本発明は、上記の欠点を除去し、Ａ／Ｄ変換入
力の色差信号の直流レベルの調整が不要な２画面
方式のテレビジヨン受像機を提供することを目的
とする。OBJECTS OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a two-screen television receiver that does not require adjustment of the DC level of the color difference signal of the A/D conversion input.
発明の構成
本発明においては、子画像用のＡ／Ｄ変換器の
基準電圧のセンター電圧で入力の色差信号（Ｒ−
Ｙ，Ｂ−Ｙ）をブランキング期間にそれぞれクラ
ンプすように構成することにより、Ａ／Ｄ変換入
力の調整を減らし、尚かつ子画像の映像品質を容
易に向上することができるものである。Structure of the Invention In the present invention, the input color difference signal (R-
By configuring the image forming apparatus to clamp the images (Y, B-Y) respectively during the blanking period, it is possible to reduce the adjustment of the A/D conversion input and easily improve the video quality of the child image.
実施例の説明
第５図に本発明の一実施例の構成図を示す。
Ａ／Ｄ変換器４４より基準電圧VL，VHのセンタ
ー電圧Vrefを色差信号（Ｒ−Ｙ，Ｂ−Ｙ）用クラ
ンプ回路に加え、色差信号の基準を常にＡ／Ｄダ
イナミツクレンジのセンターにクランプするよう
にしている。DESCRIPTION OF THE EMBODIMENT FIG. 5 shows a configuration diagram of an embodiment of the present invention.
The center voltage V ref of the reference voltages V L and V H is added from the A/D converter 44 to the clamp circuit for color difference signals (RY, B-Y), and the reference voltage of the color difference signal is always set to the A/D dynamic range. I try to clamp it in the center.
すなわち、第６図に具体構成を示すように、２
３は子画像用の映像信号処理回路であり、エミツ
ターホロワートランジスター６１のベースにはそ
れぞれＲ−Ｙ，Ｂ−Ｙの色差信号が入力される。
コンデンサ６３はクランプ用のものであり、信号
のないブランキング期間内のみ正方向のクランプ
パルスにより抵抗６４を介してスイツチング用ト
ランジスター６５をオンさせ、それぞれの電圧を
保持する。クランプされた色差信号Ｒ−Ｙ，Ｂ−
Ｙはそれぞれマルチプレクサ４３の端子C1，C2
に、又、Ｙ信号は端子C3に供給している。マル
チプレクサ４３で時系列化した信号出力C4は
Ａ／Ｄ変換器４４の入力に接続されている。Ａ／
Ｄ変換器４４より、基準電圧VL，VHのセンター
電圧Vrefが色差信号のクランプ基準電圧としてト
ランジスタ６８を介してトランジスタ６５，６
５′のエミツターに供給されている。抵抗６２，
６２′，６４，６４′，６６，６６′，６９，６７，
６７′はそれぞれトランジスタ６１，６１′のエミ
ツター抵抗およびトランジスタである。６３，６
３′はコンデンサである。 That is, as shown in FIG. 6, the 2
Reference numeral 3 designates a video signal processing circuit for a child image, and color difference signals of R-Y and B-Y are inputted to the base of an emitter follower transistor 61, respectively.
The capacitor 63 is for clamping, and a positive clamp pulse turns on the switching transistor 65 via the resistor 64 only during a blanking period in which there is no signal, thereby holding the respective voltages. Clamped color difference signal R-Y, B-
Y are terminals C 1 and C 2 of multiplexer 43, respectively.
Additionally, the Y signal is supplied to terminal C3 . The signal output C 4 converted into a time series by the multiplexer 43 is connected to the input of the A/D converter 44 . A/
The D converter 44 outputs the center voltage V ref of the reference voltages V L and V H to the transistors 65 and 6 via the transistor 68 as a clamp reference voltage for the color difference signal.
5' emitter. resistance 62,
62', 64, 64', 66, 66', 69, 67,
67' are the emitter resistors and transistors of the transistors 61 and 61', respectively. 63,6
3' is a capacitor.
尚、トランジスタ６６と６８は、PNPとNPN
のものを使用して温度保償している。 Note that the transistors 66 and 68 are PNP and NPN.
The temperature is guaranteed using the following.
発明の効果
以上のように、本発明によればＡ／Ｄに供給さ
れている基準電圧のセンター電圧で色差信号をク
ランプすることにより、
従来必要であつた色差信号のDCレベル調整
が２箇所不要にでき、
電源電圧Ａ／Ｄ変換器に供給する基準電圧等
が変化しても、常にＡ／Ｄ変換器のダイナミツ
クレンジの最大が使え、
容易な回路で実現できる等の利点がある。Effects of the Invention As described above, according to the present invention, by clamping the color difference signal at the center voltage of the reference voltage supplied to the A/D, there is no need to adjust the DC level of the color difference signal at two locations, which was conventionally necessary. It has the advantage that even if the reference voltage supplied to the power supply voltage A/D converter changes, the maximum dynamic range of the A/D converter can always be used, and it can be realized with a simple circuit.
そして以上を総合して子画像のホワイトバラン
スが安定し、２画面テレビの映像品質が向上する
ものである。 By combining the above, the white balance of the child image is stabilized, and the video quality of the two-screen TV is improved.
第１図は従来例のテレビジヨン受像機の画面の
概略正面図、第２図は従来例のテレビジヨン受像
機の構成図を示すブロツク図、第３図は第２図中
の点線内の部分の詳細な構成を示すブロツク図、
第４図はその動作説明用の波形図、第５図は本発
明の一実施例におけるテレビジヨン受像機の構成
を示すブロツク図、第６図は同受像機の要部の一
具体例の回路である。
１……アンテナ、１１……チユーナ選局回路、
１２……VIF・映像検波回路、１３……映像信号
処理回路、３１……子画像挿入回路、３２……
CRT、４３……マルチプレクサ、４４……Ａ／
Ｄ変換器、４７……Ｄ／Ａ変換器。
Fig. 1 is a schematic front view of the screen of a conventional television receiver, Fig. 2 is a block diagram showing the configuration of a conventional television receiver, and Fig. 3 is the portion within the dotted line in Fig. 2. A block diagram showing the detailed configuration of
FIG. 4 is a waveform diagram for explaining its operation, FIG. 5 is a block diagram showing the configuration of a television receiver according to an embodiment of the present invention, and FIG. 6 is a circuit diagram of a specific example of the main part of the same receiver. It is. 1...Antenna, 11...Tuner tuning circuit,
12... VIF/video detection circuit, 13... video signal processing circuit, 31... child image insertion circuit, 32...
CRT, 43...Multiplexer, 44...A/
D converter, 47...D/A converter.
Claims (1)
け、上記Ａ／Ｄ変換器に供給する第１、第２の色
差信号をクランプするクランプ回路を設け、前記
Ａ／Ｄ変換器に供給する基準電圧のセンター電圧
に前記第１、第２の色差信号をそれぞれクランプ
するようにしたことを特徴とするテレビジヨン受
像機。1. An A/D converter for A/D converting the color difference signal is provided, and a clamp circuit is provided for clamping the first and second color difference signals supplied to the A/D converter, and the clamp circuit is provided for supplying the first and second color difference signals to the A/D converter. A television receiver characterized in that the first and second color difference signals are each clamped to a center voltage of a reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2752184A JPS60171889A (en) | 1984-02-16 | 1984-02-16 | Television receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2752184A JPS60171889A (en) | 1984-02-16 | 1984-02-16 | Television receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60171889A JPS60171889A (en) | 1985-09-05 |
| JPH0326957B2 true JPH0326957B2 (en) | 1991-04-12 |
Family
ID=12223426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2752184A Granted JPS60171889A (en) | 1984-02-16 | 1984-02-16 | Television receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60171889A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1289314A3 (en) * | 2001-08-31 | 2003-05-02 | Thomson Licensing S.A. | Color difference signal processing |
| US6967691B2 (en) | 2002-08-07 | 2005-11-22 | Thomson Licensing | Color difference signal processing |
-
1984
- 1984-02-16 JP JP2752184A patent/JPS60171889A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60171889A (en) | 1985-09-05 |
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