JPS62254572A - Scanning signal generating circuit - Google Patents

Abstract

PURPOSE:To simply change the peak value of a scanning signal without increasing a mounting space and cost by shifting the digit of a count value inputted to a digital analog converting means by a selecting means. CONSTITUTION:When the value of a select signal 600 inputted to a select circuit 3 is defined to be '1' and a bias signal 500 to be '0', the highest order bit of a D/A converter circuit 4 is fixed to '0' and the count value of 7 bits outputted from a count circuit 1 is inputted to remaining 7 bits. Thereby, the peak value of the outputted scanning signal goes to V/2. When the select signal 600 remains '1' and the bias signal 500 is defined to be '1', the respective areas obtained by dividing a scanning screen 41 into four can be scanned by the combination of the bias signal 500 of respective scanning signals 700 scanning horizontally and vertically.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a scanning signal generation circuit that generates a scanning signal used, for example, to display a video signal on a monitor screen.

(Prior Art) Conventionally, a scanning signal generation circuit that generates a sawtooth scanning signal used in whistles to display video signals on a monitor screen is a mirror integration circuit as shown in FIG. 5(B). It was occurring. That is, the Miller integration circuit is composed of a resistor R, a capacitor C, and an amplifier 51, and the input terminal is connected to the input terminal shown in FIG.
When the input signal 100 shown by is input, the fifth
A sawtooth scanning signal 200 as shown in Figure (C) is output.

Here, if the peak value of the scanning signal @200 is ■, the period is XX, and the peak value of the input signal is ■, then T = (CXVxR)/v
There is a relationship between

Here, in order to scan an arbitrary window on the monitor screen, the peak value V (sometimes referred to as level) of the scanning signal 200 must be changed. In such a case, the peak value V of the scanning signal must be changed using the mirror integration circuit. However, V= (T-v),'(C-
R), and normally T and V are constant, so in order to change the peak value V of the scanning signal, it is necessary to change the time constant of the Miller integration circuit, that is, change the values of the resistor R and capacitor C. Must be. Changing the time constant of the Miller integration circuit as described above has the drawback of poor operability due to mechanical movement, and it also requires the use of multiple resistors and capacitors in order to change the peak value V of the scanning signal over multiple stages. This has disadvantages in that the required circuit scale increases, and the mounting space and cost increase.

(Problems to be Solved by the Invention) In the above-mentioned conventional scanning signal generation circuit using a mirror integration circuit, operability is poor in changing the peak value of the generated scanning signal, and the peak value is changed in multiple stages. had the disadvantage of increasing mounting space and cost. SUMMARY OF THE INVENTION Therefore, the present invention aims to eliminate the above-mentioned drawbacks, and provides a scanning signal generation circuit that can easily change the peak value of a scanning signal without increasing mounting space or cost. be.

[Structure of the Invention] (Means for Solving the Problems) The scanning signal generation circuit of the present invention includes a counting means that repeats a counting operation up to one predetermined shift, and converting the count value output from the counting means into an analog signal. digital-to-analog conversion means for inputting the count value to the digital-to-analog conversion means; and selection means for changing the bit range used by the digital-to-analog conversion means to shift the digit of the count value input to the conversion means. configured.

(Function) In the scanning signal generation circuit of the present invention, when converting a digital signal into an analog signal, focusing on the fact that the peak value of the analog signal depends on the maximum value of the digital signal to be converted, By shifting the digit of the count value input to the conversion means, it is possible to convert the peak value (level) of the sawtooth scanning signal obtained by analog conversion of the count value.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of the scanning signal generating circuit of the present invention. 1 is a count circuit that repeatedly counts down from a predetermined value to zero; 2 is a timing generation circuit that generates a count start timing signal 400 for count circuit 1; and 3 is a selector that controls the scanning signal 7 (>O peak value and resolution). A circuit 4 converts the count value supplied from the select circuit 3 into an analog signal and generates a scanning signal 700.
This is a D/A conversion circuit that outputs.

FIG. 2 is a block diagram showing a detailed configuration example of the select circuit 3 shown in FIG. 1. The select circuit 3 consists of eight selectors 31 to 38, and each selector receives a select signal 6.
When 00 is "Ole", the signal input to terminal O is selected and output, and when the select signal 600 is "'1", each selector selects and output the signal input to terminal 1.
A bias signal 500 of 1 is input to the terminal 1 of the selector 38, and the most significant bit D6 of the count value output from the count circuit 1 is input to the terminal O of the selector 38. Terminal O of selector 31
The D1 signal is always applied to the terminal 1, and the least significant bit D of the count value is output from the count circuit 1 to the terminal 1.

is input. The count value of the count circuit 1 is input to terminals 1 and 0 of the selectors 37-32. Also, the signal FO-F7 selected by the selectors 31 to 38
are input from the least significant bit DO to the most significant bit D7 of the 8-bit D/A conversion circuit 4.

Next, the operation of this embodiment will be explained. When the count start signal 400 is output from the timing generation circuit 2 to the count circuit 1, the count circuit 1 receives the input clock 3.
Start counting down in synchronization with 00. The count value 50 output from the count circuit 1 is inputted to a predetermined input terminal (same as a predetermined bit range) of the D/A converter circuit 4 by the select circuit 3, so that the count value 50 is output from the D/A converter circuit 4 to a predetermined value. For example, a sawtooth scanning signal 700 as shown in FIG. 3 having a peak value V is output. The period T of this scanning signal is determined by multiplying the period t1 of the clock 300 input to the count circuit 1 by the count number n counted by the count circuit 1 (directly (ntl). When the count is completed by counting up to O, it outputs a count end signal 4aOO to the timing generation circuit 2. As a result, the timing generation circuit 2 outputs the count start signal 400 to the count circuit 1 again and sets the count circuit 1 again. Count down from the value.

Through such repeated operations of the count circuit 1, a scanning signal 700 as shown in FIG. 3 is output.

Next, the detailed operation of the select circuit 3 will be explained with reference to FIG. First, when the select signal @600 input to the select circuit 3 is "01?", the most significant bit D6 of the count value output from the count circuit 1 is output to the selector 3.
8 and is input to the most significant bit input terminal D7 of the D/A conversion circuit 4. The same goes for the above count values D5 and Dl.

... Each bit of Do is selected by selector 37, 36 . ...3
1 to the input terminals D6 and D5 of the D/A conversion circuit 4.
,...

It is input to Dl. At this time, the selector 31 selects "1" inputted to the terminal O and outputs it to the input terminal DO of the least significant bit of the D/A conversion circuit 4.

As a result, the 7-bit count value from the count circuit 1 is input to the 7 bits from the most significant bit to the bit next to the least significant bit of the 8-bit D/A conversion circuit 4. This input count value (digital value) is converted into an analog signal by the D/A conversion circuit 4, and a scanning signal 700 having a peak value V and a period T as shown in FIG. 3 is output. Next, the value of the select signal 600 is set to "1", and the bias signal 500 is set to "0".
11, the selectors 31 to 38 select and output the signal input to the terminal 1. Therefore, the most significant bit D6 of the count value output from the count circuit 1 is F
The count value D4 becomes F5 and is input to the input terminal D6 of the bit next to the most significant bit D7 of the D/A conversion circuit 4, and the count value D4 becomes F5 and is input to the input terminal D5 of the D/A conversion circuit 4. Similarly, the least significant bit DO of the same count value is FO
Then, the least significant bit input terminal DO of the D/A conversion circuit 4
is input.

Therefore, in this case, the most significant bit of the D/A conversion circuit 4 is fixed at "O'°, and the remaining 7 bits are set to the count circuit 1.
The 7-bit count value output from the 7-bit count value is input. Therefore, the count value input to the 8-bit D/A modification circuit 4 is the remaining bits excluding the most significant bit, so when this is converted into analog, the peak value of the output scanning signal is V /2. Note that even if the peak value changes, the period T of the scanning signal 700 remains the same.

Here, when the select signal 600 is set to "09m", the peak value of the scanning signal 700 outputted is v as shown in FIG.
can be scanned across the entire horizontal and vertical directions. Next, when the select signal 600 is set to "1" and the bias signal 500 is set to "Otp," the scanning signal 7 is output.
00 has a peak value of V/2 as shown in FIG. 4(B). Therefore, when scanning in the horizontal and vertical directions using such a scanning signal 700, only an area P obtained by dividing the scanning screen 41 into four parts can be scanned as shown in FIG. 4(B).

Also, if the select signal @600 remains 1'' and the bias signal 500 is set to 1'', the peak value V/
If the horizontal scanning signal 700 of No. 2 is shifted horizontally as it is and the vertical scanning signal 700 is left unchanged, the area Q of the scanning screen 41 can be scanned. Similarly, by combining the bias signals 500 of the respective scanning signals 700 for scanning in the horizontal and vertical directions (in this case, there are four types), the scanning screen 41 is
Each of the divided @ areas of P, Q, R, and S can be scanned. Note that when the entire surface of the scanning screen 41 is scanned as shown in FIG. When 174 areas of the scanning screen 41 are scanned as shown in B), the D/A conversion circuit 4 operates at 8 bits, so its resolution is 28=256, which is twice the resolution when scanning the entire scanning screen 41. Since one screen to be scanned is scanned in proportion to the absolute value of the scanning signal voltage, this means that when converting to one screen, when scanning an area of 1/4, it is equivalent to scanning the entire surface. Since scanning is performed with a peak value that is 1/2 of the signal peak value, the resolution is twice that of the signal peak value.

According to this embodiment, the peak value of the scanning signal 700 can be easily changed by simply changing the select signal 600 input to the select circuit 3, and the period of the signal 700 can be changed by inputting the select signal 600 to the count circuit 1. This can be easily changed by simply changing the cycle of the clock 300. Similarly, by changing the bias signal 500, the scanning position on the scanning screen 41 by the scanning signal 700 can be easily changed, so that arbitrary window scanning can be easily performed. Furthermore, by changing the processing bits of the count circuit 1 and the D/A conversion circuit 4, the resolution of the scanning screen can be set to an arbitrary value, and in this example, the resolution of the scanning screen can be set to an arbitrary value. By using the D/A conversion circuit 4 of
The resolution can be improved when the peak value of 00 is lowered. Further, since the above-mentioned effects can be achieved with a simple circuit configuration, both cost and mounting space can be reduced compared to the case where a conventional Miller integrating circuit or the like is used.

In addition, in the above embodiment, the case was described in which the level of the scanning signal was half that when scanning the entire screen, but D/
By further shifting the count value from the count circuit 1 input to the A conversion circuit 4 to the lower bit side, the peak value of the scanning signal 700 can be reduced by that amount, and an even smaller area on the scanning screen divided into four or more can be reduced. Scanning can also be easily performed.

[Effects of the Invention] As described above, according to the scanning signal generation circuit of the present invention,
By generating the scanning signal by digital-to-analog conversion of the count value of a counter and by changing the bits used when converting the count value from D/A, the waveform of the scanning signal can be generated without increasing the mounting space and cost. It has the effect of easily changing the high price.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the scanning signal generation circuit of the present invention, FIG. 2 is a block diagram showing a detailed configuration example of the select circuit shown in FIG. 1, and FIG. 3 is the same as that shown in FIG. Figure 4 shows an example of the scanning signal waveform output from the circuit in Figure 1.
A diagram showing an example of a screen area scanned by a scanning signal generated by the circuit shown in the figure, and FIG. 5 is a diagram showing an example of a conventional scanning signal generation circuit and signal waveforms input/output to this circuit. be. 1... Count circuit 3... Select circuit 4.
...D/A conversion circuit 31-38...Selector agent Patent attorney Book 1) Takashi Figure 1 Figure 2

Claims (1)

[Claims] a counting means that repeats a counting operation up to a predetermined value;
digital-to-analog converting means for converting the count value outputted from the counting means into an analog signal; and a bit range used by the digital-to-analog converting means when inputting the count value to the digital-to-analog converting means and inputting the same to the converting means. 1. A scanning signal generation circuit comprising: selection means for shifting the digit of a counted value.