JPH02280482A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To output a black level with a simple circuit and to prevent the deterioration in the characteristic of a video signal by connecting a resistance means between an output terminal of a picture memory and a reference level or a power supply and providing a D/A conversion circuit. CONSTITUTION:A picture memory 17 stores a video signal for a picture period, the video signal is outputted for a prescribed period corresponding to a prescribed area of a screen and a video signal for a picture period is displayed on a prescribed area on the screen. On the other hand, an output terminal of the picture memory 17 reaches a high impedance for a period other than a prescribed period and a digital signal with a value depending on resistors R4-R7 connected between the output terminal of the picture memory 17 and a reference level or a power supply is inputted to a D/A converter 19. Thus, a digital signal representing, e.g. a black level is given to the D/A converter 19 and a video signal for non-picture period not stored in the picture memory 17 is supplemented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing circuit, and particularly to a video signal processing circuit suitable for an electronic endoscope.

[Prior art and problems to be solved by the invention] Conventionally, in display devices, etc., video signals are converted into digital data and stored in an image memory, and screen data is read from this image memory and converted to an analog video signal. By doing so, there are devices that have made it possible to perform various types of image processing, such as displaying still images. In this case, in order to reduce the memory capacity of the image memory, video signals during blanking periods and the like are removed and only video signals during image periods are stored in the image memory. By the way, in electronic endoscope devices, it is necessary to reduce the diameter of the insertion section of the endoscope, so it is not possible to increase the resolution of an image sensor such as a COD provided at the distal end of the insertion section. Therefore, the image inside the body cavity is displayed without using the entire display screen.
I am trying to display it only in a part of it. Therefore, as described above, by not storing video signals of non-image areas in the image memory, the effect of saving memory capacity is extremely high.

FIG. 5 is a block diagram showing such a conventional video signal processing circuit.

The video signal is converted into a digital signal, and as mentioned above, only the signal of the image period is stored in the image memory 1. The video signal from the image memory 1 is input to the D/A conversion circuit 2, where it is converted into an analog video signal, and is applied to the terminal a of the analog switch 3. On the other hand, a predetermined reference voltage is applied to a terminal of the switch 3 from a power source 4.

The switch 3 is configured to select terminals a and b by receiving a switching signal such as a retrace pulse, for example. In other words, switch 3 is used to control the image during the scanning period! During the & period, the video signal from the D/A conversion circuit 2 is outputted from the common terminal C, and during a non-image period such as a retrace period, a predetermined reference voltage is outputted from the common terminal C.

The output from the switch 3 is output to the output terminal 6 via the output buffer 7 circuit 5. Note that normally, the reference voltage of the source 4 is set to the black level.

In this manner, by outputting the reference voltage during the non-image period such as the retrace period, data of the non-image period that is not stored in the image memory 1 is complemented. However, since the analog switch 3 switches between the analog video signal and the reference voltage, the frequency characteristics and S/N ratio of the video signal deteriorate. Further, there is also a problem in that spike-like noise is heavily added to the video signal during the switching operation of the analog switch 3.

Therefore, a method of switching between the video signal and the reference voltage using digital processing is sometimes adopted.

FIG. 6 is a block diagram showing such a conventional video signal processing circuit.

A digital video signal of the image period is output from the image memory 1 to the multiplexer 7. The multiplexer 7 is operated by being supplied with an operating voltage of 5.times. from the power supply terminal 8.

When the switching signal from the switching signal input terminal 9 indicates that it is a non-image period, the multiplexer 7 outputs a digital signal indicating the black level, and when it indicates that it is an image period, the multiplexer 7 outputs a digital signal indicating the black level. , a digital video signal from the image memory 1 is output. The signal from the multiplexer 7 is applied to the D/A conversion circuit 2, converted into an analog signal, and outputted to the output terminal 6 via the output buffer circuit 5.

With this configuration, since digital processing is performed during switching, the frequency characteristics, S/N ratio, etc. do not deteriorate. However, since the multiplexer 7 is used to switch the output between the image period and the non-image period, there is a problem in that the circuit becomes complicated.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a video signal processing circuit that can be configured with a simple circuit and can prevent the characteristics of a video signal from deteriorating.

[Means for Solving the Problems] A video signal processing circuit according to the present invention includes a control signal output circuit that outputs a control signal for a predetermined period corresponding to a predetermined area of a screen, and a digital video signal for an image period. an image memory that sequentially outputs the stored data based on the control signal or puts an output terminal in a high impedance state; and a resistor connected between the output terminal of the image memory and a reference potential point or a power source. is connected to the output terminal of the image memory, inputs data stored in the image memory during the predetermined period, and inputs data indicating a predetermined level during a period when the output terminal of the image memory is in a high impedance state. D/A that converts the data into an analog signal and outputs it.
It is equipped with a conversion circuit.

[Operation] In the present invention, a video signal for an image period is stored in the image memory, and this video signal is output for a predetermined period corresponding to a predetermined area of the screen. As a result, the video of the image period is displayed in a predetermined area on the screen. On the other hand, during periods other than the predetermined period, the output end of the image memory is in a high impedance state, and the D/A conversion circuit has a value determined by the resistor connected between the output end of the image memory and the reference potential point or power source. A digital signal is input. Therefore, this +
For example, a digital signal indicating the black level is connected between D/A
It can be supplied to the conversion circuit, and it is possible to complement images of non-image periods that are not stored in the image memory.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a video signal processing circuit according to a first embodiment of the present invention, and FIG. 2 is a circuit diagram showing an image memory 17.
2 is a block diagram showing a 611111 signal output circuit 18 that outputs a control signal to be applied to the 611111 signal output circuit 18. FIG.

An analog video signal of the image period is input to the input terminal 10. The input terminal 10 is connected to a coupling capacitor C.
1 to the collector of a clamping transistor Q1. Terminal 1 is connected to the base of transistor Q1.
A pedestal period pulse is applied via 1. The emitter of the transistor is connected to the reference potential point via the capacitor C2, and is also connected to the output end of the buffer circuit 12. The input terminal of the buffer circuit 120 is connected to the power supply 13
and a reference potential point to the sliding end of a variable resistor R1. Capacitor C1 and transistor Q1
The connection point with the collector of A/
It is connected to the D converter circuit 15.

The A/D conversion circuit 15 converts an analog video signal based on high level (hereinafter referred to as 118 It) and low level (hereinafter referred to as 11 L 11) reference voltages applied to the HR terminal and the LR terminal, respectively. The signal is converted into a digital signal and output to the image memory 17. In addition, the reference voltage of "H" is applied to the HR terminal from the power supply 13, and the "H" reference voltage is applied to the LR terminal through the buffer 7 circuit 16 from the connection point of resistors R2 and R3 connected between the power supply 13 and the reference potential point. A reference voltage of 1/2'' is applied.

The image memory 17 sequentially stores the video signals from the A/D conversion circuit 15, and also receives the HT+ control signal from the control signal output circuit 18 to an output enable terminal (not shown) and stores it as shown in FIG. Screen data is output to the D/A conversion circuit 19 from each output terminal. Further, each output terminal of the image memory 17 is connected to a resistor R4, R
5. It is connected to the reference potential point via R6, or to the power supply terminal 20 via resistor R7, so that it is in a high impedance state when the open signal is "L". It has become. The D/A conversion circuit 19 has an H'' reference voltage applied from the power supply 13 to the HR terminal, and resistors R4 and R5 connected between the power supply 13 and the reference potential point to the LR terminal.
The reference voltage of "L II" is applied from the connection point of D/ through the buffer 7 circuit 21, and the input digital signal is converted to an analog signal and output.
The output of the A conversion circuit 19 is led out to an output terminal 23 via a capacitor C3 and a buffer 7 circuit 22. 1. .

The sampling clock of the A/D conversion circuit 15 is input to the input terminal 24 of the control signal output circuit 18 shown in FIG. 2, the horizontal synchronization signal is input to the input terminal 25, and the vertical synchronization signal is input to the input terminal 26. is input.

The 10-bit h counter 27 counts the clock that can be input to the output terminal CK and outputs the count from the ROM2.
It is designed to output to 9. 8 bit counter 2
8 counts the horizontal synchronizing signal inputted to the rear end CK and outputs the count output to the ROM 30. The counter 21 is input to the clear end C [input terminal 25
The horizontal synchronization signal is input from counter 2, which is cleared.
8 is designed to be cleared by inputting a vertical synchronizing signal from the input terminal 26 to the clear terminal CL.

The ROM 29 supplies data whose address is designated by the count output of the counter 27 and is stored to one end of the AND circuit 31 . The ROM 30 is configured to supply data stored at an address designated by the count output of the counter 28 to the other end of the AND circuit 31. A
The ND circuit 31 makes sure that the outputs of the ROMs 29 and 30 are all “H”.
A control signal of "H" is applied to the output enable terminal of the image memory 17 via the output terminal 32 only when it is It.

Next, the operation of the video signal processing circuit configured as described above will be explained with reference to FIG. FIG. 3 is an explanatory diagram for explaining the relationship between the control signal of the control signal output circuit 18 and the display on the screen 35.

A video signal of an image period is inputted via an input terminal 10. Transistor Q is used during the pedestal period of the video signal.
1 is turned on. Thereby, the video signal input via the coupling capacitor C1 is clamped based on the voltage at the sliding end of the variable resistor R1. The clamped video signal of the A/D conversion circuit 15 is set to “H” and °
It is converted into a digital signal based on the reference voltage of "L" and outputted to the image memory 17. The image memory 17 sequentially stores this digital video signal.

On the other hand, the clock applied to the A/D conversion circuit 15 is also applied to the clock terminal C of the counter 27 via the input terminal 24. The counter 27 counts the clock and provides a count output to the ROM 29. This allows R.O.
Addresses are sequentially designated to M29, and the stored data is sequentially output to the AND circuit 31. The count value of the counter 27 is cleared every 1H period (one horizontal period), and each timing within one horizontal period is indicated by the count value. The ROM 29 stores "'H" at a predetermined series of addresses.
", and data "L II" is stored in another address. When the count value of the counter 27 indicates period A in FIG. 3, data of "H" is output.

On the other hand, the counter 28 counts the horizontal synchronization signal until it is cleared by the vertical synchronization signal, and the count value indicates a predetermined timing of the 1v period (one vertical period). When the count value of count 28 indicates the interval B11J in FIG. 3, the ROM 30 becomes “H” only during this period.
Output the data of II. AND circuit is ROM29.3
When all outputs of 0 are H'', a control signal of H11 is applied to the output enable terminal of the image memory 17.

Image memory 17 includes control signal output circuit 18 to 44811
By being given a control signal, the stored data is sequentially output, and when the control signal is L'', the output end is in a high impedance state.

That is, the data stored in the image memory 17 is input to the D/A conversion circuit 19 during periods A and B in FIG. 3, and the data determined by the resistors R4 to Rγ (for example, the black level data) is entered. The D/A conversion circuit 19 converts the input digital signal into an analog signal and outputs the analog signal based on the "H" or "L" reference voltage. The display screen 35 is driven by the video signal output from the output terminal 23, and images are displayed. In this way, the image memory 1 is placed in the area indicated by diagonal lines on the display screen 35.
An image based on the screen data from 7 is displayed, and an image with a black level, for example, is displayed in other areas.

In this way, in this embodiment, a control signal is given to the output enable end of the image memory 17 at a predetermined timing corresponding to the display area of the screen, and screen data is output during this period, and is output during other periods. The end is placed in a high impedance state to complement data in a non-image period that is not stored in the image memory 17, and switching without deteriorating the characteristics of the video signal is possible with a simple configuration.

Note that it is necessary to adjust the variable resistor R1 so that when the level of the video signal input through the input terminal 10 is O, a video signal with a level of 0 is output from the output terminal 23. If the previous stage circuit has an offset, when the input level of the previous stage circuit is set to O,
The output level may be adjusted to 0. Furthermore, it is better to connect each output terminal of the image memory 17 to the reference potential point or the power supply terminal 20 via the resistors R4 to R7, as the variable resistor R1
It is easy to adjust. In addition, the reference voltage of L18 applied to the A/D conversion circuit 15 is obtained by resistor voltage division of resistors R2 and R3, and the reference voltage of "L" of the D/A conversion circuit 19 is
The voltage is obtained by resistor voltage division of resistors R8 and R9, and “
The difference between the HIT reference voltage and the L'' reference voltage is resistor R2,
Since it is determined by R3, R8, and R9, even if the power supply voltage of the power supply 13 fluctuates, the influence on the output can be reduced.

Note that this embodiment has been described assuming that it is possible to put the output end of the image memory 17 into a high impedance state, but if it is not possible to put it into a high impedance state, the image memory 17 and the D/A conversion A tri-state buffer 7 circuit may be provided between the circuit 19 and the tri-state buffer circuit 7 to control the tri-state buffer circuit. Even in this case, the circuit scale can be reduced compared to a configuration in which a multiplexer is provided.

FIG. 4 is a circuit diagram showing a video signal processing circuit according to a second example of actual droplets of the present invention. In FIG. 4, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted.

In this embodiment, a FET Q2 is used in place of the clamping transistor Q1, and a constant voltage for clamping is obtained by voltage division between resistors R10 and R11.

Furthermore, a power supply 13.33 is connected to the LR terminal of the A/D conversion circuit 15.
A voltage from the power source 13.34 is applied to LR@ of the D/A conversion circuit 19 via the buffer circuit 21. Further, each output terminal of the image memory 17 is connected to a reference potential point via resistors R12 to R15, respectively.

In the embodiment configured in this manner, unlike the transistor Q1, there is no need to consider the collector-emitter voltage VCE, and the clamp voltage can be set as a constant voltage by the resistors R10 and R11.

In addition, by using high-precision power supplies 33 and 34, the A/D converter circuit 15 and the D/A converter circuit 19
By improving the accuracy of the reference voltage applied to each
D conversion and D/A conversion become possible.

[Effects of the Invention] As described above, according to the present invention, it is possible to configure the circuit with a simple circuit, and it is possible to prevent the characteristics of the video signal from deteriorating.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a video signal processing circuit according to the first embodiment of the present invention, and FIG.
FIG. 3 is a block diagram of a tiI + control signal ratio signal output circuit that outputs one signal. FIG. 3 is an explanatory diagram for explaining the relationship between the control signal of the control signal output circuit 18 and the display on the screen. FIG. A circuit diagram showing a video signal processing circuit according to a second embodiment, and FIGS. 5 and 6 are block diagrams showing a conventional video signal processing circuit. 15... A/D conversion circuit, 16... Image memory, 1
9...D/A conversion circuit, R4-R7...Resistor. Figure 13 @ Figure 4

Claims (1)

[Scope of Claims] A control signal output circuit that outputs a control signal during a predetermined period corresponding to a predetermined area of a screen; and a control signal output circuit that stores a digital video signal of an image period and sequentially outputs the stored data based on the control signal. or an image memory whose output end is in a high impedance state; a resistor connected between the output end of the image memory and a reference potential point or a power supply; and a resistor means connected to the output end of the image memory for the predetermined period. is a D/A that inputs data stored in the image memory, inputs data indicating a predetermined level during a period when the output terminal of the image memory is in a high impedance state, converts these data into analog signals, and outputs the data. A video signal processing circuit comprising a conversion circuit.