JP2814814B2 - Thin film transistor substrate - Google Patents
Thin film transistor substrateInfo
- Publication number
- JP2814814B2 JP2814814B2 JP1491992A JP1491992A JP2814814B2 JP 2814814 B2 JP2814814 B2 JP 2814814B2 JP 1491992 A JP1491992 A JP 1491992A JP 1491992 A JP1491992 A JP 1491992A JP 2814814 B2 JP2814814 B2 JP 2814814B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- electrode wiring
- transistor substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、液晶表示装置に用いる
薄膜トランジスタ基板に関し、特に製造歩留りの高い薄
膜トランジスタ基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate used for a liquid crystal display device, and more particularly to a thin film transistor substrate having a high production yield.
【０００２】[0002]
【従来の技術】従来の薄膜トランジスタ基板は、図３に
示すように薄膜トランジスタのゲート電極１に接続する
走査電極配線２，ドレイン電極に接続する信号電極配線
４．半導体層６，ソース電極７，表示電極８とから少な
くとも構成されている。このため走査電極配線２と信号
電極配線４との交点５が１つ存在する。この部分は、通
常絶縁膜を用いて電気的に分離される。2. Description of the Related Art As shown in FIG. 3, a conventional thin film transistor substrate has a scanning electrode wiring 2 connected to a gate electrode 1 of a thin film transistor and a signal electrode wiring 4 connected to a drain electrode. It comprises at least a semiconductor layer 6, a source electrode 7, and a display electrode 8. Therefore, there is one intersection 5 between the scanning electrode wiring 2 and the signal electrode wiring 4. This part is usually electrically separated using an insulating film.
【０００３】また、他の従来の薄膜トランジスタ基板
は、図４に示すように走査電極配線２が信号電極配線４
付近で２本に別れ、走査電極配線２と信号電極配線４と
の交点５ａ，５ｂが２つある（例えば電子通信学会技術
研究報告，ＥＤ−８４，Ｎｏ．１５９，ｐ１７〜ｐ１
９）。この例では信号電極配線４がドレイン電極３を兼
ねていてドレイン電極３は信号電極配線４とゲート電極
１との重なり部分に相当している。In another conventional thin film transistor substrate, as shown in FIG.
There are two intersections 5a and 5b between the scanning electrode wiring 2 and the signal electrode wiring 4 in the vicinity (for example, IEICE Technical Report, ED-84, No. 159, p17 to p1).
9). In this example, the signal electrode wiring 4 also serves as the drain electrode 3, and the drain electrode 3 corresponds to a portion where the signal electrode wiring 4 and the gate electrode 1 overlap.
【０００４】[0004]
【発明が解決しようとする課題】この従来の薄膜トラン
ジスタ基板では、ゲート電極１とドレイン電極３で短絡
欠陥がある場合、図３の薄膜トランジスタ基板では、ゲ
ート電極１と走査電極配線２との接続部をレーザ等で切
断することにより線欠陥となることを防ぎ、図４のもの
では走査電極配線２の２本に別れたゲート電極１側の走
査電極配線２を切断することにより線欠陥となることを
防ぐことができる。しかしながら、両者とも走査電極配
線２と信号電極配線４との交点での短絡欠陥修正および
断線欠陥修正はできないという問題点があった。In this conventional thin film transistor substrate, when there is a short-circuit defect in the gate electrode 1 and the drain electrode 3, in the thin film transistor substrate of FIG. 3, the connection between the gate electrode 1 and the scanning electrode wiring 2 is changed. By cutting with a laser or the like, line defects are prevented, and in the case of FIG. 4, line defects are caused by cutting the scanning electrode wiring 2 on the side of the gate electrode 1 which is separated into two scanning electrode wirings 2. Can be prevented. However, in both cases, there is a problem that correction of a short-circuit defect and correction of a disconnection defect at an intersection between the scanning electrode wiring 2 and the signal electrode wiring 4 cannot be performed.
【０００５】[0005]
【課題を解決するための手段】本発明は、薄膜トランジ
スタのゲート電極に接続する行状の走査電極配線と前記
薄膜トランジスタのドレイン電極に接続する列状の信号
電極配線とを少なくとも有する薄膜トランジスタ基板に
おいて、行状の走査電極配線と列状の信号電極配線との
交点部分を走査電極配線を２本以上に分けかつ信号電極
配線を２本以上に分けて交点を２×２以上のマトリクス
とすることを特徴とする。According to the present invention, there is provided a thin film transistor substrate having at least a row-shaped scanning electrode wiring connected to a gate electrode of a thin film transistor and a column-shaped signal electrode wiring connected to a drain electrode of the thin film transistor. The intersection between the scanning electrode wiring and the column-shaped signal electrode wiring is divided into two or more scanning electrode wirings, and the signal electrode wiring is divided into two or more wirings, and the intersection is formed into a matrix of 2 × 2 or more. .
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の第１の実施例の薄膜トランジスタ基
板を示す平面図である。基板に導電体を成膜し、ホトリ
ソグラフィ技術を用いてパターニングしたあと不要部分
の導電体をエッチング除去しゲート電極１と走査電極配
線２を形成する。次に、プラズマケミカルベーパーデポ
ジション（ＰＣＶＤ）法により絶縁層，半導体層を連続
成膜し、ホトリソグラフィ技術を用いてパターニングし
たあと不要部分の半導体層をエッチング除去し半導体層
６を形成する。次に導電体を成膜し、ホトリソグラフィ
技術を用いてパターニングしたあと不要部分の導電体を
エッチング除去しドレイン電極３と信号電極配線４を形
成する。さらに、透明導電体を成膜しホトリソグラフィ
技術を用いてパターニングしたあと不要部分の透明導電
体をエッチング除去し表示電極８を形成し薄膜トランジ
スタ基板を形成した。走査電極配線２と信号電極配線４
とは、それらの交点部分はともに２本に分け、交点５ａ
〜５ｄは２×２のマトリクスとした。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a plan view showing a thin film transistor substrate according to a first embodiment of the present invention. After forming a conductor on the substrate and patterning it by photolithography, unnecessary portions of the conductor are removed by etching to form a gate electrode 1 and a scanning electrode wiring 2. Next, an insulating layer and a semiconductor layer are continuously formed by a plasma chemical vapor deposition (PCVD) method, and after patterning using a photolithography technique, unnecessary portions of the semiconductor layer are removed by etching to form a semiconductor layer 6. Next, a conductor is formed and patterned by photolithography. Then, unnecessary portions of the conductor are removed by etching to form a drain electrode 3 and a signal electrode wiring 4. Further, a transparent conductor was formed and patterned by photolithography. Then, unnecessary portions of the transparent conductor were removed by etching to form a display electrode 8, thereby forming a thin film transistor substrate. Scan electrode wiring 2 and signal electrode wiring 4
Means that their intersection is divided into two parts, and the intersection 5a
5d is a 2 × 2 matrix.
【０００７】対角１４インチ表示数１０２４×１０２４
×３のカラー液晶ディスプレイを製造した場合の配線欠
陥についてのみの歩留りを図３に示した従来のものと比
較すると、従来のもののストレートの歩留りは７０％，
修理を含む歩留りは７５％であるのに対し、本発明のも
のはストレートの歩留り７５％、修理を含む歩留りは９
５％であった。本発明のものでストレートの歩留りも良
くなるのは、短絡による欠陥発生の増加よりも断線によ
る欠陥発生の阻止の割合が多いためである。また、修正
できないものがあるのは、短絡が高抵抗の場合ディスプ
レイに組み立てないと発見できない欠陥があり、ディス
プレイに組み立てると交点５ａ〜５ｄのどこが欠陥なの
か判別できないことがあるためである。[0007] 14 inch diagonal display number 1024 x 1024
Comparing the yield of only the wiring defect when a × 3 color liquid crystal display is manufactured with the conventional one shown in FIG. 3, the straight yield of the conventional one is 70%,
The yield including repair is 75%, while the yield of the present invention is 75% for straight and the yield including repair is 9%.
5%. The reason why the straight line yield is improved in the present invention is that the rate of preventing the occurrence of defects due to disconnection is larger than the rate of increasing the occurrence of defects due to short circuit. In addition, the reason why some of the defects cannot be corrected is that when the short circuit has a high resistance, there is a defect that cannot be found unless assembled in the display, and when assembled in the display, it may not be possible to determine which of the intersections 5a to 5d is defective.
【０００８】図２は、本発明の第２の実施例の薄膜トラ
ンジスタ基板を示す平面図である。製造方法は第１の実
施例と同じであるが、表示電極は８ａ〜８ｄに４分割し
てある。このものの歩留りはストレートで７５％、修理
を含む歩留りは１００％であった。これは第１の実施例
ではディスプレイに組み立ててからでは欠陥の判別がで
きなかったのに対し、第２の実施例では欠陥個所に近い
表示電極にかかる電圧が他と異なるためディスプレイを
表示させた場合に表示濃度が他と異なって見え欠陥のあ
る交点の個所の判別ができるためである。FIG. 2 is a plan view showing a thin film transistor substrate according to a second embodiment of the present invention. The manufacturing method is the same as that of the first embodiment, but the display electrodes are divided into four parts 8a to 8d. The yield was 75% straight and 100% including repairs. This is because, in the first embodiment, the defect could not be determined after assembling the display, whereas in the second embodiment, the display was displayed because the voltage applied to the display electrode near the defective portion was different from the others. This is because, in such a case, it is possible to determine the point of the intersection where the display density is different from the others and there is a defect.
【０００９】[0009]
【発明の効果】以上説明したように本発明は、交点部分
で走査電極配線を２本以上に分けかつ信号電極配線を２
本以上に分けて交点を２×２以上のマトリクスとしたこ
とにより、断線欠陥が発生しても修正が可能であること
により薄膜トランジスタ基板の歩留りを向上できるとい
う効果を有する。As described above, according to the present invention, the scanning electrode wiring is divided into two or more at the intersection and the signal electrode wiring is divided into two.
By dividing the matrix into 2 × 2 or more matrices, it is possible to improve the yield of the thin film transistor substrate because it is possible to correct even if a disconnection defect occurs.
【図１】本発明の第１の実施例の薄膜トランジスタ基板
の平面図である。FIG. 1 is a plan view of a thin film transistor substrate according to a first embodiment of the present invention.
【図２】本発明の第２の実施例の薄膜トランジスタ基板
の平面図である。FIG. 2 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention.
【図３】従来の薄膜トランジスタ基板の平面図である。FIG. 3 is a plan view of a conventional thin film transistor substrate.
【図４】従来の薄膜トランジスタ基板の他の例の平面図
である。FIG. 4 is a plan view of another example of a conventional thin film transistor substrate.
１ ゲート電極 ２ 走査電極配線 ３ ドレイン電極 ４ 信号電極配線 ５，５ａ〜５ｄ 交点 ６ 半導体層 ７ ソース電極 ８，８ａ〜８ｄ 表示電極 DESCRIPTION OF SYMBOLS 1 Gate electrode 2 Scanning electrode wiring 3 Drain electrode 4 Signal electrode wiring 5,5a-5d Intersection 6 Semiconductor layer 7 Source electrode 8,8a-8d Display electrode
Claims (1)
スタのゲート電極およびドレイン電極にそれぞれ接続す
る走査電極配線および信号電極配線と、前記薄膜トラン
ジスタのソース電極に接続する表示電極とを有する薄膜
トランジスタ基板において、前記走査電極配線と信号電
極配線との交点部分の前記走査電極配線および信号電極
配線をそれぞれ２本に分けて４個の交点とし、各交点に
対応してそれぞれ薄膜トランジスタと表示電極とを設け
たことを特徴とする薄膜トランジスタ基板。A thin film transistor and said thin film transistor
Connected to the gate and drain electrodes of the
Scanning electrode wiring and signal electrode wiring, and the thin film transistor
In a thin film transistor substrate having a display electrode connected to a source electrode of a transistor, the scanning electrode wiring and the signal electrode at an intersection of the scanning electrode wiring and the signal electrode wiring
Divide the wiring into two and make four intersections.
Correspondingly provided thin film transistor and display electrode
A thin film transistor substrate characterized by the above-mentioned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1491992A JP2814814B2 (en) | 1992-01-30 | 1992-01-30 | Thin film transistor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1491992A JP2814814B2 (en) | 1992-01-30 | 1992-01-30 | Thin film transistor substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05224234A JPH05224234A (en) | 1993-09-03 |
| JP2814814B2 true JP2814814B2 (en) | 1998-10-27 |
Family
ID=11874376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1491992A Expired - Lifetime JP2814814B2 (en) | 1992-01-30 | 1992-01-30 | Thin film transistor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2814814B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050075280A (en) | 2002-11-19 | 2005-07-20 | 가부시키가이샤 이시카와 세이사쿠쇼 | Pixel control element selection transfer method, pixel control element mounting device used for pixel control element selection transfer method, wiring formation method after pixel control element transfer, and planar display substrate |
| KR100776503B1 (en) * | 2002-12-02 | 2007-11-15 | 엘지.필립스 엘시디 주식회사 | Structure of lcd pixel |
| JP2005164854A (en) | 2003-12-01 | 2005-06-23 | Nec Lcd Technologies Ltd | Liquid crystal display device |
| CN101290408B (en) * | 2007-04-17 | 2010-04-14 | 北京京东方光电科技有限公司 | Thin film transistor display |
| JP5125671B2 (en) * | 2008-03-26 | 2013-01-23 | ソニー株式会社 | Image display device, defect detection method, and short-circuit accident repair method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61147285A (en) * | 1984-12-21 | 1986-07-04 | キヤノン株式会社 | Display element and repair thereof |
-
1992
- 1992-01-30 JP JP1491992A patent/JP2814814B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05224234A (en) | 1993-09-03 |
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