JPH05224234A - Thin-film transistor substrate - Google Patents
Thin-film transistor substrateInfo
- Publication number
- JPH05224234A JPH05224234A JP1491992A JP1491992A JPH05224234A JP H05224234 A JPH05224234 A JP H05224234A JP 1491992 A JP1491992 A JP 1491992A JP 1491992 A JP1491992 A JP 1491992A JP H05224234 A JPH05224234 A JP H05224234A
- Authority
- JP
- Japan
- Prior art keywords
- film transistor
- thin film
- transistor substrate
- electrode wiring
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、液晶表示装置に用いる
薄膜トランジスタ基板に関し、特に製造歩留りの高い薄
膜トランジスタ基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate used in a liquid crystal display device, and more particularly to a thin film transistor substrate having a high manufacturing yield.
【0002】[0002]
【従来の技術】従来の薄膜トランジスタ基板は、図3に
示すように薄膜トランジスタのゲート電極1に接続する
走査電極配線2,ドレイン電極に接続する信号電極配線
4.半導体層6,ソース電極7,表示電極8とから少な
くとも構成されている。このため走査電極配線2と信号
電極配線4との交点5が1つ存在する。この部分は、通
常絶縁膜を用いて電気的に分離される。2. Description of the Related Art A conventional thin film transistor substrate includes a scan electrode wiring 2 connected to a gate electrode 1 of a thin film transistor 2, a signal electrode wiring 4 connected to a drain electrode 4 as shown in FIG. At least the semiconductor layer 6, the source electrode 7, and the display electrode 8 are formed. Therefore, there is one intersection 5 between the scanning electrode wiring 2 and the signal electrode wiring 4. This portion is usually electrically isolated by using an insulating film.
【0003】また、他の従来の薄膜トランジスタ基板
は、図4に示すように走査電極配線2が信号電極配線4
付近で2本に別れ、走査電極配線2と信号電極配線4と
の交点5a,5bが2つある(例えば電子通信学会技術
研究報告,ED−84,No.159,p17〜p1
9)。この例では信号電極配線4がドレイン電極3を兼
ねていてドレイン電極3は信号電極配線4とゲート電極
1との重なり部分に相当している。Further, in another conventional thin film transistor substrate, as shown in FIG. 4, the scanning electrode wiring 2 is a signal electrode wiring 4
There are two intersections 5a and 5b between the scanning electrode wiring 2 and the signal electrode wiring 4 in the vicinity (for example, Technical Report of the Institute of Electronics and Communication Engineers, ED-84, No. 159, p17 to p1).
9). In this example, the signal electrode wiring 4 also serves as the drain electrode 3, and the drain electrode 3 corresponds to the overlapping portion of the signal electrode wiring 4 and the gate electrode 1.
【0004】[0004]
【発明が解決しようとする課題】この従来の薄膜トラン
ジスタ基板では、ゲート電極1とドレイン電極3で短絡
欠陥がある場合、図3の薄膜トランジスタ基板では、ゲ
ート電極1と走査電極配線2との接続部をレーザ等で切
断することにより線欠陥となることを防ぎ、図4のもの
では走査電極配線2の2本に別れたゲート電極1側の走
査電極配線2を切断することにより線欠陥となることを
防ぐことができる。しかしながら、両者とも走査電極配
線2と信号電極配線4との交点での短絡欠陥修正および
断線欠陥修正はできないという問題点があった。In this conventional thin film transistor substrate, when there is a short circuit defect in the gate electrode 1 and the drain electrode 3, in the thin film transistor substrate of FIG. 3, the connection portion between the gate electrode 1 and the scan electrode wiring 2 is formed. It is possible to prevent a line defect by cutting with a laser or the like, and to prevent a line defect by cutting the scan electrode wiring 2 on the side of the gate electrode 1 which is divided into two scan electrode wirings 2 in FIG. Can be prevented. However, both of them have a problem that the short-circuit defect and the disconnection defect cannot be corrected at the intersection of the scanning electrode wiring 2 and the signal electrode wiring 4.
【0005】[0005]
【課題を解決するための手段】本発明は、薄膜トランジ
スタのゲート電極に接続する行状の走査電極配線と前記
薄膜トランジスタのドレイン電極に接続する列状の信号
電極配線とを少なくとも有する薄膜トランジスタ基板に
おいて、行状の走査電極配線と列状の信号電極配線との
交点部分を走査電極配線を2本以上に分けかつ信号電極
配線を2本以上に分けて交点を2×2以上のマトリクス
とすることを特徴とする。The present invention provides a thin film transistor substrate having at least row-shaped scan electrode wirings connected to gate electrodes of thin film transistors and column-shaped signal electrode wirings connected to drain electrodes of the thin film transistors. The intersections of the scanning electrode wirings and the column-shaped signal electrode wirings are characterized by dividing the scanning electrode wirings into two or more and dividing the signal electrode wirings into two or more and forming the intersections into a matrix of 2 × 2 or more. ..
【0006】[0006]
【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の第1の実施例の薄膜トランジスタ基
板を示す平面図である。基板に導電体を成膜し、ホトリ
ソグラフィ技術を用いてパターニングしたあと不要部分
の導電体をエッチング除去しゲート電極1と走査電極配
線2を形成する。次に、プラズマケミカルベーパーデポ
ジション(PCVD)法により絶縁層,半導体層を連続
成膜し、ホトリソグラフィ技術を用いてパターニングし
たあと不要部分の半導体層をエッチング除去し半導体層
6を形成する。次に導電体を成膜し、ホトリソグラフィ
技術を用いてパターニングしたあと不要部分の導電体を
エッチング除去しドレイン電極3と信号電極配線4を形
成する。さらに、透明導電体を成膜しホトリソグラフィ
技術を用いてパターニングしたあと不要部分の透明導電
体をエッチング除去し表示電極8を形成し薄膜トランジ
スタ基板を形成した。走査電極配線2と信号電極配線4
とは、それらの交点部分はともに2本に分け、交点5a
〜5dは2×2のマトリクスとした。The present invention will be described below with reference to the drawings. 1 is a plan view showing a thin film transistor substrate of a first embodiment of the present invention. A conductor is deposited on the substrate, patterned by using a photolithography technique, and then unnecessary portions of the conductor are removed by etching to form the gate electrode 1 and the scan electrode wiring 2. Next, an insulating layer and a semiconductor layer are continuously formed by the plasma chemical vapor deposition (PCVD) method, and the semiconductor layer 6 is formed by patterning using a photolithography technique and then removing the unnecessary semiconductor layer by etching. Next, a conductor is formed into a film and patterned by using a photolithography technique, and then the unnecessary part of the conductor is removed by etching to form the drain electrode 3 and the signal electrode wiring 4. Further, a transparent conductor was formed into a film and patterned by using a photolithography technique, and then an unnecessary portion of the transparent conductor was removed by etching to form a display electrode 8 to form a thin film transistor substrate. Scan electrode wiring 2 and signal electrode wiring 4
And, the intersections of them are both divided into two, and the intersection 5a
˜5d is a 2 × 2 matrix.
【0007】対角14インチ表示数1024×1024
×3のカラー液晶ディスプレイを製造した場合の配線欠
陥についてのみの歩留りを図3に示した従来のものと比
較すると、従来のもののストレートの歩留りは70%,
修理を含む歩留りは75%であるのに対し、本発明のも
のはストレートの歩留り75%、修理を含む歩留りは9
5%であった。本発明のものでストレートの歩留りも良
くなるのは、短絡による欠陥発生の増加よりも断線によ
る欠陥発生の阻止の割合が多いためである。また、修正
できないものがあるのは、短絡が高抵抗の場合ディスプ
レイに組み立てないと発見できない欠陥があり、ディス
プレイに組み立てると交点5a〜5dのどこが欠陥なの
か判別できないことがあるためである。14-inch diagonal display number 1024 × 1024
Comparing the yield only for wiring defects in the case of manufacturing a × 3 color liquid crystal display with the conventional one shown in FIG. 3, the straight yield of the conventional one is 70%,
The yield including repairs is 75%, whereas that of the present invention is 75% in straight yield, and the yield including repairs is 9%.
It was 5%. The reason why the straight yield in the present invention is also improved is that the rate of prevention of defect occurrence due to disconnection is higher than the increase of defect occurrence due to short circuit. In addition, the reason why there is something that cannot be corrected is that if the short circuit has a high resistance, there is a defect that cannot be discovered unless assembled in the display, and when assembled in the display, it may not be possible to determine where the intersection points 5a to 5d are defective.
【0008】図2は、本発明の第2の実施例の薄膜トラ
ンジスタ基板を示す平面図である。製造方法は第1の実
施例と同じであるが、表示電極は8a〜8dに4分割し
てある。このものの歩留りはストレートで75%、修理
を含む歩留りは100%であった。これは第1の実施例
ではディスプレイに組み立ててからでは欠陥の判別がで
きなかったのに対し、第2の実施例では欠陥個所に近い
表示電極にかかる電圧が他と異なるためディスプレイを
表示させた場合に表示濃度が他と異なって見え欠陥のあ
る交点の個所の判別ができるためである。FIG. 2 is a plan view showing a thin film transistor substrate of a second embodiment of the present invention. The manufacturing method is the same as that of the first embodiment, but the display electrode is divided into 8a to 8d. The yield of this product was 75% for straight and the yield including repair was 100%. In the first embodiment, the defect could not be discriminated after it was assembled into the display, whereas in the second embodiment, the display electrode was displayed because the voltage applied to the display electrode near the defect location was different from the others. This is because, in this case, the display density is different from the others, and it is possible to determine the location of the intersection having a visual defect.
【0009】[0009]
【発明の効果】以上説明したように本発明は、交点部分
で走査電極配線を2本以上に分けかつ信号電極配線を2
本以上に分けて交点を2×2以上のマトリクスとしたこ
とにより、断線欠陥が発生しても修正が可能であること
により薄膜トランジスタ基板の歩留りを向上できるとい
う効果を有する。As described above, according to the present invention, the scanning electrode wiring is divided into two or more and the signal electrode wiring is divided into two at the intersection point.
By dividing the matrix into two or more and dividing the matrix into 2 × 2 or more, even if a disconnection defect occurs, it can be repaired, so that the yield of the thin film transistor substrate can be improved.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の第1の実施例の薄膜トランジスタ基板
の平面図である。FIG. 1 is a plan view of a thin film transistor substrate according to a first embodiment of the present invention.
【図2】本発明の第2の実施例の薄膜トランジスタ基板
の平面図である。FIG. 2 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention.
【図3】従来の薄膜トランジスタ基板の平面図である。FIG. 3 is a plan view of a conventional thin film transistor substrate.
【図4】従来の薄膜トランジスタ基板の他の例の平面図
である。FIG. 4 is a plan view of another example of a conventional thin film transistor substrate.
【符号の説明】 1 ゲート電極 2 走査電極配線 3 ドレイン電極 4 信号電極配線 5,5a〜5d 交点 6 半導体層 7 ソース電極 8,8a〜8d 表示電極[Explanation of Codes] 1 gate electrode 2 scan electrode wiring 3 drain electrode 4 signal electrode wiring 5, 5a to 5d intersection 6 semiconductor layer 7 source electrode 8, 8a to 8d display electrode
Claims (1)
る走査電極配線と前記薄膜トランジスタのドレイン電極
に接続する信号電極配線とを少なくとも有する薄膜トラ
ンジスタ基板において、前記走査電極配線と前記信号電
極配線との交点部分を前記走査電極配線を2本以上に分
けかつ前記信号電極配線を2本以上に分けて交点を2×
2以上のマトリクスとすることを特徴とする薄膜トラン
ジスタ基板。1. In a thin film transistor substrate having at least a scanning electrode wiring connected to a gate electrode of a thin film transistor and a signal electrode wiring connected to a drain electrode of the thin film transistor, an intersection portion of the scanning electrode wiring and the signal electrode wiring is aforesaid. The scanning electrode wiring is divided into two or more and the signal electrode wiring is divided into two or more, and the intersection is 2 ×.
A thin film transistor substrate having a matrix of two or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1491992A JP2814814B2 (en) | 1992-01-30 | 1992-01-30 | Thin film transistor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1491992A JP2814814B2 (en) | 1992-01-30 | 1992-01-30 | Thin film transistor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05224234A true JPH05224234A (en) | 1993-09-03 |
JP2814814B2 JP2814814B2 (en) | 1998-10-27 |
Family
ID=11874376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1491992A Expired - Lifetime JP2814814B2 (en) | 1992-01-30 | 1992-01-30 | Thin film transistor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2814814B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100683288B1 (en) * | 2003-12-01 | 2007-02-15 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | Liquid crystal display unit |
KR100776503B1 (en) * | 2002-12-02 | 2007-11-15 | 엘지.필립스 엘시디 주식회사 | Structure of lcd pixel |
JP2008268860A (en) * | 2007-04-17 | 2008-11-06 | Beijing Boe Optoelectronics Technology Co Ltd | Liquid crystal display, and manufacturing method and repairing method thereof |
US7585703B2 (en) | 2002-11-19 | 2009-09-08 | Ishikawa Seisakusho, Ltd. | Pixel control element selection transfer method, pixel control device mounting device used for pixel control element selection transfer method, wiring formation method after pixel control element transfer, and planar display substrate |
JP2009237040A (en) * | 2008-03-26 | 2009-10-15 | Sony Corp | Image display, defect detecting method, shirt circuit accident restoring method |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61147285A (en) * | 1984-12-21 | 1986-07-04 | キヤノン株式会社 | Display element and repair thereof |
-
1992
- 1992-01-30 JP JP1491992A patent/JP2814814B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61147285A (en) * | 1984-12-21 | 1986-07-04 | キヤノン株式会社 | Display element and repair thereof |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7585703B2 (en) | 2002-11-19 | 2009-09-08 | Ishikawa Seisakusho, Ltd. | Pixel control element selection transfer method, pixel control device mounting device used for pixel control element selection transfer method, wiring formation method after pixel control element transfer, and planar display substrate |
KR100776503B1 (en) * | 2002-12-02 | 2007-11-15 | 엘지.필립스 엘시디 주식회사 | Structure of lcd pixel |
KR100683288B1 (en) * | 2003-12-01 | 2007-02-15 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | Liquid crystal display unit |
US7511301B2 (en) | 2003-12-01 | 2009-03-31 | Nec Lcd Technologies, Ltd. | Liquid crystal display unit |
JP2008268860A (en) * | 2007-04-17 | 2008-11-06 | Beijing Boe Optoelectronics Technology Co Ltd | Liquid crystal display, and manufacturing method and repairing method thereof |
US8654053B2 (en) | 2007-04-17 | 2014-02-18 | Beijing Boe Optoelectronics Technology Co., Ltd. | Liquid crystal display device, manufacturing method and repair method thereof |
JP2009237040A (en) * | 2008-03-26 | 2009-10-15 | Sony Corp | Image display, defect detecting method, shirt circuit accident restoring method |
Also Published As
Publication number | Publication date |
---|---|
JP2814814B2 (en) | 1998-10-27 |
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