JP2814034B2 - Method for manufacturing power control semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a power control semiconductor device such as a thyristor and a triac, and more particularly to a semiconductor device having a small leakage current at the time of interruption.

[0002]

2. Description of the Related Art An example of a conventional method for manufacturing a thyristor will be described with reference to FIG. 3. Gallium is diffused on both sides of an N-type semiconductor wafer 31 to form a P-type layer 32 on both sides as shown in FIG. And 33 are formed. And P
When phosphorus is selectively diffused into a part of the mold layer 32, an N-type layer 34 is formed as shown in FIG. 3B, and a four-layer structure of NPNP is formed. Therefore, as shown in FIG.
The thyristor is completed by providing the gate electrode 35 on the exposed portion of the mold layer 32, the cathode 36 on the N-type layer 34, and the anode 37 on the P-type layer 33.

[0003]

As shown in FIG. 4, a single-phase half-wave power supply 41, a load resistor 42 and a current measuring circuit 43 are connected in series between a cathode 36 and an anode 37 of the thyristor described above. A gate control circuit 44 is connected between the electrode 35 and the anode 37. The output voltage V _DR of the single-phase half-wave power supply 41 starts at a phase angle of 0 °, reaches a maximum value at a phase angle of 90 °, returns to 0 at a phase angle of 180 ° as shown in FIG. repeat. Maximum permissible instantaneous value of the OFF voltage V _DR that can be applied repeatedly with the gate open Repetitive peak off-state voltage V _DRM a.

Then, the gate control circuit 44 is operated, and as shown in FIG.
1 is generated and applied to the gate electrode 35, the thyristor is turned on, and the cathode 3 is turned on during a phase angle of 90 ° to 180 ° as shown by oblique lines in FIG.
A current flows between 6 and the anode 37.

[0005] Therefore, when the phase angle examine the leakage current I _DR between the cathode 36 and the anode 37 in the cut-off period of 0 ° to 90 °, as shown in FIG. 5 (c), the peak repetition off voltage V _DRM Rapidly increases from around 1/2 to 2/3. This increased leakage current results in increased power loss.
An object of the present invention is to suppress an increase in leakage current in the vicinity of a peak repetition off voltage V _DRM .

[0006]

In the manufacture of a power control semiconductor device according to the present invention, impurities are diffused on both surfaces of a semiconductor of a first conductivity type to form a layer of a second conductivity type, and at least one of the layers is formed. After the impurity is selectively diffused into a part of the surface to return to the first conductivity type layer, the surface part of the selective diffusion layer is removed by etching.

The range of etching of the selective diffusion layer is suitably about 1/4 to 1/3 of the thickness of the layer. In addition, this etching may be performed not only on the surface layer of the selective diffusion layer but also on the surface layer of the adjacent portion having a different conductivity type.

[0008]

[Action] increase in the leakage current I _DR in the vicinity of the above-mentioned peak repetitive off voltage V _DRM, the impurity is selected diffusion,
This is considered to be due to the fact that they are gathered on the surface portion of the selective diffusion layer. Therefore, by removing the surface layer portion of the selective diffusion layer by etching to remove the portion where impurities are gathered, it is possible to prevent an increase in leakage current due to the gathering of impurities.

[0009]

As shown in FIG. 1A, gallium is diffused from both sides of a 900 μm thick N-type wafer 1 to a depth of 100 μm to form P-type layers 2 and 3. Next, FIG.
As shown in (b), phosphorus is selectively diffused from the surface of the P-type layer 2 to a depth of 20 μm to form an N-type selective diffusion layer 4. Further, the exposed P-type layer 2 and selective diffusion layer 4 are
Etching was performed with buffered hydrofluoric acid to remove the surface shown in FIG.
The structure shown in (c) is obtained.

Finally, the peripheral wall 9 is treated to form a mesa structure as shown in FIG. 1D, and the gate electrode 5 is formed on the exposed surface of the P-type layer 2.
A cathode electrode 6 is provided on the N-type selective diffusion layer 4 and an anode electrode 7 is provided on the P-type layer 3, so that the off-state voltage 4000
V, 1000A thyristor is completed. Leakage current I _DR of the thyristor, 0V peak repetitive off-state voltage V _DRM from the vicinity of the repetitive-off voltage V _DR, as shown in FIG. 2
It was 0.15 mA constantly until it reached the vicinity.

[0011]

As described above, according to the present invention, the power loss can be reduced by suppressing the increase of the leakage current in the vicinity of the peak repetition off-voltage of the semiconductor thyristor, and the same phenomenon of the increase of the leakage current occurs. The present invention can be applied to all power control semiconductor devices such as a triac to obtain an effect of reducing power loss.

[Brief description of the drawings]

FIG. 1 is a thyristor manufacturing process diagram embodying the present invention.

FIG. 2 is a graph showing off-voltage vs. leakage current characteristics of a thyristor obtained by the manufacturing process of FIG.

FIG. 3 is a view showing a conventional thyristor manufacturing process.

FIG. 4 is a diagram showing a circuit for measuring off-state voltage versus leakage current characteristics.

FIG. 5 is an explanatory diagram of voltage and current in each section of FIG.

[Explanation of symbols]

 Reference Signs List 1 N-type (first conductivity type) semiconductor wafer 2 P-type (second conductivity type) diffusion layer 3 P-type (second conductivity type) diffusion layer 4 N-type (first conductivity type) selective diffusion layer 5 Gate electrode 6 Cathode electrode 7 Anode electrode 8 Etching level

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/74 H01L 29/747

Claims (1)

(57) [Claims] 1. A step of diffusing impurities on both surfaces of a semiconductor of a first conductivity type to form a layer of a second conductivity type, and forming a layer of the second conductivity type on at least one surface of the semiconductor. A method for manufacturing a power control semiconductor device, comprising: a step of selectively diffusing an impurity to return to a first conductivity type layer; and a step of removing a surface portion of the selective diffusion layer by etching.