JP3199924B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a semiconductor device to which a lifetime control technique is applied and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 6 is a sectional view showing the structure of a conventional semiconductor device. A semiconductor region 2 doped with impurities is formed on the surface of a semiconductor substrate 1, an insulating film 3 having an opening is formed on the semiconductor region 2 on the substrate, and an electrode 4 is formed on the insulating film 3.
And is connected to the semiconductor region 2 via. An electrode 4 is also formed on the back surface of the semiconductor substrate 1. In such a semiconductor device, a low lifetime layer 5 in which the carrier lifetime is shortened with respect to the substrate is formed. When the semiconductor device shifts from the on state to the off state,
The carriers in the substrate are quickly recombined and disappear, contributing to high-speed switching.

A conventional lifetime control technique irradiates the semiconductor device with any one of H ⁺ , ³ He ²⁺ , and ⁴ He ²⁺ ,
A crystal defect is created in the stop region. Thereby, the low lifetime layer 5 is formed as a local layer.

In such a configuration, as shown in the figure, a low lifetime layer 5 is formed uniformly at a predetermined depth with respect to an irradiation surface. Therefore, when a voltage is applied to this semiconductor device in the forward direction, electrons always pass through the low lifetime layer 5. In the low-lifetime layer 5, the amount of carriers is attenuated due to active recombination of carriers. Therefore,
Compared with a semiconductor device without the low lifetime layer 5, a voltage (on-voltage) required to flow a certain current through the semiconductor device increases.

[0005]

In the conventional lifetime control, a low lifetime layer is formed uniformly in the substrate, and the electron path of the semiconductor device always passes through the lifetime layer, and the ON voltage is reduced. Becomes larger. As a result, the existence of such a low lifetime layer has
There is a disadvantage that power consumption increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has as its object to provide a low-lifetime layer for speeding up a switching operation and a current path not passing through the low-lifetime layer. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can reduce the on-state voltage by securing the semiconductor device.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor region of the second conductivity type selectively provided on the surface of the first semiconductor substrate for injecting carriers from the outside and a semiconductor layer provided in the semiconductor substrate deeper than the semiconductor region and alternately formed on a separated layer. And a divided lifetime control layer.

According to the method of manufacturing a semiconductor device of the present invention, a step of selectively forming a semiconductor region of the second conductivity type on a surface of a first semiconductor substrate, and a step of selectively etching one surface of the substrate to form uneven portions. Forming, and a step of irradiating the uneven portions with charged particles to alternately form lifetime control layers on predetermined spaced layers in the substrate.

[0009]

By alternately forming the lifetime control layers so as to be divided into two separated layers, a current path which contributes to carrier recombination and does not pass through the lifetime control layer is secured. It is necessary that the etching amount for forming the concave / convex portion is deeper than the half value width connecting two places where the defect density becomes half of the peak of the crystal defect density due to the lifetime control object.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a configuration of a semiconductor device according to the present invention. On a surface of a semiconductor substrate 1, a semiconductor region 2 into which an impurity of a conductivity type opposite to that of the substrate is introduced is formed.
An insulating film 3 having an opening on the semiconductor region 2 on the substrate
Is formed, and the electrode 4 is connected to the semiconductor region 2 via the insulating film 3. An electrode 4 is also formed on the back surface of the semiconductor substrate 1. In such a semiconductor device, in a semiconductor substrate deeper than the semiconductor region 2, low-lifetime layers 5 are alternately formed into separated layers.

According to the above configuration, carrier recombination is performed in the low-lifetime layer 5 divided into two layers, so that high-speed switching can be achieved, and a current path 6 that does not pass through the low-lifetime layer 5 can be secured. , Low on-voltage can be achieved.

FIGS. 2 to 4 are sectional views sequentially showing the steps of manufacturing the semiconductor device of FIG. 1 as a method of one embodiment of the present invention. As shown in FIG. 2, a silicon semiconductor substrate 1 on which a PN junction is selectively formed is oxidized at 1100 ° C. for 130 minutes in a steam atmosphere to form a silicon substrate 1 μm thick.
An insulating film (oxide film) 3 of m is formed.

As shown in FIG. 3, the oxide film 3 on the surface where the PN junction is not formed (the back surface of the substrate) is selectively etched. Using the remaining oxide film 3 as a mask, the flow rate ratio is HBr: NF ₃ : He = 45 SCCM: 7 SCCM: 7 SC
The Si of the substrate 1 is etched by RIE or the like for about 10 minutes at CM, pressure of 0.1 Torr, and RF power of 500 W. Thereby, an irradiation surface having an uneven portion is positively formed.

As shown in FIG. 4, the oxide film 3 is selectively etched to make contact with the semiconductor region 2, aluminum having a thickness of 1 μm is sputter-deposited on the front and back surfaces of the substrate, and after patterning as an electrode 4, Irradiation surface acceleration energy having a part of 7 MeV, dose amount 1 × 10 ¹² cm
Irradiate ³ He ²⁺ with ^-2 . Thus, a structure having the low lifetime layer 5 as shown in FIG. 1 is formed.

It is important that the etching amount of the substrate on which the irradiation surface of the uneven portion is formed is made deeper than the half value width connecting two places where the defect density is halved with respect to the peak of the crystal defect density due to the lifetime control object. is there. The half width is about 15 for H ⁺
μm and about 3 μm for He ²⁺ .

According to the method of the above embodiment, an uneven portion having a step of about 6 μm is formed on the surface irradiated with ³ He ²⁺ . ³ H
The half width of the defect generating region due to the e ²⁺ irradiation is about 3 μm, so that the current path 6 that does not pass through the low lifetime layer 5
Is formed.

FIG. 5 is a comparison between the semiconductor device of the embodiment and the semiconductor device of the conventional configuration, and is a characteristic diagram showing the relationship between the ON voltage and the switching speed. It can be evaluated that the configuration of the embodiment having the low lifetime layer 5 divided into two layers is superior to the conventional configuration in terms of higher switching speed and lower on-voltage of the element.

[0018]

As explained above, according to the present invention,
Lifetime control secures a current path that does not pass through the lifetime control layer while contributing to carrier recombination, so that high-speed switching operation and a reduction in on-voltage can be achieved. A semiconductor device which leads to power consumption and a manufacturing method thereof can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing a configuration of one embodiment of the present invention.

FIG. 2 is a first sectional view showing a manufacturing process of the semiconductor device of FIG. 1;

FIG. 3 is a second sectional view showing the manufacturing process of the semiconductor device of FIG. 1;

FIG. 4 is a third sectional view showing the manufacturing process of the semiconductor device of FIG. 1;

FIG. 5 is a characteristic diagram for evaluating a relationship between an on-voltage and a switching speed of the semiconductor device having the configuration of FIG. 1 and a semiconductor device having a conventional configuration.

FIG. 6 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

[Explanation of symbols]

1 ... semiconductor substrate, 2 ... semiconductor area, 3 ... insulating film, 4 ... electrode, 5 ... low lifetime layer.

Continuation of the front page (56) References JP-A-4-214674 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/322

Claims (4)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a second conductivity type selectively formed in a surface of said semiconductor substrate
And semiconductor region, formed in the semiconductor substrate deeper than the semiconductor region
First and second lifetime control layers , wherein the first and second lifetime control layers are
And formed at different depths from each other
A semiconductor device characterized by being separated by: 2. The method according to claim 1, wherein the first conductive type semiconductor substrate has a surface selectively.
Forming a semiconductor region of a second conductivity type, selectively etching a surface of the semiconductor substrate opposite to the surface on which the semiconductor region is formed to form an uneven portion; Irradiating the semiconductor substrate with a lifetime control object to form first and second lifetime control layers, wherein the first and second lifetime control layers are adjacent to each other, A method for manufacturing a semiconductor device, wherein the semiconductor devices are formed so as to be separated by being formed at different depths. To claim 2, characterized in that wherein before Symbol etching depth for forming the concavo-convex portion is approximately 1.5~30μm
The manufacturing method of the semiconductor device described in the above. 4. The lifetime control object includes H +, ³ He.
^{2+, 4} The method of manufacturing a semiconductor device according to claim 2, characterized in that it contains one at least one of the He ^2+.