JP2805621B2 - Image data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field of Use B Outline of the Invention C Prior Art D Problems to be Solved by the Invention E Means for Solving the Problems F Operation G Example H Effects of the Invention A Field of Industrial Use The present invention relates to: Writing discrete image data formed by sampling an image signal representing one screen to a memory,
The present invention relates to an image data processing apparatus that reads out written discrete image data from a memory in predetermined data block units and performs block processing on the discrete image data.

B. Summary of the Invention The present invention provides an image signal representing one screen in a horizontal direction of ^2K.
(K is a positive integer) pixels are obtained and J ·
2 ^M (J and M are positive integers) write discrete image data sampled and formed to obtain pixels into a memory, and write discrete image data of one screen written in the memory into
An image data processing device that reads out 2 ^N (N is a positive integer, N ≦ K) pixels in the horizontal direction and data blocks corresponding to image blocks of 2 ^M pixels in the vertical direction and performs block processing on discrete image data in, when the discrete image data for one screen in the memory is written, the write address data to the memory, from 0 to M + K + I-1 ( I is the maximum not exceeding one or log ₂ J + 1 is equal to log ₂ J (Integer), the address data is supplied from first address data generating means having M + K + I bit terminals, and when one screen of discrete image data is read from the memory, the read address data for the memory is:
Supplied from the second address data generating means having M + K + I bit terminals which can be expressed as 0 to M + K + I-1, each bit terminal of the first and second address data generating means has one of 0 to N- 1 corresponds to the other 0 to N−1, and one N to N + M−
1 corresponds to the other N + M to M + K−1, respectively, and one N + M to M + K−1 corresponds to the other N to N
+ M-1 respectively, and one M + K to M + K + I-1 corresponds to the other M + K to M + K + I-1.
The discrete image data for one screen written in the memory is converted into a data block unit equivalent to an image block of 2 ^N pixels in the horizontal direction and 2 ^M pixels in the vertical direction. In reading each time, the address control of the memory can be performed very easily,
According to the present invention, block processing of discrete image data can be facilitated and speeded up.

C Prior Art In a so-called video phone system for transmitting and receiving image information and audio information via an analog public telephone line,
Digital processing of an image signal is performed. In such digital processing of the image signal, discrete image data formed by sampling an image signal representing one screen and performing analog / digital conversion is written to a memory. It has been proposed to read the discrete image data from the memory in units of a predetermined data block and perform block processing on the discrete image data. Block processing on such discrete image data is performed, for example, with a circuit configuration as shown in FIG.

In the circuit configuration shown in FIG. 6, an image signal Sv introduced from an input terminal 10 is supplied to an analog / digital conversion unit (A / D conversion unit) 11, and the image signal Sv is supplied from the A / D conversion unit 11. So that a predetermined number of pixels can be obtained for each screen of
For example, a discrete image formed by being sampled and converted from analog to digital so that n pixels (n is a positive integer) in the horizontal direction and m pixels (m is a positive integer) in the vertical direction are obtained. Data Dv is obtained sequentially. The discrete image data Dv representing one screen obtained from the A / D conversion unit 11 is supplied to the memory 12 and is stored in the memory 12 according to the address data Da sent from the address counter 14 as write address data to the memory 12.
Is written to.

Next, the discrete image data Dv representing one screen written in the memory 12 is converted into an image block having a predetermined number of pixels, for example, according to the address data Db transmitted as read address data from the image block processing unit 15 to the memory 12. The corresponding data blocks are read out in units and taken in by the image block processing unit 15, and are read by the image block processing unit 15.
In, data block processing is performed on the discrete image data Dv. Each data block unit of the discrete image data Dv subjected to the data block processing in the image block processing unit 15 is transferred to the memory 12 again according to the address data Db transmitted as write address data from the image block processing unit 15 to the memory 12. Written sequentially.

After that, the discrete image data Dv ′ written to the memory 12 and subjected to the data block processing is stored in an address counter.
The data is read from the memory 12 according to the address data Da transmitted from the memory 14 as read address data to the memory 12, and is supplied to a digital / analog converter (D / A converter) 13. Then, an image signal based on the discrete image data Dv ′ subjected to the data block processing is output from the D / A conversion unit 13.
Sv 'is obtained and is output to the output terminal 16.

D Problems to be Solved by the Invention As described above, the discrete image data Dv is formed by sampling the image signal Sv representing one screen so that n pixels are obtained in the horizontal direction and m pixels are obtained in the vertical direction. When it is written to the memory 12, the memory 12 is assumed to have a capacity to accommodate data for m and n pixels, and the address data Da sent from the address counter 14 and the address data Da sent from the image block processing unit 15. Each of the address data Db to be written is log ₂ (mn) or log 2
₂ (m · n) +1, which is assumed to be equal to the maximum integer that does not exceed (X) bit code data, and the address data transmitting portions of the address counter 14 and the image block processing unit 15 are respectively provided with X address bits. It has terminals. Then, the connection relationship between the address counter 14 and the memory 12 is changed as shown in FIG.
The 14 address bit terminals a0 to aX are made to correspond to the address bit terminals A0 to AX in the memory 12, respectively, so that when the discrete image data Dv is written to the memory 12, the discrete image data Dv Are sequentially stored at the address designated positions in the memory 12, and are sequentially transmitted from the A / D converter 11 to form discrete image data Dv as shown in FIG. 8A.
The n pixel data units are stored in the memory 12 at positions corresponding to addresses 0 to mn-1.

Then, when the mn pixel data units forming the discrete image data Dv for one screen are taken into the image block processing unit 15 from the memory 12 for the data block processing, for example, in the horizontal direction, Data are read out in units of 16 data blocks formed by 16 pixel data units each corresponding to an image block of 4 pixels in the vertical direction with 4 pixels. At this time, the reading order of each pixel data unit from the memory 12 is the eighth order. In FIG. B, as shown by the numbers in [], first, 16 pixel data units forming a data block unit representing the first image block are 1 to 1.
The 16 pixel data units which are read out in the 16th order and form a data block unit representing the second image block following the first image block are 17 to 32.
The data blocks are sequentially read out in the same order, and similarly, data blocks representing the third and subsequent image blocks are sequentially read out. Therefore, as shown in FIG. 9, the correspondence between the sending order of the address data Db from the image block processing unit 15 and the address in the memory 12 where the address data Db is to be represented is 1, 2, 3, 4 as shown in FIG. Is the address 0,
Address data Db, which represents 1, 2, and 3, respectively, and the transmission order is 5, 6, 7, and 8, is the address n, n + 1, n + 2,
Address data Db, such as n + 3
Are arranged so that the addresses in the memory 12 which represent them are discontinuous every four.

As described above, the address data Db sent from the image block processing unit 15 does not represent an address indicated by a number whose content simply increases or decreases. At the time of sending the address data Db, it is required to perform an operation on the address in the memory 12 to be represented for every four sent out continuously. Therefore, the discrete image data for one screen written in the memory 12
For data block processing, the address control of the memory 12 in reading out the data blocks in units of data blocks corresponding to predetermined image blocks is not easily performed. In addition to complicating the configuration, it becomes difficult to facilitate and speed up the block processing of the discrete image data Dv.

In view of the above, the present invention writes discrete image data formed by sampling an image signal representing one screen into a memory, and writes the written discrete image data from the memory into a data block unit corresponding to a predetermined image block. In performing the block processing on the discrete image data by reading in, the discrete image data for one screen written in the memory is read out in data block units.
Memory address control can be performed very easily,
Accordingly, an object of the present invention is to provide an image data processing apparatus capable of facilitating and speeding up block processing of discrete image data.

To achieve the above-mentioned means purpose of solving the E is provided an image data processing apparatus according to the present invention, J · 2 ^M in the vertical direction together with the image signal representing one screen is obtained 2 ^K pixels in the horizontal direction An image data supply unit for sending discrete image data formed by sampling to obtain pixels, a memory for writing one screen of discrete image data sent from the image data supply unit, and A data block processing unit that reads out discrete image data for one screen by a data block unit corresponding to an image block of 2 ^N pixels in the horizontal direction and 2 ^M pixels in the vertical direction, and performs block processing on the discrete image data; A memory address control unit that performs address control on the memory, wherein the memory address control unit includes:
When discrete image data for one screen is written to the memory, the write address data for the memory is changed from 0 to M +
In addition to the supply from the first address data generating means having M + K + I bit terminals which can be expressed as K + I−1, when one screen of discrete image data is read from the memory to the data block processing unit, A second address having M + K + I bit terminals capable of representing read address data from 0 to M + K + I-1
And the bit terminals of the first and second address data generating means correspond to 0 to N-1 on one side and 0 to N-1 on the other side, respectively. N to N + M-1 is the other N + M to M
+ K-1 respectively, and one of N + M to M + K-
1 corresponds to the other N to N + M−1, respectively, and one M + K to M + K + I−1 corresponds to the other M
+ K to M + K + I−1, respectively.

In the image data processing device according to the present invention configured as described above, the memory address control unit transmits the write address data to the memory when the discrete image data for one screen is written to the memory. M + K + I bit terminals which can be represented as 0 to M + K + I-1 in the address data generating means of 1 and read address data for the memory when one screen of discrete image data is read from the memory to the data block processing section. 0 to M + K in the second address data generating means
+ I-1 and M + K + I bit terminals, one of which 0 to N-1 corresponds to the other 0 to N-1, and one of N to N + M-1 corresponds to the other N- M to M + K-1 respectively, one of N + M
To M + K-1 correspond to the other N to N + M-1, respectively, and one M + K to M + K + I-1 corresponds to the other M + K to M + K + I-1, respectively. When sending address data from the first and second address data generating means, it is not necessary to perform an operation on an address in a memory to be represented by the address data. Because of the data block processing, the address control of the memory when reading out the data block unit by data block and taking it into the data block processing unit can be performed extremely easily. Will be achieved.

G Embodiment FIG. 1 shows an example of an image data processing apparatus according to the present invention. In this example, the image signal Sv is introduced from the input terminal 30 and supplied to the A / D converter 31. A / D converter 31
In the above, one screen of the image signal Sv is sampled such that, for example, 16 pixels are obtained in the horizontal direction and 16 pixels are obtained in the vertical direction, and the analog / digital conversion is performed. Are sequentially formed.

The discrete image data Dv representing one screen obtained from the A / D conversion unit 31 is stored in the memory 32. The discrete image data Dv representing one screen once written in the memory 32 is read out, for example, in units of data blocks corresponding to an image block of 4 pixels in the horizontal direction and 4 pixels in the vertical direction, and is read out from the data buffer unit. Data block processing unit via 34
The data is processed by the data block processing unit 35. Then, discrete image data Dv
Is subjected to data block processing, is supplied to the memory 32 via the data buffer unit 34, and is written into the memory 32 again.

Thereafter, the discrete image data Dv 'subjected to the data block processing is read out from the memory 32 and supplied to a digital / analog conversion unit (D / A conversion unit) 33, where the data block processing is performed. Image data D subjected to
v ′ is converted into an analog signal to obtain an image signal Sv ′. The image signal Sv ′ obtained in the D / A converter 33 is
The signal is supplied to a signal adding unit 41 through a low-pass filter (LPF) 40, and the signal adding unit 41
The synchronizing signal Ss supplied from 39 is added to form a composite image signal Svc. Then, the signal adding unit 41
Are derived to the output terminal 42.

The data block processing unit 35 is supposed to perform data block processing on the discrete image data Dv fetched from the memory 32, and further has a built-in address data forming unit, and eight data blocks connected to the address data forming unit. The address bit terminals B0 to B7 transmit address data DB, which is 8-bit code data, and further serve as a control unit for controlling the operation of the memory 32 and the like. A signal Cs and a write command signal Cw and a read command signal Cr for the memory 32 are transmitted.

An address buffer unit 36 is connected to the address bit terminals B0 to B7 provided in the data block processing unit 35, and the address buffer unit 36 has eight address bit terminals b0 to b7 on its output side. Address data Db, which is 8-bit code data based on the address data DB supplied from the address bit terminals B0 to B7 of the data block processing unit 35, at the address bit terminals b0 to b7.
Are generated as sequentially representing addresses 0 to 255.

An address counter 37 for supplying address data to the memory 32 is provided separately from the data block processing unit 35 and the address buffer unit 36. The address counter 37 has eight address bit terminals a0 at its output side. ~
a7, operates in response to a clock pulse signal Cp synchronized with the synchronization signal Ss sent from the timing signal forming unit 39, and outputs address data converted into 8-bit code data to address bit terminals a0 to a7. Da and address 0
255 is generated as a sequential representation.

Address bit terminals b0 to b7 provided in the address buffer unit 36 are connected to selection contacts P in each of the eight switches T0 to T7 forming the switching unit 38.
Address bit terminal a0 provided in the address counter 37
To a7 are connected to the selection contact Q in each of the switches T0 to T7, and the movable contacts of each of the switches T0 to T7 are connected to eight address bit terminals A0 to A7 provided in the memory 32. I have. The switch control signal Cs sent from the data block processing unit 35 is supplied to the switching unit 38 formed by the switches T0 to T7.
When the switch control signal Cs assumes a high level, the respective movable contacts of the switches T0 to T7 are connected to the selection contact P, and when the switch control signal Cs assumes a low level, the switches Each of the movable contacts T0 to T7 is connected to the selection contact Q.

Address bit terminals b0 to b7 provided in the address buffer unit 36, and selection contacts P in each of the switches T0 to T7.
Is connected to the address bit terminals b0, b1, b2, b3, b4, b5, b6 and b7 provided in the address buffer unit 36, and the switches T0, T1, T4, T5, T2, T3, T6 and Each selection contact P of T7
The connection between the address bit terminals a0 to a7 provided in the address counter 37 and the selection contacts Q in each of the switches T0 to T7 is performed by an address bit terminal a0 provided in the address counter 37. , a1, a
2, a3, a4, a5, a6 and a7 are switches T0, T1, T2, T3, T
4, T5, T6, and T7 are made in a manner corresponding to each of the selection contacts Q. Further, the connection between each movable contact of the switches T0 to T7 and the address bit terminals A0 to A7 provided in the memory 32 is performed by a switch. T0, T1, T2, T3, T4, T5, T6 and T7 are configured in a manner corresponding to the address bit terminals A0, A1, A2, A3, A4, A5, A6 and A7, respectively. By making such a connection, as shown in FIG. 2, with respect to the address bit terminals A0 to A7 provided in the memory 32, the address bit terminals a0 and a0 provided in the address counter 37 are provided. a1, a2, a3, a4, a5, a6, and a7 are address bit terminals b0, b1, b provided in the address buffer unit 36, respectively.
4, b5, b2, b3, b6, and b7.

The write command signal Cw and the read command signal Cr sent from the data block processing unit 35 are selectively supplied to the memory 32 as appropriate.

Under the circumstances, when the discrete image data Dv representing one screen obtained from the A / D conversion unit 31 is stored in the memory 32, the switch control signal Cs from the data block processing unit 35 takes a low level. It is assumed that the switching unit 38
As a result, each of the movable contacts of the switches T0 to T7 is connected to the selection contact Q, and the address bit terminals a0, a1, a2, a3, a4, a5, a6 and
a7, via switches T0 to T7, address bit terminals A0, A1, A2, A3, A4, A5, A6 and A7 provided in the memory 32, respectively.
And the address data Da obtained at the address bit terminals a0 to a7 of the address counter 37,
The memory 32 is supplied with the write address data as write address data, and the write command signal Cw is supplied to the memory 32 so that the memory 32 is set in a writable state. In such a state, the address bit terminals A0 to A7 in the memory 32
Is sequentially represented as addresses 0 to 255, and each pixel data unit representing each of 16 × 16 = 256 pixels constituting the discrete image data Dv from the A / D conversion unit 31 is Are sequentially written to the position specified by the address data Da in the memory 32,
When all pixel data units constituting the discrete image data Dv are written, discrete image data Dv representing one screen is formed at a position corresponding to addresses 0 to 255 in the memory 32 as shown in FIG. 3A. Each of the 256 pixel data units is stored.

Subsequently, in this manner, the discrete image data Dv representing one screen written in the memory 32 is read out in units of data blocks corresponding to an image block of 4 pixels in the horizontal direction and 4 pixels in the vertical direction, When fetched into the data block processing unit 35 via the data buffer unit 34, the data block processing unit 35 sends the switch control signal Cs
Is set to a high level and supplied to the switching section 38. As a result, each movable contact of the switches T0 to T7 is connected to the selection contact P, and the address bit terminal b0 provided in the address buffer section 36 is provided. , b1, b4, b5, b2, b3, b6 and b7
Are connected to the address bit terminals A0, A1, A2, A3, A4, A5, A6, and A7 provided in the memory 32 via the switches T0 to T7, respectively. Address data Db obtained in b0 to b7 is
In a state where the memory 32 is supplied as read address data, a read command signal Cr is supplied to the memory 32, and the memory 32 is brought into a readable state. Then, 256 pixel data units forming the discrete image data Dv stored at the positions corresponding to the addresses 0 to 255 in the memory 32 are read by the address data Db supplied to the address bit terminals A0 to A7 in the memory 32. The data is read out according to the position designation, but under such a condition, the address data supplied to the address bit terminals A0 to A7 in the memory 32 are read.
Db does not represent the addresses 0 to 255 in the memory 32 sequentially, but represents each of the addresses 0 to 255 in the order shown by the number in [] in FIG. 3B. First, addresses forming a first address block composed of 16 addresses of addresses 0 to 3, 16 to 19, 32 to 35, and 48 to 51 in the memory 32 are sequentially represented, and then the addresses following the first address block are represented. The 16 addresses forming the second address block are sequentially expressed, and similarly, the 16 addresses forming each of the third and subsequent address blocks are sequentially expressed. Therefore, the discrete image data Dv stored at the position corresponding to the addresses 0 to 255 in the memory 32 is formed by 256
The pixel data units are read out in units of data blocks formed by 16 pixel data units corresponding to an image block of 4 pixels in the horizontal direction and 4 pixels in the vertical direction. The reading order of each pixel data unit from 32 will be as shown by the number in [] in FIG. 3B. First, the data block unit representing the first image block is formed. Addresses 0 to 3,16 to 19,32 to 3 in the memory 32
The 16 pixel data units stored at the positions corresponding to 5 and 48 to 51 are read out in the order of Nos. 1 to 16, and represent the second image block following the first image block. The 16 pixel data units forming the data block unit are read in the order of Nos. 17 to 32, and similarly, the data block units representing the third and subsequent image blocks are sequentially read out.

Then, a total of 16 data block units read from the memory 32 are sequentially taken into the data block processing unit 35 via the data buffer unit 34, and the data blocks of the discrete image data Dv in the data block processing unit 35 are read. Provided for processing.

Further, discrete image data Dv ′ obtained by performing data block processing on the discrete image data Dv is stored in the data buffer unit 34.
Is written to the memory 32 through the switch control signal Cs from the data block processing unit 35, which is assumed to have a high level and is supplied to the switching unit 38.
Each movable contact of the switches T0 to T7 is connected to the selection contact P, and the address bit terminals b0, b1, b4, b5, b2, b3, b6 and b7 provided in the address buffer unit 36 are connected to the switches T0 to T7.
Respectively, and connected to the address bit terminals A0, A1, A2, A3, A4, A5, A6 and A7 provided in the memory 32, respectively.
Address bit terminals b0 to b0 in the address buffer unit 36
While the address data Db obtained in b7 is supplied to the memory 32 as write address data,
The write command signal Cw is supplied to the memory 32, and the memory 32 is set in a writable state. Then, the data block processing unit 35
Is supplied to the memory 32 via the data buffer unit 34, and the discrete image data Dv '
v ′, 256 pixel data units, which are assumed to constitute 16 data block units, are written in accordance with the write position specified by the address data Db supplied to the address bit terminals A0 to A7 in the memory 32. Is written to a position corresponding to addresses 0 to 255 in the memory 32,
Under such circumstances, the address bit terminal in the memory 32
The address data Db supplied to A0 to A7 does not sequentially represent addresses 0 to 255 in the memory 32,
Addresses 0 to 255 are represented in the order shown by the numbers in brackets [] in FIG. 3B. First, addresses 0 to 3, 16 to
Addresses forming a first address block consisting of 16 addresses 19, 32 to 35 and 48 to 51 are sequentially shown, and then 16 addresses forming a second address block following the first address block are sequentially shown. Hereinafter, similarly, 16 addresses forming each of the third and subsequent address blocks are sequentially represented. Accordingly, the writing order of each of the pixel data units divided into the 16 data block units forming the discrete image data Dv 'in the memory 32 is as shown by the numbers in [] in FIG. 3B. First, 16 pixel data units forming a data block unit representing an image block of 4 pixels in the first horizontal direction and 4 pixels in the vertical direction are stored in the memory 32 at addresses 0 to 3, 16 to 19, 32. The 16 pixel data which are written in the positions corresponding to Nos. 35 and 48 to 51 in the order of Nos. 1 to 16, and then form a data block unit representing the second image block following the first image block The units are written in the order of Nos. 17 to 32, and similarly, data block units representing the third and subsequent image blocks are sequentially written.

Further, when the discrete image data Dv ′ subjected to the data block processing is read from the memory 32 and supplied to the D / A conversion unit 33, the switch control signal Cs from the data block processing unit 35 is set to a low level. Are supplied to the switching unit 38, and as a result, the respective movable contacts of the switches T0 to T7 are connected to the selection contact Q, and the address bit terminals a0, a1, a2, and a3,
a4, a5, a6, and a7 are connected to the address bit terminals A0, A1, A2, A3, A provided in the memory 32 via the switches T0 to T7, respectively.
4, address counter 3 connected to A5, A6 and A7
7, the address data Da obtained at the address bit terminals a0 to a7 is supplied to the memory 32 as read address data, and the read command signal Cr is supplied to the memory 32 so that the memory 32 can be read. It is said. In such a state, the address data Da supplied to the address bit terminals A0 to A7 in the memory 32 sequentially represent the addresses 0 to 255, and the discrete data stored at the positions corresponding to the addresses 0 to 255 in the memory 32. The 256 pixel data units forming the image data Dv ′ are divided according to the read position specified by the address data Da.
The addresses are read in the order of addresses 0 to 255 in the memory 32 and supplied to the D / A converter 33.

As described above, in the example shown in FIG.
Discrete image data representing one screen obtained from the conversion unit 31
When Dv is stored in the memory 32, and when the discrete image data Dv ′ subjected to the data block processing is read out from the memory 32 and supplied to the D / A conversion unit 33, Address bit terminal of the address counter 37
Address data Da obtained at a0 to a7 are supplied as write address data and read address data, and discrete image data Dv representing one screen written in the memory 32 is divided into four pixels in the horizontal direction and four pixels in the vertical direction. When the data is read out in units of data blocks corresponding to an image block of four pixels in the direction and taken into the data block processing unit 35 via the data buffer unit 34, and the data block processing unit 35
The discrete image data Dv ′ obtained by performing the data block processing on the discrete image data Dv in
When data is written to the memory 32 via the address buffer 34, the address data Db obtained at the address bit terminals b0 to b7 in the address buffer unit 36 are supplied as write address data and read address data.

In the above example, each screen of the image signal Sv is
Pixels are sampled so that 16 pixels are obtained in the vertical direction as well, and discrete image data Dv is formed, which is stored in the memory 32 and a discrete image for one screen stored in the memory 32 The data Dv is read out in units of data blocks corresponding to an image block of 4 pixels in the horizontal direction and 4 pixels in the vertical direction, and is subjected to data block processing for discrete image data in the data block processing unit 35. However, the image data processing device according to the present invention is not limited to such an example,
In general, discrete image data is formed by sampling each image signal of one screen so that ^2K pixels are obtained in the horizontal direction and J · ^2M pixels are obtained in the vertical direction. with J · 2 ^M · 2 ^K pieces of pixel data units forming are stored in the memory corresponding to the memory 32 which is assumed to have a capacity to accommodate the J · 2 ^M · 2 ^K pixels data, discrete image data of one frame stored in the memory, is read by one data block unit corresponding to the image blocks of 2 ^M pixels in the vertical direction by 2 ^M pixels in the horizontal direction, the block processing of the discrete image data To be offered to the public.

FIG. 4A shows a discrete image data which is formed by sampling each image of the image signal so that ^2K pixels are obtained in the horizontal direction and J · ^2M pixels are obtained in the vertical direction.・ 2 ^M・ 2 ^K pixel data units are 0 to
J · 2 ^M · 2 ^K indicates a state where it is stored into the address position -1, FIG. 4 B is, J · 2 ^M · 2 ^K number of discrete image data of one frame stored in the memory to form The pixel data unit is
This figure shows a state in which data blocks are read out in units of data blocks corresponding to an image block of 2 ^N pixels in the horizontal direction and 2 ^M pixels in the vertical direction.

Under such circumstances, the data block processing unit corresponding to the data block processing unit 35 has M + K + I address bit terminals B0 to B [M + K + I-1] connected to the built-in address data forming unit. , M + K + I bit code data, and the address buffer corresponding to the address buffer 36 has M + K + I address bit terminals b0 to b [M + K + I-1] on its output side. Address data, which is M + K + I bit code data, is applied to address bit terminals b0 to b [M + K + I-1].
+ K + I-1 are sequentially generated, and an address counter corresponding to the address counter 37 has M + K + I address bit terminals a0 to a [M + K + I-1] on its output side. Address data, which is M + K + I bit code data, is applied to terminals a0 to a [M + K + I-1].
To M + K + I-1 are sequentially generated. The memory corresponding to the memory 32 is M
+ K + I address bit terminals A0 to A [M + K + I-
1], and in relation to address bit terminals A0 to A [M + K + I-1] in such a memory, as shown in FIG. 5, address bit terminals a0 to a [ N-1] and address bit terminals b0 to b in the address buffer unit.
[N-1] correspond to the address bit terminals a [N] to a [N + M-1] in the address counter and the address bit terminals b [N +] in the address buffer unit.
M] to b [M + K−1] respectively correspond to address bit terminals a [N + M] to a [M
+ K-1] and address bit terminals b [N] to b [N + M-1] in the address buffer unit, respectively, and furthermore, an address bit terminal a in the address counter.
[M + K] to a [M + K + I-1] and address bit terminals b [M + K] to b [M +
K + I-1].

As it is clear from the description effect over the H invention, according to the image data processing apparatus according to the present invention, J · 2 ^M pixels in the vertical direction together with the image signal representing one screen is obtained 2 ^K pixels in the horizontal direction The discrete image data formed by sampling as obtained is written to the memory, and the discrete image data of one screen written in the memory is equivalent to an image block of 2 ^N pixels in the horizontal direction and 2 ^M pixels in the vertical direction. In reading the data block by data block and performing block processing on the discrete image data, when the discrete image data for one screen is written to the memory, the first address data generation means for sending the write address data to the memory is used. ~
M + K + I bit terminals, which can be represented as M + K + I-1, and second address data generation for sending read address data to the memory when discrete image data for one screen is read from the memory to the data block processing unit And M + K + I bit terminals, which can be represented as 0 to M + K + I−1,
To N-1 and the other 0 to N-1 respectively correspond to one N
N + M-1 and the other N + M to M + K-1 correspond to each other, and one of N + M to M + K-1 and the other N to N + M-1
And M + K to M + K + I−
1 and the other M + K to M + K + I-1 correspond to each other, so that when the address data is sent from the first and second address data generating means, the operation on the address in the memory to be represented by them is performed. It is not required, and therefore, the address control of the memory can be performed very easily when the discrete image data for one screen written in the memory is read out in data block units for the data block processing. Block processing can be facilitated and speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an image data processing apparatus according to the present invention, and FIG. 2 shows a correspondence relationship between address bit terminals of an address counter and address bit terminals of an address buffer unit in the example shown in FIG. FIGS. 3A and 3B are diagrams for explaining the storage and retrieval of the discrete image data to and from the memory in the example shown in FIG. 1, and FIGS. FIG. 5 is a diagram provided for general description of storage and retrieval of discrete image data in and from a memory in the image data processing apparatus. FIG. 5 is a diagram showing address bit terminals of an address counter in the image data processing apparatus according to the present invention. FIG. 6 is a diagram provided for general description of the correspondence relationship between address bit terminals of an address buffer unit, and FIG. 6 shows an example of a conventional image data processing device. FIG. 7 is a block diagram, FIG. 7 is a diagram showing the correspondence between the address bit terminals of the address counter and the address bit terminals of the memory in the device shown in FIG. 6, FIGS. 8A and 8B, and FIG. FIG. 4 is a diagram provided for describing storage of a discrete image data in a memory and retrieval from the memory in the device illustrated in FIG. In the figure, 31 is an A / D converter, 32 is a memory, 33 is a D / A converter, 34
Is a data buffer unit, 35 data block processing unit, 36 is an address buffer unit, 37 is an address counter, 38 is a switching unit, and 39 is a timing signal forming unit.

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Tsutomu Yamamoto 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-60-221848 (JP, A) JP-A Sho 64-7140 (JP, A) JP-A-63-156260 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06T 1/60 G06F 12/00

Claims (1)

(57) [Claims] 1. A second image signal representing the initial screen in the horizontal direction ^K
(K is a positive integer) pixels are obtained and J ·
2. An image data supply unit for sending discrete image data formed by sampling to obtain 2 ^M (J and M are positive integers) pixels, and one screen of discrete image data sent from the image data supply unit And the discrete image data for one screen written in the memory.
A data block processing unit that reads out 2 ^N (N is a positive integer, N ≦ K) pixels in the horizontal direction and a data block unit corresponding to an image block of 2 ^M pixels in the vertical direction and performs block processing on discrete image data When one screen of discrete image data is written to the memory, the write address data for the memory is changed from 0 to M + K + I−1 (I is equal to log ₂ J or l
M + K that can be expressed as og ₂ J + 1)
The first address data generating means having + I bit terminals supplies the read address data to the memory when the discrete image data for one screen is read from the memory to the data block processing unit. Is M + K, which can be expressed as 0 to M + K + I-1.
+ I number of bit terminals are supplied from the second address data generating means, and each bit terminal of the first and second address data generating means is connected to one of 0 to N-1 by the other 0 to N −1, one N to N + M−1 corresponds to the other N + M to M + K−1, and one N + M to M + K−1 corresponds to the other N
To N + M-1 respectively, and one M +
From K to M + K + I-1 is the other M + K to M + K +
And a memory address control unit corresponding to each of I-1 and I-1.