JPS63142783A - Scan converter - Google Patents

Abstract

PURPOSE:To need only one monitor by reading out video signals, which are asynchronous with each other and different in frequency, such as a TV image that is a picked up picture and the text picture of a computer, in unified mode to the picture of a higher frequency. CONSTITUTION:An addition circuit 18 adds up together the picture signal MPS, which is switched by a switching circuit SS2 and read out from either a bank memory 17a or 17b, and a text image signal TXS from the computer 20, and transmits it to a digital/analog converter (D/A converter) 22. The D/A converter 22 converts the image signal, added up by the addition circuit 18, into the analog signal of a variable density, and outputs it to the monitor 23, which is capable of an analog-inputting. The monitor 23 displays a video output, synthesized from the picture signal of the D/A converter and the text video signal at the synchronizing frequency of an inputted text synchronizing signal TSY, on the same screen.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Field of Application> The present invention provides an advantage for displaying two systems of video signals controlled at a given synchronous frequency on the same monitor. Regarding the converter.

- <Prior Art> FIG. 5 is a block diagram showing the configuration of a conventional image display device.

The computer 10 receives character information such as a program from the keyboard 11, and displays this on the text CRT 12 as, for example, character information with one pixel being one bit.

On the other hand, the image 19 processing device 13 is, for example, an industrial television (rT).
An analog gray scale image of the object to be inspected placed on a conveyor or the like is input in real time from the camera θIR, 14 such as V), and this is processed in response to a control signal from the computer 10, for example, when one pixel is 8 bits. The data is converted into a digital value, processed, D/A converted, and output to the monitor CRT 15.

In this case, the text CRT 12 has, for example, a horizontal synchronization frequency of 26.016KI-1z and a vertical synchronization frequency of 54
．． 65! -1z, the pixel signal representing one pixel is 21.6
It is controlled by a control signal of /I 5 MHz, and the screen consists of 640 dots in the horizontal direction and 512 dots in the vertical direction.

For example, the CRT15 has a horizontal synchronous frequency of 15.7KI-1z and an I-direction synchronous frequency of 301
-1z, and the pixel frequency is controlled by a control signal of 6 MHz, resulting in a screen consisting of 320 dots in the horizontal direction and 240 dots in the vertical direction.

Therefore, the text CRT 12 and the monitor CRT 15 are independently controlled at different synchronization frequencies.

<Problems to be solved by the invention> However, in such conventional image processing devices, the synchronization frequency is different between text display and image display.
The first disadvantage is that a monitor corresponding to each is required, which increases the cost and requires extra space.

Means for Solving the Problems> In order to solve the above problems, the present invention provides a first switch means in which an image captured by an image pickup device is converted into an image signal by an image processing device and inputted; First switch hand
a first bank memory into which image signals are written from the switching end;
a second bank memory into which an image signal is written from the second switching end of the first switch means; a second switch means which switches between the image signals read from the first and second bank memories and outputs one of them; addition means for receiving and adding the text video signal whose information has been converted by the computer and the image signal output from the second switch means; and an image synchronization signal from the image processing device having a synchronization frequency different from this. A text synchronization signal from the computer is input, a first switching signal for controlling the first switching means, a second switching signal for controlling the second switching means, a first mode signal for switching the state mode of the first bank memory, and a second switching signal for controlling the first switching means. and timing control means for outputting a second mode signal for switching the state mode of the bank memory, and outputting the video output of the addition means and the text synchronization signal to a monitor so that the image signal and the text video signal can be displayed on the same screen. This is how it is displayed.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

, FIG. 1 is a block diagram showing one embodiment of the present invention.

The image processing device 16 receives an image signal IMG, which is a grayscale image of the inspection object placed on a belt conveyor or the like, captured by the image carrier 14 online, and converts this into a grayscale image using multiple bits. Converts the video to an image signal PIG and outputs it, and also outputs an image synchronization signal @P from the imaging signal IMG.
SY (horizontal synchronization fg No. 1-I SY 1, vertical in
The same III signal vSY1 and a pixel signal PXL1 representing one pixel are separated and output.

17a and 117b are bank memories, and these two function as one memory. bank memory 1
7a, the image signal PIG is at the -th switching end a of the switch SW1.
The image signal PIG is input to the bank memory 17b via the second switching terminal of the switch SW+. Furthermore, bank memory 17a and bank memory 1
The image signals PIG stored in 7b are respectively connected to switches S.
The signal is switched from either the -th switching end a or the second switching end of W2 and read out to the adding circuit 18.

Text such as a program is input to the computer 20 from the keyboard 19, and the computer 20 inputs the text 1111 ¥3TSY (horizontal synchronization signal H8Y2, vertical synchronization signal VSY2, and pixel signal px representing one pixel).
L2> is outputted to the timing control circuit 21, and the text video signal TXS is outputted to the addition circuit 18.

The timing control circuit 21 receives an image synchronization signal PSY synchronized with the image signal PIG and a text synchronization signal TSY synchronized with the text video signal TXS from the image processing device 16, and uses them to input a mode signal MDA1 bank into the bank memory 17a. A mode signal MDB is output to the memory 17b, a switching signal S81 is output to the switch SW+, and a switching signal SS2 is output to the switch SW2.

To the mode signal MD, MDB is the bank memory 17a, 17
b is the write mode W (Wr
ite), read mode R (Read) by text synchronization signal TSY, or preparation mode R/R (Read-Ready) up to read mode, and preparation mode W/R (Write-Ready) up to write mode.
).

The switching signal SS1 transfers the image signal PIG to the bank memory 17a.
, 17b to which to write, and the switching signal SS2
controls which of the image signals written in the bank memory 17a or 17b is read out.

The adder circuit 18 adds the picture 11 signal MPS read out from either the bank memory 17a or 17b by the switching signal 882 and the text 1-picture fiHFi signal TXS from the computer 20, and performs digital/analog conversion. 1g4 device <D/A converter) 22. Incidentally, the addition/stopping circuit 18 also has a priority function of giving priority to the text video signal @rxss between the image signal @MPS and the text video signal T.sub.XS.

The D/A converter 22 converts the video signal added by the addition circuit 1B into a gray-scale analog signal and outputs it to a monitor 23 capable of analog input.

The monitor 23 displays on the same screen a video output obtained by combining the image signal of the D/A converter 22 and the text video signal at the synchronization frequency of the input text synchronization signal TSY.

Among these, the bank memory 17a117b1 addition circuit 18, timing control circuit 21.0/A converter 22, switches SW+, S'll'/2, etc. constitute the scan converter 24.

Next, the operation of the scan converter developed as described above will be explained using FIGS. 2 to 4.

FIG. 2 is a mode state diagram showing the relationship between the mode signal output from the timing control circuit 21 and the switching signal.

In the state of mode L, the switch SW+ is switched to the bank memory 17a side by the switching signal 881, and the switch S
W2 is switched to the bank memory 17b side. The bank memory 17a is in a write and read preparation state, mode 1 is write preparation W/R, mode 1 is write W, mode 1 is read read preparation R/R. On the other hand, the bank memory 17b is in the read R mode.

In the states of modes N to ■, the switch S W + is switched to the bank memory 17b side by the switching signal SS2.
W2 are respectively cut out on the bank memory 17a side. The bank memory 17a is in the read R mode in both modes N to Z. The bank memory 17b is in the state of preparation for writing and reading, and the mode W is write Q-preparation W/
R, mode V is in write W mode, and mode leaf is in read preparation R/R mode.

The timing R11 control circuit 21 selects these modes using the mode signals MDA, MD[3 and the switching signal ssi.
, with s$2, the transition is made as follows: engineering → 2 → engineering.

Next, FIG. 3 shows a specific configuration of a timing control circuit that satisfies the transition conditions shown in FIG. 2.

25 is a counter, which in this case is composed of 3 bits. Pulse signals for creating mode signals and switching signals are generated at the outputs INQo-Q2. This is input to the decoder 26 and decoded into mode signals MDA and MOB and switching signals SS1 and SS2.

The outputs of the counters 25 are input to gates E to N that determine each mode L5, respectively. The outputs of gates G to M are output to OR gate G+, and gate group Gu is output to OR gate G.
The respective outputs of 1 and gate -, as well as the image synchronization signal PSY and text synchronization signal @TSY are inputted, and these are AND-ORed and outputted to the counter 25. Further, the output of the gate 2 is applied to the clear terminal CL of the counter 25,
Clear the contents of the counter 25. FIG. 4 is a timing diagram showing the timing controlled by the timing control circuit 21.

FIG. 4(A) is a waveform showing the timing waveform of the text synchronization signal TSY, FIG. 4(B) is a waveform showing the timing of the image synchronization signal PSY, and FIG. 4(D) shows a state in which the symbols .about.■ appear one after another. FIG. 4(D) shows a state in which bank memory 17a is written or read. FIG.
7b, the state showing the write or read state, FIG.
) is the image signal M read out from switch SW2.
PS, FIG. 4(g) shows states corresponding to the mode states showing each mode shown in FIG. 2, respectively.

The image signal PIG shown in Fig. 4 (c) is generated by the rising edge of every other pulse of the image synchronization signal PSY (Fig. 4 (b)).
Every other image, for example, images ■, ■, ■ are written alternately to the bank memories 17a and 17b.

On the other hand, the image ■ stored in the bank memories 17a and 17b
, ■, ■ (Fig. 4 (D) and (H)) are read out alternately from the bank memories 17a and 17b by every other rising edge of the text II signal TSY (Fig. 4 (A)). The signal is read out to the adder circuit 18 as an image signal MPS shown in FIG.

As described above, the image signal PIG outputted from the image processing device 16 is sent to the adder circuit 1 for every other image among images ■ to ■.
However, since the image signal IMG originally imaged by the image pickup 114 is a signal obtained when the object to be inspected is stationary, for example, on a conveyor, every other image signal PEG is read out. The image is not damaged when read out.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, video signals of different frequencies and asynchronous to each other, such as a TV image such as an imaging screen and a computer text screen, are transferred to a high-frequency screen. Since it is now possible to uniformly read out images on both sides and display them on the same monitor, only one monitor is required, reducing costs and improving the space factor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a mode diagram showing the mode states of the timing control circuit shown in FIG. 1, and FIG. 3 is the timing shown in FIG. 1. FIG. 4 is a timing diagram showing the timing controlled by the polytiming control circuit in FIG. 1, and FIG. 5 is a block diagram showing the configuration of a conventional image display device. 10.20...Computer, 12...Text C
RT, 13.16... Image processing device, 15... Monitor CRT, 17a, 17 b-... Bank memory, 1
8... Addition circuit, 21... Timing control circuit, 2
3...Monitor, 24...Scan converter, 25
...Counter, [MG...11 signal, PSY...Image synchronization signal, PIG, MPS...Image signal, TSY...
...Text synchronization signal, TXS...Text video @ signal, MDA, MDE3...Mode signal, SS1. SS2
...Switching signal. 'Figure 2

Claims (1)

[Claims] a first switch means into which an image captured by the image pickup device is converted into an image signal by an image processing device and input; a first bank memory into which the image signal is written from a first switching end of the first switch means; a second bank memory into which the image signal is written from a second switching end of the first switch means; and a second switch means which switches between the image signals read from the first and second bank memories and outputs one of them. , an addition means for receiving and adding together a text video signal whose input information is converted by a computer and an image signal output from the second switch means; and an image synchronization signal from the image processing device, which is different from the above. A text synchronization signal from the computer having a synchronization frequency is input, a first switching signal for controlling the first switching means, a second switching signal for controlling the second switching means, and a state mode of the first bank memory. and timing control means for outputting a first mode signal for switching and a second mode signal for switching the state mode of the second bank memory, and outputting the video output of the adding means and the text synchronization signal to a monitor. A scan converter that displays the image signal and the text video signal on the same screen.