JPS62153894A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention displays an image stored in a frame memory on a raspberry-type display, and displays a figure output from a graphic display controller on it. The present invention relates to an improvement of an image display device that displays images in a superimposed manner.

(Prior Art) In the image display device of this scale, the read clock of the frame memory is the same as that of the display screen -F.
It is determined in accordance with the raster skillen horizontal scanning time so that the a ratio is 1:1. On the other hand, the output of the graphic display controller is written to one overlay memory, and the contents of this overlay memory are, for example, 16
:1 parallel-to-serial conversion and output,
The read clock of the overlay memory is determined according to the number of parallel-to-serial conversion stages and the horizontal scanning time. Therefore, the frame memory and overlay memory have different read clock frequencies.

(Problem that fI Ming attempts to solve) If the read clock frequencies of the frame memory and A-barley memory differ, the respective pixel sizes when displaying an image on a display device will differ. For this reason, the aspect ratio of the A-barley image is not 1:1, and for example, even if an attempt is made to draw a perfect circle, a circle drawing command cannot be used. In addition, the calculation of the coordinate transformation between the frame image and the overlay figure becomes complicated, and errors inevitably occur.Furthermore, the NTSC system and PAL
In this method, it is difficult to make the frequency ratio of the read clocks of the frame memory and the overlay memory the same, so the specifications of the overlay screen cannot be unified.

The present invention was made in view of these conventional problems, and its purpose is to solve the above problems by making the pixel size of the frame memory image and the pixel size of the overlay figure the same. An object of the present invention is to provide an image display device.

(Means for Solving the Problems) The present invention, which solves the above problems, includes a frame memory that stores image data, and a frame memory that generates a read clock for the frame memory based on a horizontal synchronization signal.
a clock circuit, a composite video signal creation circuit that receives frame memory read data and creates a composite video signal, a display that displays an image based on the output signal of the composite video signal creation circuit, and a display that displays an image on the display. A graphic display controller that generates a signal representing a figure to be displayed superimposed on the image in the frame memory, an overlay memory that stores the output signal of the graphic display controller, and a parallel-serial controller that converts the read data of the overlay memory from parallel to serial. In an image display device that connects the converter and an overlay clock circuit that generates a clock for the parallel-to-serial converter based on a horizontal synchronization signal, the output signal of the parallel-to-serial converter is read out and read out. The horizontal scanning memory is fed to the composite video signal creation circuit, and the writing to the horizontal scanning memory is performed according to the clock of the overlay clock circuit.
The present invention is characterized in that it includes a read address generation circuit that controls reading of the horizontal scanning memory according to the clock of the frame memory clock circuit and the m address generation circuit that performs +*U.

(Example) An example of the present invention is shown in FIG. In FIG. 1, 1 is a synchronization signal generator, which generates a horizontal synchronization signal and a vertical synchronization signal, and 2 is a DSC clock generation circuit, which generates a frame memory 3 based on the horizontal synchronization signal of the Domei signal generator 1. Generates a DSC clock for reading. Note that DSC is an abbreviation for digital scan converter. Image data (hereinafter referred to as DSC data) read out from the frame memory 3 in accordance with the DSC clock is converted into a composite video signal by a composite video signal generation circuit 4, and is applied to a display device 5 (CRT) to be displayed as an image. Note that data for an image to be displayed is written into the frame memory 3 by means not shown.

6 is a graphic display controller (hereinafter referred to as G
DC), which generates a signal representing a figure to be displayed superimposed on the image displayed on display 'FA5. The graphical signal to be generated is specified by means not shown. The output signal of the GDC 6 is written into an overlay memory 7, and the signal read from the overlay memory 7 is converted into a serial signal by a parallel/serial conversion circuit 8 and output. GDC6゜A
- Burley memory 7 and parallel/serial conversion circuit 8
The clock for the operation is given from the overlay clock generation circuit 9. The clock of this overlay clock circuit 9 is generally generated at a frequency different from the clock of the raw circuit 2 by the DSC clock based on the horizontal synchronization signal of the synchronization signal generator 1.

Reference numerals 10 and 11 are a pair of horizontal scanning memories (hereinafter referred to as memories), which are used by being switched alternately for each horizontal scan.Switching is performed by switches on the input side and readout side, respectively. 12 and 13 by the signal of the 1H memory switching signal generator 14.1H
The m write address of the memories 10 and 11 is given by the 11-1 memory write address generator 15 according to the clock of the overlay clock generation circuit 9, and the read address is given by the 1H memory read address generator 16 according to the DSC clock generation circuit. It is given according to the clock of circuit 2. When one of the one-day memories io and i1 is loaded, the other is read out. 1 memory 10.
The overlay data read from 11 is given to composite video signal creation circuit 4. If the overlay clock frequency is always higher than the DSC clock frequency, use a single dual-port memory as the 1H memory, load the overlay data from one boat according to the A-barley clock, and load the overlay data from the other boat. The overlay data may be read out according to the DSC clock.

In that case, the changeover switches 12, 13 and the 1H memory changeover signal generator 14 become unnecessary.

In such a configuration, forwarding and reading of overlay data of the daily memories io and ii, and D of the frame memory 3
FIG. 2 shows the relationship with SC data reading. When horizontal scanning line 1 is scanned (second same on the left), overlay data is loaded into one of the daily memories 10 and 11 according to the overlay clock. At this time, the previously written overlay data of the scanning line O is read out from the other side according to the same DSC clock as that used for reading out the frame memory 3. When scanning is switched to scanning line 2 (second on the right), overlay data written during scanning line 1 is read out in accordance with the same DSC clock as that used for reading frame memory 3.

In this way, the overlay data of the 1H memory 10.11 is read out using the same DSC clock as that of the frame memory 3, so that the read overlay data has the same pixel size as the DSC data.

Therefore, the aspect ratio on the display screen is 1:1, and the coordinates on the display screen are the same. Also, NTSC system and P
The use of overlay screens can be made common to both AL/SECAM systems.

(Effects of the Invention) As described above, according to the present invention, by making the pixel size of the image in the frame memory and the pixel size of the figure in the overlay memory the same, an image display device that solves the conventional problems can be realized. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of the embodiment of the present invention. 1... Synchronization signal generator 2... DSG clock generation circuit 3... Frame memory 4... Composite video signal creation circuit 5... Display unit 6... Graphic display controller 7.
...Overlay memory 8...Parallel/serial conversion circuit 9...Overlay clock generation circuit 10.11...
・11" memory 12.13... changeover switch

Claims (1)

[Claims] A frame memory that stores image data, a frame memory clock circuit that generates a read clock for the frame memory based on a horizontal synchronization signal, and a composite video signal creation circuit that receives frame memory read data and creates a composite video signal. a display device that displays an image based on the output signal of the composite video signal generation circuit; a graphic display controller that generates a signal representing a figure to be displayed superimposed on the image in the frame memory displayed on the display device; an overlay memory that stores output signals of the display controller; a parallel-to-serial converter that converts read data from the overlay memory from parallel to serial;
In an image display device having an overlay clock circuit that generates a clock for a parallel-to-serial converter based on a horizontal synchronization signal, an output signal of the parallel-to-serial converter is written and a readout output is provided to a composite video signal creation circuit. The horizontal scanning memory includes a write address generation circuit that controls writing to the horizontal scanning memory according to a clock of an overlay clock circuit, and a read address generation circuit that controls reading of the horizontal scanning memory according to a clock of a frame memory clock circuit. Characteristic image display device.