JP2793474B2 - Partial write control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a partial write control circuit in a storage device.

[0002]

2. Description of the Related Art Referring to FIG. 2 showing an example of a partial write control circuit of this type, the circuit first comprises an input terminal
Write data, a write mask, an address, and a command are received from the processor from the processors 1, 102, 103, and 104, respectively, and input to the write data register 1, the write mask register 2, the address register 3, and the command register 4, respectively. A command is sent from the command register 4 to the control circuit 11 '. When the command is a partial write, the control circuit 11' sends a read command to the storage unit 13 and sends a control signal to the write data control unit 7, The write data control unit 7 includes the write mask register 2
Receive light mask from and set. The control circuit 11 ′ also sends a control signal to the address control unit 22 to receive an address from the address register 3 and transfer it to the storage unit 13.

The storage section 13 reads data based on the read command and address sent thereto, and is set in a read data register 18 via an error detection / correction circuit 16. The read data set in the read data register 18 is sent to the write data selector 6, and the write data selector 6 receives the write data set in the write data register 1 and the write mask sent to the write data control unit 7. , Partial writing is performed.
The partial write data generated by the write data selector 6 is written to the storage unit 13 via the check bit generation circuit 12.

[0004]

In the above-described conventional partial write control circuit, when performing partial write, the data at the address is read once, the check bits are generated again after merging with the write data, and then the write is performed. Because of this, there is a drawback that the execution time is longer by the read time than in the case of full write.

An object of the present invention is to provide a partial write control circuit that improves the performance of a storage device by making the execution time of partial write the same as that of full write.

[0006]

A partial write control circuit according to the present invention sets a write data, a write mask, and an address in a buffer until a predetermined number is reached when a partial write command is issued, and stores the write data, write mask, and address in a buffer. A control circuit that does not perform writing, an address comparison circuit that compares whether or not the same address is set in the buffer when a read command is issued, and an address that matches the comparison result, A read data control unit that reads write data to be read from the buffer and reads data from the storage unit when there is no matching address; and when the data in the buffer reaches the fixed number, the read data control unit Refresh / patrol control for controlling data to be written in the storage unit by reducing data in the storage unit If, when the buffer even by reducing the data in the process is full clears the previous data in the buffer, and having a buffer management unit for partial write in the storage unit all.

[0007]

FIG. 1 shows an embodiment of the present invention.
This embodiment is different from the conventional example shown in FIG. 2 in that the refresh / patrol control circuit 5, the write data buffer 8,
While a write mask buffer 9, an address table 10, an address selector 14, a timing control circuit 15, an address comparison circuit 17, a buffer management unit 19, a read data control unit 20, and a read data selector 21 are added, the address control circuit in FIG. 22 is removed, and the control circuit 11 is provided instead of the control circuit 11 '. 2 and 1 are denoted by the same reference numerals.

In FIG. 1, input terminals 101, 102,
Write data, a write mask, an address, and a command are received from the processors 103 and 104, respectively, and input to the write data register 1, the write mask register 2, the address register 3, and the command register 4, respectively. When the command is a partial write, the control circuit 11 sets an address, write data, and a write mask from these registers in the address table 10, the write data buffer 8, and the write mask buffer 9, and writes to the storage unit 13 Do not do.

When the command is read, a control signal is output from the control circuit 11 to the address comparison circuit 17. The address comparison circuit 17 refers to the address table 10 to check whether the read address set in the address register 3 is an address for which partial writing has been performed previously.
If there is a matching address, this is notified to the read data control unit 20, and the read data control unit 20 inputs the corresponding write mask for partial writing from the write mask buffer 9 and outputs it to the read data selector 21. I do.

The control circuit 11 also includes an address register 3
Is output to the storage unit 13 via the address selector 14 and a control signal for causing the timing control circuit 15 to output a timing signal for performing a read operation to the storage unit 13. With this result,
The read data read from the storage unit 13 is used for error detection /
The data is input to the read data register 18 via the correction circuit 16. The read data selector 21 generates partially written data from the output of the read data register 18 and the output of the write data buffer 8 based on the mask data from the read data control unit 20, and sends the data to the processor via the output terminal 201. .

However, when the number of partial write operations increases, the address table 10, write mask buffer 9
In addition, the write data buffer 8 becomes full, and it becomes impossible to set the address, the write mask, and the write data in these buffers. To prevent this,
When the number of addresses set in the address table 10 reaches a predetermined fixed number (detected by the control circuit 11), the refresh / patrol control unit 5
1 to directly and indirectly control the timing control circuit 15, the address selector 14, the read data control unit 20, the read data selector 21, the mask control unit 7, and the write data selector 6, respectively. The data for partial writing is generated from the data of 8, 9, and 10 and the storage unit 13, and is written to the storage unit 13 to reduce the number of data set in each buffer.

When each buffer becomes full even if the data is reduced by the above method, the buffer management unit 19 detects this and issues an interrupt signal to the processor from the output terminal 202 to suppress the memory access for a certain period of time. I do. The timing control circuit 15, the address selector 14, the read data control unit 20, the read data selector 21, the mask control unit 7, and the write data selector 6 are controlled by the output from the buffer management unit 19 via the control circuit 11 to control each buffer. All data is transferred to the storage unit 13, and the number of data set in each buffer is set to zero.

[0013]

As described above, according to the present invention, the execution time of the partial writing can be shortened with a relatively small increase in the amount of hardware, so that the effect of greatly improving the performance of the information processing apparatus can be obtained. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a partial write control circuit of the present invention.

FIG. 2 shows an example of a conventional partial write control circuit.

[Explanation of symbols]

 1 Write Data Register 2 Write Mask Register 3 Address Register 4 Command Register 5 Refresh / Patrol Control Unit 6 Write Data Selector 7 Write Data Control Unit 8 Write Data Buffer 9 Write Mask Buffer 10 Address Table 11 (11 ′) Control Circuit 12 Check Bit Generation circuit 13 Storage unit 14 Address selector 15 Timing control circuit 16 Error detection / correction circuit 17 Address comparison circuit 18 Read data register 19 Buffer management unit 20 Read data control unit 21 Read data selector 22 Address control unit 101 to 104 Input terminal 201 202 output terminal

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shin Yamauchi 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation (72) Inventor Hiroshi Kikuchi 1088-3 Otsucho, Kofu City, Yamanashi Prefecture Kofu Nippon Electric Co., Ltd. In-house (56) References JP-A-53-145428 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 11/40-11/409 G06F 12/04 520

Claims (2)

(57) [Claims] A control circuit that sets write data, a write mask, and an address in a buffer and does not perform a partial write to a storage unit until a predetermined number is reached when a partial write command is issued; An address comparison circuit for comparing whether or not the same address is set in the buffer; and if there is an address that matches the comparison result, the corresponding write data is read from the buffer and the matching address is determined. A read data control unit that reads data from the storage unit when there is no data, and when the data in the buffer reaches the fixed number, reduces the data in the buffer at a predetermined time and performs a partial write to the storage unit. A refresh / patrol control unit for controlling the operation to be performed; If § is full clears the previous data in the buffer, partial write control circuit in the storage device characterized by having a buffer management unit for partial write in the storage unit all. 2. The partial write control circuit according to claim 1, wherein the predetermined time is set immediately after refreshing or when the storage device is not operating.