JP2913873B2 - Data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system having an error detecting and correcting function, and is particularly effective in a small computer system such as a personal computer and a workstation, particularly when it is used for a main memory system which requires high speed. It relates to a memory control method.

[0002]

2. Description of the Related Art In a memory system having an error detecting and correcting function for memory contents, a known example of a conventional memory control technique for shortening a read cycle time is disclosed in Japanese Patent Publication No. 57-46158. No. Conventionally, as a means for realizing burst reading, the high-speed access mode of the memory is not used, or the high-speed access mode is terminated when an error occurs, or even if the high-speed access mode is used, error detection and correction can be performed for each data. In this case, a method is provided for facilitating error correction, such as giving a margin to the timing.

[0003]

In the conventional method, when applied to burst reading, error detection and correction are processed for each data. Therefore, reading for the next data is performed until the error determination result of the current data is known. Processing cannot be started, and the high-speed access mode of the memory element cannot be used effectively.

An object of the present invention is to provide a memory control system capable of performing high-speed burst reading by effectively utilizing a high-speed access mode of a memory element in a memory system having an error correction function.

[0005]

In order to achieve the above object, the present invention interrupts the transmission of a processing end signal when a correctable error is detected during burst reading of a memory using a high-speed access mode. In comparison with the conventional method of detecting and correcting errors for each data, by performing burst correction processing for the specified data and performing correction processing and restarting transmission of the processing end signal, error detection and correction are performed for each data. Is a simple and high-speed burst reading. According to the present invention, the reading of the next data can be started without waiting for the result of the error detection for the current data, so that a high-speed burst reading sequence optimized for the high-speed access mode of the memory element can be performed in one It is possible to design a memory control circuit that starts as a constituent unit.

[0006]

The point of view of the present invention is to correct an error with a low probability of occurrence as a process after the end of burst reading of prescribed data, optimize a normal operation, that is, a process when no error occurs, and improve the performance of the memory system. It is to realize the improvement. Utilizing a high-speed access mode of a memory element by providing a means for realizing error detection / correction and parallel operation of reading next data without impairing an error detection / correction function as a memory system. Is possible. In the memory system to which the present invention is applied, the time required for burst reading when a correctable error occurs is not always shorter than that of the conventional method, although it depends on the realizing means and the error occurrence probability. . But,
In practice, the probability that a correctable error occurs constantly is extremely low, and the performance of the entire memory system is improved. In particular, when using the high-speed access mode of the memory element,
A great effect can be obtained by operating the error detection / correction and reading of the next data in parallel.

[0007]

1 shows the position of a memory control circuit to which the present invention is applied in a computer system. The memory control circuit starts operating in response to a memory access request signal based on a signal on the processor bus, and generates an address to the memory element, a control signal, and a completion signal for accessing the processor bus. An error detection / correction circuit is provided in a data path between the processor bus and the memory element. If an error occurs in reading the memory, the information is sent to the memory control circuit.

FIG. 2 is a block diagram of a memory control circuit to which the present invention is applied, and FIG. 2 is a state transition diagram. Here, the prescribed number of burst read data is 4 long words, 1 long word is 4 bytes, and 1 word is 2 bytes. One longword read / write is one read / write
In write access, both one-word and one-byte write are realized by one read-modify-write access, and burst read and burst write are realized by page-mode read / write access, which is a high-speed access mode of a memory element to be used. ing.

[0009] This memory control circuit starts from an idle state,
From the outside, it is treated as transitioning to six states in response to the six activation signals, but internally, it transitions to eight states according to the presence or absence of error correction. It comprises a holding circuit 1, six sequencer circuits 2, and an internal start / end signal generation circuit 3 for error correction.

When a burst read activation signal is supplied to the memory control circuit, the page mode read sequencer circuit 4 is activated at the same time as a transition to the burst read state. Three types of error determination result signals NOER provided from an external error detection circuit according to the operation of the memory control circuit
R (no error), ERR123 (correctable error occurs in first to third longwords), and ERR4 (correctable error occurs in fourth longword)
The end signal generation circuit 3 instructs the next operation. NOERR
If there is no error, end the burst read state,
The state transits to the idle state, and in the case of ERR123 (correctable error occurs in the first to third longwords) and ERR4 (correctable error occurs in the fourth longword), the write access sequencer circuit 5 is activated to correct the error. .
In the case of ERR123 (correctable error occurs in the first to third longwords), the page mode read sequencer circuit 4 is restarted after the end of write access, and in the case of ERR4 (correctable error occurs in the fourth longword), write access is performed. After the end, the burst read state ends, and the state transits to the idle state. When an uncorrectable error occurs, no internal start signal is generated, and a signal notifying the occurrence of the uncorrectable error is transmitted at the same time as the processing end signal, and the state transits to the idle state. As described above, the processing for the error is performed by the internal start / end signal generation circuit 3 implemented by a simple combinational circuit.
As a result, the memory control circuit automatically performs the processing, and the processor does not need to consider whether or not there is a correctable error.

As described above, in this memory control circuit, the internal start / end signal generation circuit 3 using a simple combination circuit is added, and the optimized page mode read sequencer circuit 4 and write access sequencer circuit 5 The combination realizes an error-correctable burst read.

FIG. 4A shows a burst read timing of the memory control circuit. The next reading process is started without waiting for the error determination result for each long word, and the page mode read of the memory element is effectively used. In the conventional method, as shown in FIG. 4B, the next read process cannot be started until the error determination result is obtained for each long word, and the page mode read cannot be used effectively.

In FIG. 4, the time required until a response signal to the fourth long word is obtained is T (a) = 4 (read time) + (error detection time) in the present invention. In the method, T (b) = 4 (readout time) +4 (error detection time). Assuming that (reading time) = 90 ns and 4 (error detection time) = 60 ns, T (a) = 420
ns, T (b) = 600 ns, and about 2 /
The burst reading is completed at time 3.

FIG. 5 shows a burst read timing when an error occurs in the memory control circuit. In the conventional method, as shown in FIG. 6, it is possible to insert a correction write process for a long word in which an error has occurred without interrupting the page mode read. It takes time to restart page mode read after write access. In the worst case, an error occurs in all four longwords, and it takes a considerable time to restart page mode read four times. The probability that the system will continue to run is low and is not considered to be a problem in practice. Also, if there is room in the circuit size, the error occurrence long word number and the correction write data are stored in the page mode read, and the error correction is realized by the page mode write. Only in this case, control for realizing error correction by page mode write is possible.

[0015]

As described above, the present invention provides a high-speed burst read sequence optimized for a high-speed access mode of a memory device and a memory write sequence activated when a correctable error is detected. The combination improves the performance of the entire memory system by optimizing the normal operation, that is, the processing when no error occurs, and simplifying the error correction processing with a very low probability of actually being required. is there.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a memory system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a memory control circuit according to one embodiment of the present invention.

FIG. 3 is a state transition diagram of a memory control circuit according to an embodiment of the present invention.

FIG. 4 is a burst read timing chart of a memory control circuit according to one embodiment of the present invention.

FIG. 5 is a burst read timing chart at the time of error correction of a memory control circuit according to an embodiment of the present invention.

FIG. 6 is a burst read timing chart at the time of error correction of a conventional memory control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... State holding circuit, 2 ... Sequencer circuit, 3 ... Internal start / end signal generation circuit at the time of error correction, 4 ... Page mode read sequencer circuit, 5 ... Write access sequencer circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuji Kobayashi 810 Shimoimaizumi, Ebina-shi, Kanagawa Office System Design and Development Center, Hitachi, Ltd. (56) References JP-A-62-260251 (JP, A) JP-A-2-72455 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 12/16 320 G06F 11/10 330 G11C 11/401 G11C 29/00 631

Claims (1)

(57) [Claims] 1. A data processing system comprising: a memory for storing data; a processor for issuing an access request to the memory; and a memory control circuit for receiving the access request and controlling the memory. A circuit for receiving an access request from the processor and setting the memory control circuit to a burst read state, a page mode read processing circuit for continuously reading a predetermined number of data from the memory, and a page mode read processing circuit A circuit for detecting an error of each data read, a circuit for correcting an error of the data detected by the error detection circuit, a write processing circuit for writing the data corrected by the error correction circuit to the memory, A control circuit for controlling a setting circuit, the page mode read processing circuit, and the write processing circuit; A control circuit, when no error is detected by the error detection circuit, releases the burst read state of the setting circuit and outputs an end signal; and the error detection circuit performs the page mode read processing. When the error is detected in the last data read by the circuit, the error of the last data is corrected, the write processing circuit is operated to write the corrected data to the memory, and the burst read of the setting circuit is performed. The state is released and an end signal is output. In response to the error detection circuit detecting an error in data other than the last data read by the page mode read processing circuit, the reading of the page mode read processing circuit is terminated. Later, correct the data in which the error was detected,
A data processing system, wherein after operating the write processing circuit to write the corrected data into the memory, operating the page mode read processing circuit again to read a predetermined number of data again.