JP2758858B2 - Specific data trace device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a specific data tracing device, and more particularly to a specific data tracing device for monitoring a specific data by monitoring a bus inside a computer device.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No.
No. 2332, “Data collection method” can be mentioned.

FIG. 9 is a block diagram showing an example of a conventional data collection system, which is equivalent to that described in the above-mentioned publication.

Referring to FIG. 9, this conventional example is based on a CPU.
601, a data collection device 600 including a RAM 602 and a ROM 603, and a trigger address area setting unit 70.
1 and a trigger address area setting / comparing unit 700 including a comparing unit 702, and a logic analyzer 800.

The CPU 601, the RAM 602, and the R
OM603, logic analyzer 800 and comparison unit 7
02 is connected by an address line 604, and the address information from the address line 604 is compared with the address value from the trigger address area setting unit 701 by the comparing unit 702.

The CPU 601 samples the comparison result of the comparison unit 702 using the MI cycle line 605, and outputs a pulse from the comparison unit 702 to the external clock line 703 when it is determined that the address is within the address area.

The logic analyzer 800 accumulates address information on the address line 604 by this pulse.

In the conventional example having this configuration, only the data to be traced is collected and an external clock is supplied to the logic analyzer only when the CPU effective address is within the set area, so that the memory area in the logic analyzer can be effectively used. It can be used.

[0009]

In this conventional data collection method, it is necessary to set an address value or an address area serving as a trigger point before executing data tracing, so that specific data is tracked. Sometimes, it is necessary to check all addresses each time read / write transfer of specific data is performed, so that not only is the setting complicated, but there is a risk that a setting error may occur. .

[0010] An object of the present invention is to connect an analyzer unit to a bus inside a computer device and transfer a tag code together with data inside the computer device.
It is an object of the present invention to provide a specific data tracing device capable of automatically tracing without setting address conditions even if specific data is transferred between a CPU, a memory, and an input / output unit with different address information.

[0011]

According to the present invention, a CPU is provided.
A specific data tracing device for tracing specific data on a bus inside a computer device having a memory and an input / output unit, wherein the tag code is connected to the bus and transferred inside the computer device together with the specific data. A specific data tracing apparatus, wherein the analyzer unit sets conditions for finding the specific data and then detects the specific data by the tag code.

The analyzer unit monitors an address, data, and a control signal on the bus to detect a match with the preset condition, and a bus monitor unit for detecting a match with the preset condition. A tracing memory unit for fetching and storing the address, data and control signal, a tag transmitting unit for transmitting the tag code added to the data on the bus when the condition is satisfied, A tag detection unit for detecting a code, an address latch unit for storing an address value on the bus when the tag code is detected, and the address value stored in the address latch unit and the address on the bus. A specific data tracing device comprising an address comparing unit for comparing the value with a value is obtained.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a specific data tracing apparatus according to the present invention. Referring to FIG.
In this embodiment, the CPU unit 100, the input / output unit 300, the data memory unit 400, and the instruction memory unit 500
Are composed of a computer device 900 mutually connected by a bus 115, and an analyzer unit 200 for monitoring and tracing the computer device 900. The analyzer unit 200 and the computer device 900 are connected by a bus 115 and a tag bus 111.

The analyzer unit 200 includes a tag control unit 210
, Analyzer control unit 270 and analyzer operation unit 29
8 and a bus monitoring unit 299.

Then, the bus 115 of the computer 900 is monitored by the bus monitor 299, and the information on the bus 115 is fetched and traced.

The tag control section 210 generates a tag code when a trigger is applied by the bus monitoring section 299, sends the tag code to the CPU section 100 as a part of the data through the tag bus 111, and outputs the tag code from the CPU section 100. The tag code is monitored and used as a trace trigger of the bus monitoring unit 299.

The analyzer operation unit 298 is a bus monitoring unit 29
9 is set as a trigger condition, and a trace result is displayed.

The analyzer control unit 270 includes the analyzer unit 2
00 is controlled by the analyzer operation unit 29
8. Data transfer between the bus monitoring unit 299 and the tag control unit 210 and control thereof.

The computer device 900 is a device for mainly performing data communication.
Communication with the outside through

A plurality of input / output units 300 (only one is shown in the figure) are connected to the bus 115. And
The data received by the input / output unit 300 via the communication line 901 is taken into the CPU unit 100 via the bus 115, and the data read /
The processing is performed while writing is performed, and the processing result is transmitted from the input / output unit 300 to the communication line 901.

The instruction memory unit 500 has a CP
Stores the instruction of the U unit 100, and stores
0 reads and executes this instruction.

FIG. 2 is an internal block diagram of the analyzer unit in FIG. 1, showing details of the bus monitoring unit and the tag control unit.

The bus 115 in the computer 900 comprises an address bus 285, a data bus 286, and a control signal bus 287.

The address bus 285 is connected to the address comparing section 220, the address latching section 230, the address comparing section 240 and the tracing memory section 260, and the data bus 286 is connected to the tracing memory section 260 and the control signal bus 287 The address strobe signal and the data strobe signal are changed by the analyzer control unit 270
Is input to The tag bus 111 is input and output from the tag control unit 210 as a bidirectional signal.

The address comparing section 240 compares the address value 289 set in the address setting section 250 by the address setting signal 288 from the analyzer control section 270 with the address value on the address bus 285. 283 to the analyzer controller 270 and the tag controller 210.

The tag control section 210 generates the tag code 104 and outputs it to the tag bus 111. Tag control unit 2
Reference numeral 10 indicates a valid tag code 10 by monitoring the tag bus 111.
4 is detected, the tag code detection signal 282 is notified to the analyzer control unit 270 and the address latch unit 2 is detected.
A pulse is sent to the address 30 and the address information on the address bus 285 at that time is stored in the address latch unit 230.

The address information stored in the address latch unit 230 and the address information on the address bus 285 are compared in the address comparing unit 220, and when they match, an address match signal 284 is reported to the analyzer control unit 270.

The analyzer control section 270 has an address match signal 283 in the address comparison section 240 and a tag control section 210.
Receives a tag code detection signal 282 indicating that a valid tag code has been detected and an address match signal 284 in the address comparison section 220, sends a write signal 291 to the tracing memory section 260 and outputs the address at that time. The address information on the bus 285 and the data on the data bus 286 are stored in the trace memory 260.

Immediately after storing these address information and data, the address information 2 in the trace memory 260 is stored.
92 is updated by the analyzer control unit 270.

The analyzer control section 270 also controls the reading of the output data 290 from the trace memory section 260.

FIG. 3 is a block diagram showing details of the tag code sending section, address comparing section and address setting section in the tag control section in FIG.

The tag code sending section in the tag control section 210 shown in FIG. 2 is composed of an encoder 212 and a buffer 213 as shown in FIG.

The address setting section 250 is composed of an address setting 251, an address setting 252, and an address setting 253 for performing three different address settings, and the address setting is performed by an address setting signal 288 from the analyzer control section 270, respectively. Done.

Further, the address comparison unit 240 includes an address comparison 241, an address comparison 242, and an address comparison 2
43, and compares the address value on the address bus 285 with the address value 289 set by the address setting 251, the address setting 252 and the address setting 253, respectively.

Address comparison 241, address comparison 242
And address match signal 28 from address comparison 243
3 is input to inputs 1, 2, and 3 of the encoder 212 and is encoded.

In the address comparison 241, the address match signal 2
When 83 is output, the output of the encoder 212 is “0”.
1 ", and the address comparison signal
3 is output, the output of the encoder 212 is “1”.
0 ", and the address match signal 2
When 83 is output, the output of the encoder 212 is “1”.
When the address match signal is not output from any of the three address comparisons 241, 242 and 243, the output of the encoder 212 is “00”.

When the read / write signal 281 is in a read cycle, the output of the encoder 212 is output to the tag bus 111 through the buffer 213. The tag bus 11
The tag code of 1 has a 2-bit configuration, and the tag code is “0”.
If it is "0", this is defined as an invalid tag code.

FIG. 4 is a block diagram showing the details of the tag code detector, address latch and address comparator in the tag controller in FIG.

The tag code transmission section in the tag control section 210 shown in FIG. 2 is composed of a decoder 211 as shown in FIG.

The address latch section 230 comprises an address latch 231, an address latch 232, and an address latch 233 for latching three types of addresses.

Further, the address comparing section 220 includes an address comparing section 221, an address comparing section 222 and an address comparing section 2.
The address information on the address bus 285 is compared with the address information on the address latch 231, the address latch 232, and the address latch 233.

Then, the address match signal 284 of the address comparison 221, the address comparison 222 and the address comparison 223 is sent to the analyzer control section 270.

The decoder 211 monitors the tag bus 111 and analyzes the tag code at the timing of the data strobe signal. When the tag code is "01", it is stored in the address latch 231. When the tag code is "10", the address latch 231 is read. When the tag code is "11", the tag code detection signal 282 is sent to the address latch 233, and the address value on the address bus 285 at that time is stored.

The stored address value is used for subsequent monitoring of the address bus 285 by the address comparing section 220 shown in FIG.

Next, FIG. 5 is an internal block diagram of the CPU unit in FIG. 1, and FIG. 6 is a diagram showing an example of a data structure on the internal bus in FIG.

The bus 115 is composed of the address bus 285, the data bus 286, and the control signal bus 287 as described above.

The tag bus 111 and the data bus 28
6 is connected to the internal bus 110 of the CPU unit through the bidirectional buffer 101.

The internal bus 110 is connected to the control register 105, the general-purpose register 106, the temporary register 107A, the temporary register 107B, the ALU 108, and the instruction analyzing / executing unit 109, and performs data transfer between them.

The tag code is transferred on the internal bus 110 together with the data output to the data bus 286.

The control register 105 outputs address information to the address bus 285 through the buffer 102, and the bus control unit 114 controls the control signal bus 2 through the buffer 103.
The transfer of the control signal is performed between the control signal and the control signal 87.

The data structure on the internal bus 110 is composed of 16 bits of the data section (D ₀ ,..., D ₁₅ ) and 2 bits of the tag section (T ₀ , T ₁ ) as shown in FIG. ,
A total of 18 bits are transferred inside the CPU section. However, it is assumed that the tag section is excluded when performing the calculation and is processed.

Next, FIG. 7 shows an example of transfer timing of signals and data on the bus and the tag bus in FIG.
(A) and (b) are timing charts in a write cycle and a read cycle, respectively.

Referring to FIG. 7, the address strobe and the data strobe indicate that the address information on the address bus 285 and the data on the data bus 286 are determined, respectively. R / W indicates the direction of data transfer, “0” indicates writing, and “1” indicates reading.

Since the tag code on the tag bus is transferred together with the data, the transfer timing is the same as the data.

Next, the operation of this embodiment will be described with reference to FIGS. 1, 2 and 8.

FIG. 8 is a diagram for explaining a specific data tracing operation in the embodiment shown in FIG.

The analyzer section 200 includes a CPU section 100
Is set in advance with an address for taking in the communication data received by the input / output unit 300.

The input / output unit 300 receives the communication data,
When data is transferred to the PU unit 100, a trigger is activated in the analyzer unit 200, the data on the bus 115 at that time is captured as trace data, and the tag code 104 is generated and transmitted to the tag bus 111.

The CPU unit 100 takes in the data from the input / output unit 300 on the data bus 286 and the tag code 104, and carries out the internal processing by rotating the tag.

When writing (writing) the internally processed data to the data memory unit 400 via the bus 115,
The analyzer unit 200 detects the tag code 104 output on the tag bus 111, captures it as trace data, and stores the address information on the address bus 285 at that time.

When data is read from the data memory unit 400 to the data bus 286 (read), the address comparison unit 2 in the analyzer unit 200 stores the address information at the time of data writing.
At 20, the address value is matched to be taken in as trace data, and the generated tag code 104 is added to the data and sent to the tag bus 111.

The CPU section 100 fetches the data from the data memory section 400 on the data bus 286 and the tag code 104 and carries out the internal processing by rotating the tags.

When writing (writing) the internally processed data to the input / output unit 300 via the bus 115, the analyzer unit 200 can detect the tag code 104 output on the tag bus 111 and take it in as trace data.

In this embodiment, the address comparing section 240
Detects that the address value on the address bus 285 coincides with a preset address value, but in addition to collation of all bits, collation of a specific bit, collation of a range of address values, and R other than the address. By using the / W condition setting, the data condition setting on the data bus 286, the pulse indicating the reception timing of the received data generated from the input / output unit 300, and a combination of these conditions, a wider range of trigger conditions can be obtained. be able to.

[0066]

As described above, the present invention provides a CPU
, A memory, and a specific data tracing device for tracing specific data on a bus inside a computer device having an input / output unit, wherein an analyzer unit connected to the bus and transferring a tag code together with the specific data inside the computer device The analyzer unit sets conditions for finding the specific data and then detects the specific data by the tag code. In an embodiment, the analyzer unit monitors the address, data and control signals on the bus. A bus monitoring unit for detecting a match with the above-mentioned condition set in advance; a tracing memory unit for taking in and storing the address, data and control signal on the bus when the condition matches; A tag sending unit for sending a tag code added to data on the bus, and a tag code A tag detection unit that outputs a tag code, an address latch unit that stores an address value on the bus when a tag code is detected, and an address comparison that compares the address value stored in the address latch unit with the address value on the bus. By setting only the condition when the specific data is first transferred as the trigger condition, it is automatically specified without setting the address every time the specific data is transferred after that. Since data can be tracked, it is not necessary to set an address every time data is transferred, and the operability of a specific data trace is extremely improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a specific data tracing device of the present invention.

FIG. 2 is an internal block diagram of an analyzer unit in FIG. 1, showing details of a bus monitoring unit and a tag control unit.

FIG. 3 is a block diagram showing details of a tag code sending section, an address comparing section, and an address setting section in the tag control section in FIG. 2;

FIG. 4 is a block diagram illustrating details of a tag code detection unit, an address latch unit, and an address comparison unit in the tag control unit in FIG. 2;

FIG. 5 is an internal block diagram of a CPU unit in FIG. 1;

FIG. 6 is a diagram illustrating an example of a data structure on an internal bus in FIG. 5;

FIGS. 7A and 7B show examples of transfer timings of signals and data on a bus and a tag bus in FIG. 1, and FIGS. 7A and 7B are timing charts in a write cycle and a read cycle, respectively.

FIG. 8 is a diagram for explaining a specific data tracing operation in the embodiment shown in FIG. 1;

FIG. 9 is a block diagram showing an example of a conventional data collection method.

[Explanation of symbols]

Reference Signs List 100 CPU unit 101 Bidirectional buffer 102, 103, 213 buffer 104 Tag code 105 Control register 106 General-purpose register 107A, 107B Temporary register 108 ALU 109 Instruction analysis and execution unit 110 Internal bus 111 Tag bus 114 Bus control unit 115 Bus 200 Analyzer unit 210 Tag control unit 211 Decoder 212 Encoder 220, 240 Address comparison unit 221, 222, 223, 241, 242, 243
Address comparison 230 Address latch unit 231, 232, 233 Address latch 250 Address setting unit 251, 252, 253 Address setting 260 Trace memory unit 270 Analyzer control unit 281 Read / write signal 282 Tag code detection signal 283, 284 Address match signal 285 Address bus 286 Data bus 287 Control signal bus 288 Address setting signal 289 Address value 290 Output data of tracing memory section 291 Write signal 292 Address information 298 Analyzer operation section 299 Bus monitoring section 300 Input / output section 400 Data memory section 500 Instruction memory section 600 Data collection device 601 CPU 602 RAM 603 ROM 604 Address line 605 MI cycle line 700 Trigger address Rear setting comparison unit 701 Trigger address area setting unit 702 Comparison unit 703 External clock line 800 Logic analyzer 900 Computer unit 901 Communication line

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-64818 (JP, A) JP-A-4-336630 (JP, A) JP-A-60-159951 (JP, A) JP-A-2- 110636 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 11/28-11/34

Claims (2)

(57) [Claims] 1. A specific data tracing device for tracing specific data on a bus inside a computer device including a CPU, a memory, and an input / output unit, wherein a tag code is connected to the bus and inside the computer device. A specific data tracing device, comprising: an analyzer unit for transferring the specified data together with the specific data, wherein the analyzer unit sets conditions for finding the specific data and then detects the specific data by the tag code. 2. An analyzer according to claim 1, wherein said analyzer monitors an address, data, and a control signal on said bus to detect a match with said preset condition. A tracing memory unit for fetching and storing the address, data and control signal, a tag transmitting unit for transmitting the tag code added to the data on the bus when the condition is satisfied, A tag detection unit for detecting a code, an address latch unit for storing an address value on the bus when the tag code is detected, and the address value stored in the address latch unit and the address on the bus. 2. The specific data tracing device according to claim 1, further comprising: an address comparison unit that compares the value with a value.