JPS5831458A - Address matching device - Google Patents

Abstract

PURPOSE:To analyze faulty hardware and software, by collating an address of an address bus with a set address, and also outputting a coincidence signal of a counting value of an address matching signal, and the number of times of setting. CONSTITUTION:A matching address is sent out to a data bus BUS1 from a console 4, and also a setting signal SET1 is outputted to an address coincidence detecting part 3. Subsequently, a match counting number is sent out, and also a setting signal SET2 is outputted to a control counter 5. After that, when a CPU1 starts execution of a program, coincidence of an address on an address bus AB, and a set matching address is detected 3, and a matching signal MATCH is outputted to the counter 5 and a program stop controlling part 2. Also, when the match counting number set in advance coincides with the number of times of input of the signal MATCH, a coincidence signal CN0 is outputted to the control part 2 from the counter 5. Subsequently, a stop command HALT is outputted to the CPU1 from the controlling part 2, and the progress of the program is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address matching device, and more particularly, to an address matching device for an electronic computer,
The present invention relates to an address matching device suitable for application to peripheral devices for supporting development, etc.

The computer control panel and console panel used in the debugging stage of program development are useful for the address match function, address stop, and program counter stop associated with software development support tools such as microcombiners. As (PCHALT), break points, etc., the following methods are conventionally known.

First, in the debugging stage of the program, check whether the program flows as intended by the programmer, and in order to discover any mistakes in the program, specify an arbitrary stop address, start the program, and then The quality of the program is determined based on whether the program execution by the central processing unit K reaches the specified next stop address or not. However, this method can only partially diagnose software and hardware runaways and abnormal operations, and has the following drawbacks.

(1) If you want to perform an address match within a subroutine, stop every time you enter that subroutine. Unfortunately, it is not possible to stop a subroutine after it has been called a certain number of times. Therefore, if the predetermined number is small, manual operation by the programmer is sufficient, but if the predetermined number is large, the operation becomes difficult.

If the program involves data transfer or peripheral device control, the hardware continues to operate even if the program stops.

Next, the program stops and the software and hardware are no longer synchronized at time t, making subsequent abnormality analysis difficult. In many cases, hardware and software are being developed simultaneously for IJK multi-microcombi data application products. Therefore, no matter what abnormality analysis device is used, if the software for driving the hardware is not synchronized with the hardware, an abnormality will result, and it is impossible to analyze the hardware and software in this state. For example, in data transfer, if it is stopped at an arbitrary address, there will be no transmission underrun or reception overrun, and the hardware will perform operations such as error processing. Therefore, after data transmission has been performed a certain number of times, analysis of hardware and software and investigation of transmitted data are no longer possible.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to enable conditional address matching.
For products in which hardware and software are being developed simultaneously, it is possible to analyze incomplete hardware and software, and it also provides a reliable means of analysis for devices that require hardware and software to operate in synchronization. The purpose of the present invention is to provide a novel address matching device.

Hereinafter, the present invention will be described in detail with reference to the drawings.・FIG. 1 is a block diagram of an address match device according to an embodiment of the present invention, in which l represents a CPU, and C represents a program stop control unit that issues a stop command HALT to the CPU/;
AB is an address bus for transferring address signals, C
B is the next control bus that transfers control signals, and G is the console where the operator inputs various conditions.

BU8/ is a data bus that transfers address data and setting data for control, and J is a setting signal SE from the console.
a match address matching detection unit which takes in a match address at which the CPU/ is to be stopped based on T/ via a data bus BU8/, and outputs a match signal MATCH when an address on the address bus AB matches this match address; !
is console l i) h Cap (7) Setting signal 5E
The match count number based on the data bus RUB/
This is a control counter that outputs a match signal CNO when the count value of the match signal MATCH from the address match detection unit J matches the match count number.

The operation of this configuration will now be described with reference to the time chart of FIG. By the way, Figure 1 (4) shows the address timing of address bus AB.

Figure 2) shows the signal timing of the control bus CB,
Figure i (b) shows the data tie construction of the data bus BU8/, Figure 2 (b) shows the setting signal 8ET/, Figure 1 (6) shows the setting signal 81TJ, and Figure λ (b) shows the control counter J. The match signal CNO from the second figure) is the match signal MAYCH from the data coincidence detecting section 3, and the second figure (6) is the stop command HALT to the CPU/. Incidentally, in the time chart of FIG. 2, 〒 indicated by TI is the setting period for the match address and match count number, and the period indicated by Tl is the period after the start of the program.

First, at the beginning of period T1, a match address is sent from the console to the data bus BUS/, and a setting signal 8ET/ is output to the address match detection section J. As a result, the address match detection section J is set with a matching address. Next, data bus BU8 is connected from 1 console
For 7, send out the match count number and control the setting signal BET □ Counter! Output to. As a result, control counter! The match count number is set for .

Next, in period T2, when the CPU/ starts executing the program, a 7-step signal is output to the CPU/control bus CBK. This fetch signal is C
This is a signal generated when the instruction code is etched into the instruction register of the PU. The address match detection section J compares the address on the address bus AB with the fixed match address in synchronization with the 7-match signal, and if a match is detected, the match signal MATCH is sent to the control counter! It is also output to the program stop control section. In addition, the control counter! adopts a presetter pull-down counter configuration, and counts down the initially set match count number (counts down every time IN No. MA-TCH is input. Now, if the preset match count number is N, then the match signal MATCH is N
When the same person is selected, the control counter j becomes "0" and outputs a signal representing this, a match signal CNO, to the program stop control section.

When the program stop control section receives the match signal MATCH from the address coincidence detection section 3 while receiving the coincidence signal CNO, it outputs a stop command HALT to the CPU/, and stops the progress of the program.

In addition, the control counter! The maximum number of match counts that can be set depends on the number of bits of the built-in counter. Also,
The coincidence detection method does not necessarily have to be a down count method, and a digital comparator may also be used. In this case, there is an advantage that there is no need to reset as long as the match count number remains the same.

Peripheral devices of a computer are controlled by a driver routine under the management of an operating system, and the same is true for microcombiators.

For example, in a transmission control module, data is exchanged between the module and the CPU only in a certain subroutine in the driver routine. Therefore, the program passes through this subroutine many times. 1 At this time, only the transmitted and received data is different. In such a case, if the address matching device according to the present invention is used, it is possible to stop the CPU at a predetermined address in any routine, so it is possible to effectively judge whether the program is good or bad regarding abnormalities during execution. .

On the other hand, in recent years, computer peripherals have become more sophisticated and are being converted into firmware. When analyzing abnormalities in hardware, software, and firmware in such a system, the hardware and firmware continue to operate even if the software stops.

In contrast, conventionally it was possible to analyze the movement of the tuna until it reached the first match point, but it was impossible to analyze the movement after that. For example, it is possible to continue the program by ignoring the address match point an arbitrary number of times, so it is possible to efficiently perform abnormality analysis while stopping -CPυ in one step.0
As described above, according to the present invention, there is a system in which the operation of a combination machine is analyzed while stopping the CPU at an address specification point, and a desired address matching point is specified and the CPU is stopped at this point. Therefore, it is possible to obtain a new address matching device that can greatly improve the efficiency of program behavior analysis.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an address match device according to an embodiment of the present invention. , FIG. 2 is a meme chart explaining the operation of the configuration shown in FIG. 1. ◇ l: CPU, 2: program stop control section. 3...Address-alIltB section, a...Console,! ,...control counter. Applicant's agent Kiyoshi Inomata

Claims (1)

[Claims] A means for setting the address to be detected and outputting an address match signal by matching the address of the address bus with the set address, and a means for setting the number of address detections and counting the address match signal, and setting this count value and setting. An address matching device comprising means for outputting a matching signal when the number of times matches.