JP2730109B2 - Memory monitoring method for time slot switching equipment - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to an improvement in a monitoring method, and more particularly to a memory monitoring method in a time slot changer.

(Prior Art) FIG. 3 is a block diagram showing an example of a conventional memory monitoring method. In FIG. 3, 1 is a monitoring signal generation circuit, 2 is a first selection circuit, 31 and 32 are temporary storage circuits, 4 is a write counter, 5 is a read counter,
Reference numeral 6 denotes a second selection circuit, and reference numeral 7 denotes a monitoring signal comparison circuit.

Conventionally, in this type of monitoring system, two temporary storage circuits 31 and 32 are prepared as shown in FIG. 3, and a monitoring pattern is inserted into an empty time slot in an input data sequence.
After replacing the time slots, it has been confirmed that a monitoring pattern is output at a predetermined position.

(Problems to be Solved by the Invention) In the conventional memory monitoring method described above, data is alternately written to and read from two temporary storage circuits. Thank you
When only one empty time slot for monitoring in the input data string can be assigned to two periods, the monitoring pattern can be written / read only to one temporary memory circuit, but the other temporary memory circuit can be written. Has the disadvantage that it cannot be monitored.

An object of the present invention is to prepare for three temporary storage circuits to cope with the case where there is only one empty time slot in the input data in two periods, and to use the temporary storage circuits in the period of writing / reading / rest, thereby solving the above-mentioned disadvantage. It is an object of the present invention to provide a memory monitoring method which is configured so as to be able to monitor all temporary storage circuits.

(Means for Solving the Problems) A memory monitoring method according to the present invention includes a monitoring signal generation circuit for generating a monitoring signal, a first selection circuit for selecting an input signal or the monitoring signal, and Three temporary storage circuits, each of which sequentially writes and randomly reads the output of the first selection circuit as data or randomly writes and sequentially reads and writes in order to write, read and pause. A write counter for generating a timing for writing data to the three temporary storage circuits; a read counter for reading data from the three temporary storage circuits; and an output of the three temporary storage circuits A second selection circuit for selecting one of the above and executing the exchange of time slots; and a monitoring signal included in an output of the second selection circuit. And a monitoring signal matching circuit for checking the pattern with the monitoring pattern.

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a memory monitoring system according to the present invention.

In FIG. 1, reference numeral 1 denotes a monitoring signal generation circuit;
, 31 to 33 are first to third temporary storage circuits, 41 is a write counter, 51 is a read counter, 6 is a second selection circuit, and 7 is a monitoring signal comparison circuit. In FIG. 1, the same elements as those in FIG. 2 are denoted by the same reference numerals.

The data input is applied to the first selection circuit 2 together with the monitoring pattern output from the monitoring signal generation circuit 1, and the first selection circuit 2 selects the monitoring pattern based on the empty time slot of the data input. These data inputs are
Input to the third temporary storage circuits 31 to 33 and write counter
The data is written into the first to third temporary storage circuits 31 to 33 according to the instruction of 41. The data read from the first to third temporary storage circuits 31 to 33 according to the instruction of the read counter 51 is selected by the second selection circuit 6 and output. Read data is
Next, the pattern is compared with the monitoring pattern by the pattern matching circuit 7.

FIG. 2 is a time chart showing the above operation in comparison with the operation of the conventional system.

If only one empty time slot can be prepared in the input data in two cycles, the monitoring pattern is written only in the first temporary storage circuit 31 in the prior art, and only the first temporary storage circuit 31 is monitored. Can not.

In the present invention, when the first to third temporary storage circuits 31 to 33 are used in a cycle of writing / reading / rest, one empty time slot is sequentially provided in two cycles in the first to third temporary storage circuits 31 to 33. ~ 33 will pass.

(Effects of the Invention) As described above, the present invention prepares three temporary storage circuits to deal with the case where there is only one empty time slot in two periods in the input data, and performs write / read / read.
The use of a period called a break has the effect that three temporary storage circuits can be monitored alternately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a memory monitoring system according to the present invention. FIG. 2 is a time chart showing the operation of the present invention in comparison with the operation of the conventional system. FIG. 3 is a configuration diagram of a conventional memory monitoring system. 1 monitoring signal generation circuit 2, 6 selection circuit 31 to 33 temporary storage circuit 4, 41 write counter 5, 51 read counter 7 monitoring signal verification circuit

Claims (1)

(57) [Claims] 1. A monitoring signal generating circuit for generating a monitoring signal, and a first signal for selecting an input signal or the monitoring signal.
And the three selection circuits which sequentially write and read out the output of the first selection circuit as data, or operate at writing, reading and pausing cycles for writing and reading out at random. A temporary storage circuit; a write counter for generating a timing for writing data to the three temporary storage circuits; a read counter for reading data from the three temporary storage circuits; A second selection circuit for selecting one of the outputs of the storage circuit and exchanging the time slots, and for comparing a monitoring signal included in an output of the second selection circuit with a monitoring pattern. A memory monitoring system in a time slot exchanging device, comprising a monitoring signal matching circuit.