JPH057388A - Time switch fault monitor - Google Patents

Abstract

PURPOSE:To always monitor a fault of all areas by writing a prescribed time slot as a time switch monitor time slot to a memory at write and reading all addresses of all areas of the memory sequentially and repetitively at read. CONSTITUTION:A signal S1 multiplexed onto a time slot is written sequentially in a memory 14 together with a parity bit generated by a parity bit generating circuit 11 by using a sequential write address string from a counter 19. A time slot generating decoder 21 for time switch fault monitor generates a prescribed time slot at read and a read address for the time slot is repetitively generated by the counter 19 over all areas of the memory 14. Then a parity bit of a read data is discriminated by the parity check circuit 12. Thus, all the areas of the time switch are always monitored for their fault.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a time division multiplexer and a time switch failure monitor for an electronic exchange.
In particular, the present invention relates to a time switch failure monitoring device including a memory.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional time switch failure monitoring apparatus. FIG. 4 is a diagram showing the contents of the address control memory of the conventional time switch failure monitoring device. Conventionally, the time switch failure monitoring device has a configuration as shown in FIG. FIG. 3 shows a write sequential read random T with time switching of n time slots.
This is a one-stage time switch. The input signal S1 multiplexed in the n time slots together with the parity bit generated by the parity bit generation circuit 11 is supplied to the counter 1
Sequential write address sequence 31 generated at 9A
The data is sequentially written in the memory 14 by A.

The switched output signal S3 is generated by being read from the memory 14 according to the contents of the address control memory 20A (read address string 32A shown in FIG. 4). In this case, the parity check circuit 12A determines whether the read data is true or false and monitors the failure.

[0004]

However, such a conventional time switch fault monitoring apparatus has a problem that fault monitoring is performed only in the memory area designated for reading by the address control memory.

Further, as in the case of the contents of the address control memory shown in FIG. 4, there is also switching for reading the same memory area twice (read address AD1 in the read address string 32A), and therefore there is a read address from the address control memory. There was a problem that failure monitoring inevitably could not be carried out in all areas.

The present invention solves the above problems.
An object of the present invention is to provide a time switch failure monitoring device capable of constantly performing failure monitoring in all areas of a time switch.

[0007]

According to the present invention, there is provided a parity bit generation circuit for generating a parity bit of an input signal multiplexed in a predetermined number of time slots, the input signal and the parity based on a write address to be input. A memory that stores the output parity bit of the bit generation circuit and reads the contents based on the input read address, a parity check circuit that checks the parity of the output signal read from this memory, and the write address and the write address in the memory. In a time switch failure monitoring device provided with write / read means for giving a read address, the write / read means writes a predetermined time slot into the memory together with the input signal and a parity bit as a time switch monitoring time slot. When an embedded address is given and the above specified time slot is read And means for performing write and read as read addresses by giving repeated addresses of all areas of the memory in order, the parity check circuit is characterized in that it comprises a means for performing a parity check of the predetermined time slots.

Further, according to the present invention, the write address may be an address for sequentially writing the input signal in the memory, and the read address may be an address for randomly reading the contents of the memory.

[0009]

The writing / reading means gives the memory a write address for writing a predetermined time slot as a time switch monitoring time slot together with an input signal and a parity bit, and the entire area of the memory is used as a read address when reading the predetermined time slot. The addresses are sequentially repeated and written and read. The parity check circuit checks the parity of a predetermined time slot.

As described above, it is possible to constantly monitor the failure of the entire area of the time switch.

[0011]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a time switch failure monitoring apparatus according to an embodiment of the present invention.

In FIG. 1, the time switch fault monitoring apparatus inputs a parity bit generation circuit 11 for generating a parity bit of an input signal S1 multiplexed in (n + 1) time slots and an input based on a write address to be input. A memory 14 which stores the signal S1 and the output parity bit of the parity bit generation circuit 11 and reads the contents based on the input read address; and a parity check circuit 12 which performs a parity check of the output signal S3 read from the memory 14. , A 1/2 frequency divider 1 as write / read means for giving the write address and read address to the memory 14.
8, a selector 16, a counter 19 and an address control memory 20.

A feature of the present invention is that the writing / reading means provides the memory 14 with a write address for writing a predetermined time slot as a time switch monitoring time slot together with the input signal S1, and a predetermined time. The parity check circuit 12 includes selectors 13 and 15, a counter 17 and a decoder 21 as means for performing writing and reading by sequentially giving addresses of the entire area of the memory as reading addresses when reading the slots, and the parity check circuit 12 is a parity of a predetermined time slot. It is to include a means for checking.

The write address is an address for sequentially writing the input signal S1 in the memory 14, and the read address is an address for randomly reading the contents of the memory 14.

The operation of the time switch failure monitoring device having such a configuration will be described. FIG. 2 is a diagram showing the operation of the time switch failure monitoring apparatus of the present invention. FIG. 1 is a one-stage time switch of a write sequential read random T switch for performing time switching of n time slots.
The signal S1 multiplexed in the (n + 1) time slot is sequentially written in the memory 14 by the sequential write address sequence 31 generated by the counter 19 together with the parity bit generated by the parity bit generation circuit 11. FIG. 2 shows the relationship between the multiplexed input signal S1 and the write address string 31.

The switched output signal S3 is generated by being read from the memory 14 based on the contents of the address control memory 20.

In this embodiment, a predetermined time slot 35 of the output signal S3 is defined as a time switch monitoring time slot, a predetermined time slot is generated by the decoder 21 for creating the time switch monitoring time slot, and this predetermined time slot is generated. The read address of the time slot of is sequentially generated by the counter 19 in order of the addresses of the entire area of the memory 14 (time switch monitoring read address 34 shown in FIG. 2 as an example), and the parity bit of the data read from the memory 14 is parity-checked. The check circuit 12 judges whether the condition is true or false, thereby monitoring the failure of the entire area of the time switch.

[0018]

As described above, the present invention has an excellent effect that it is possible to constantly monitor the failure of the entire area of the time switch.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a time switch failure monitoring device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the operation of the time switch failure monitoring apparatus of the present invention.

FIG. 3 is a block configuration diagram of a conventional time switch failure monitoring device.

FIG. 4 is a diagram showing an operation of a conventional time switch failure monitoring device.

[Explanation of symbols]

11 Parity bit generation circuit 12, 12A parity check circuit 13, 15, 16, 16A selector 14 memory 17, 19, 19A counter 18, 18A 1/2 divider 20, 20A address control memory 21 decoder 31, 31A Write address string 32, 32A Read address string 33 Read address Read address for 34 hour switch monitoring 35 hour switch monitoring time slot S1 input signal Output signal of S2 parity check circuit Output signal of S3 memory

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Claims (2)

[Claims] 1. A parity bit generation circuit for generating a parity bit of an input signal multiplexed in a predetermined number of time slots, and the input signal and an output parity bit of this parity bit generation circuit based on a write address to be input. A memory for reading the contents based on a read address to be stored and input, a parity check circuit for performing a parity check of an output signal read from the memory, and a write / read means for giving the write address and the read address to the memory. In the time switch failure monitoring apparatus having the above-mentioned, the writing / reading means gives to the memory a write address for writing a predetermined time slot as a time switch monitoring time slot together with the input signal and the parity bit, and the predetermined address. When reading a time slot, the above address is used as a read address. A time switch failure monitoring apparatus comprising: means for performing writing and reading by repeatedly giving addresses of all areas of the memory sequentially, and the parity check circuit includes means for performing a parity check of the predetermined time slot. 2. The time switch fault monitoring according to claim 1, wherein the write address is an address for sequentially writing the input signal in the memory, and the read address is an address for randomly reading the contents of the memory. apparatus.