JP2888030B2 - Line connection monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit connection monitoring circuit used in communication equipment and the like, and more particularly, to a circuit connection monitoring circuit having a function of preventing erroneous detection of a device failure when initializing an address control memory.

[0002]

2. Description of the Related Art Conventionally, this kind of line connection monitoring circuit has
2. Description of the Related Art In communication devices such as multiplexing devices, relay devices, switching devices, etc., they are used for device failure monitoring of a line connection unit for performing time division line connection.

FIG. 2 is a block diagram showing an example of a conventional line connection monitoring circuit. In FIG. 2, the data memory
3 is a memory which performs a time switch function and is an input data bus.
The line connection of the input data of 12 is changed and the output bus 15 is changed.
Output to This input data is a time division multiplexed data signal
Each line data is accommodated in each time slot in the frame.
Have been. Also one of the empty time slots in the frame
Is inserted with a pass pattern. Address control memo
The memory 7 is provided for each time slot (that is, for each line) of the input data.
(Data and path pattern) are sequentially written to the data memory 3.
And set in advance at a predetermined timing.
For reading each time slot in the specified order
Generates a control signal and outputs it to address bus 15
You. The path pattern generation circuit 4 generates a path pattern and
The empty time of the input data on the input data bus 12
Insert into the slot. The pass pattern detection circuit 5
The pass pattern is detected from the output side of the memory 3 and the data
This is to confirm the normality of the operation of the file 3. in this way
The line connection monitoring circuit includes a path pattern generation circuit 4 and a path pattern generation circuit.
And a ton detection circuit 5 as a main element.

Next, the operation will be described. Input data
The input data signal of the address 12 is
Control signal to the data memory 3
The slots are written sequentially, and each time slot is
A preset sequence with a predetermined timing,
That is, the output bus 15 is read and output in the order of setting the line connection.
Output to In other words, the time slot order is
The line connection is changed by switching in step 3.
On the other hand, the path pattern is detected by the
Data memos can be created by comparing patterns with reference patterns.
The normality of Re3 has been confirmed.

[0005]

In this conventional line connection section monitoring circuit, the address for the line connection and the address for the pass pattern are mixed in the address control memory. Therefore, when the address control memory is initialized,
The pass pattern data is no longer recorded in the data memory 3. At this time, the Pasupatan detection circuit, Pasupatan
Is not detected, so the line setting section of the data memory 3 fails.
There is a problem that judges . The address for line connection
Must be initialized when the equipment is started up, during inspection, etc.
On the other hand, the address for the pass pattern is always
It is added every time and does not need to be initialized.

[0006]

According to the present invention, there is provided a line connection monitoring circuit comprising: a data memory for storing connection destination data and path pattern data of line data input via an input data bus; Address control memory for designating an address to store the data and controlling writing and reading, a path pattern generation circuit for generating the path pattern data, and a path pattern for querying the pulse pattern data of the data memory output via an output data bus A line connection monitoring circuit including a detection circuit, wherein the address control memory specifies a first address of a connection destination data of the line data
And a second address control memory for designating the address of the pass pattern data.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the present embodiment.

In FIG. 1, the outputs of an address control memory 1 for connection line data and an address control memory 2 for pass pattern are connected by an AND circuit 6 and connected to an address bus 15 of the data memory 3. The path pattern generation circuit 4 is connected to the data memory 3 via the input data bus 12, and the data memory 3 is connected to the path pattern detection circuit 5 via the output data bus 16.

Next, the operation of the circuit shown in FIG. 1 will be described. In the address code control memory 2, only the address of the area where the pass pattern is recorded in the data memory 3 is recorded, and 1 is recorded in all other areas. In the address control memory 1, only the connection destination address is recorded, and all 1s are recorded in the pass pattern area. The logical product of these two address control memory outputs by the AND circuit 6 is connected to the address of the data memory 3. As a result, either the connection destination address from the address control memory 1 or the pass pattern address from the address control memory 2 is input to the data memory 3 as the address of the data memory 3. At this time, the path pattern addressed by the address control memory 2 is recorded in the data memory 3 by initializing only the address control memory 1 when the line connection section is initialized. In this way, erroneous detection of a device failure due to initialization of the line connection unit can be prevented.

[0010]

As described above, the line connection monitoring circuit of the present invention divides the line connection address control memory and the path pattern address control memory, so that the path pattern can be detected even if the address control memory is initialized. This has the effect of preventing erroneous detection of a device failure.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 address control memory 2 address control memory 3 data memory 4 pass pattern generation circuit 5 pass pattern detection circuit 11 address bus 12, 15 input data bus 13 output data bus

Claims (1)

(57) [Claims] 1. A control and data memory for the memory and a line de <br/> over data and path pattern data, the specified writing and reading addresses for memory data to the data memory input through the input data path an address control memory for a Pasupatan generation circuit for generating the path pattern data, the line connection unit monitoring circuit and a Pasupatan detection circuit for collation of the path pattern data of the data memory to be output via the output data path , The address control memory stores the line data
Second specifying the first address control memory specifying the address, the address of the path pattern data
And an address control memory.