JPH07322310A - Time division switch testing system - Google Patents

Abstract

PURPOSE:To perform a test at all times even for a time slot with less using frequency. CONSTITUTION:A successive counter 8 performs counting synchronized with the time slot and a test counter 9 is operated in synchronism with the successive counter 8. Since the successive counter 8 generates trigger signals through a signal line (c) at the time of specifying a test time slot, a selector 10 separates a communication memory read address supplied from a communication control memory 7 and transmits signals sent out from the test counter 9 as the communication memory read address. Thus, data are read from a communication memory 2 by communication memory read address signals outputted from the test counter 9 during the period of the test time slot for the communication memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division switch test system having a channel memory among time-division switches used for exchanges.

[0002]

2. Description of the Related Art Conventionally, a time division switch of this type has been constructed so as to confirm normality when a path is connected to an exchange. FIG. 3 shows an example of a conventional device, in which the data of the speech path 1 and the parity data added by the parity adder 4 are sequentially written into the address of the speech memory 2 determined by the counter 6. At this time, the sequential counter 6 operates in synchronization with the change in the time slot of the communication path 1. Therefore, the data of all the time slots of the communication path 1 are written in the communication memory 2.

On the other hand, the call memory 2 is stored in the call control memory 7 for controlling the switch from an external processor when the call is connected.
Write the read address data. The read address data written in the call control memory 7 is read based on the output of the sequential counter 8 which operates in synchronization with the time slot of the call path 3. The read data is the call memory 2
Read address data, the data and the parity data are read from the call memory 2 by the address data, and the normality is tested by the parity checker 5.

[0004]

However, in such a conventional method, not all the time slots of the communication path 1 are used uniformly, so that a long-time unused time slot or an infrequently used time slot is used. If there is,
It has a problem that the failure is found only after using it. Therefore, there is a problem that the failure is not immediately detected, and the failure is not known before use. The present invention has been made in view of such circumstances, and is intended to ensure the immediacy of failure detection.

[0005]

In order to solve such a problem, the invention of claim 1 decides a specific time slot as a test time slot, and when allocating the time slot, the data for all the time slots of the communication memory is set. The data is read out sequentially and tested. A second aspect of the present invention is a call control memory (7) for reading data stored at an address corresponding to a supplied signal, and a sequential counter (8) for supplying sequentially changing address data to the call control memory (7). And a test counter (9) which operates in synchronization with the operation of the sequential counter (8), and a call control memory (7)
And a selector (10) for selecting and transmitting either the output or the output of the test counter (9). The selector sequentially outputs the output of the test counter (9) when the output signal of the counter (8) selects a specific time slot. According to the signal, the test counter output signal is supplied to the call memory until the data of all time slots are read from the call memory. According to a third aspect of the invention, in the first or second aspect of the invention, the call memory is tested by a parity check.

[0006]

According to the present invention, data for all time slots of the call memory are sequentially read out and tested at the time of allocating a specific time slot. According to the invention of claim 2, a test counter output signal which is sequentially synchronized with the counter at a specific time slot is supplied to the call memory, and the test counter output signal is changed so that the data of all time slots can be read. is there. According to a third aspect of the present invention, in the first or second aspect of the invention, the call memory is tested by a parity check.

[0007]

1 is a block diagram of one embodiment of the present invention, FIG.
FIG. 3 is a diagram corresponding to a time division switch highway of the device shown in FIG. 1. In FIG. 1, the sequential counter 6 is counted up in synchronization with the time slot of the communication path 1 and the write address of the communication memory 2 is designated for each time slot.
The call data in each time slot is written in order. At the same time, the parity data added by the parity adder 4 is also written at the same time.

On the other hand, the sequential counter 8 counts up in synchronization with the time slot of the speech path 3, so that the read address of the speech control memory 7 is generated for each time slot. Therefore, from the call control memory 7 to the call path 3
The address corresponding to the time slot is read from the call control memory 7.

Then, according to the address, the call memory 2
While the call data and the parity data are read from, the parity checker 5 performs the parity test.
By sequentially performing this operation, the call data and the parity data of each time slot on the call path 3 are read.

However, the above operation is normally performed only for the time slot based on the path setting instruction of the time slot of the communication path 1 and the time slot of the communication path 3.
Since the processing is switch path connection from software, path connection information is written in the call control memory 7 under the control of a processor (not shown). That is, the processor (not shown) writes the time slot number of the communication path 1 as address data and the time slot number of the communication path 3 as write data in the communication control memory 7.

All the time slots of the communication path 1 are not always used, and some of them are empty. Therefore, a specific time slot of the communication path 3 (TSn in this example)
The following configuration is used to perform a parity test.

That is, a test counter 9 is provided, and the test counter 9 starts its operation when a synchronizing signal is sequentially supplied from the counter 8 through the signal line a, and generates an output signal in synchronization with the test counter 8. The output signal is transmitted for a period slightly exceeding at least one frame. On the other hand, the sequential counter 8 outputs the trigger signal via the signal line b when the address signal generated therein becomes TSn-1, and outputs the trigger signal via the signal line c when the address becomes TSn. I have to. The selector 10 sends the output signal from the test counter 9 for one frame after the trigger signal is supplied to the signal line c, but sends the signal output from the call control memory 7 for the other periods. I have to.

With this configuration, the call memory read address read from the call control memory 7 and the call memory read address generated from the test counter 9 are supplied to the input side of the selector (SEL) 10. However, the selector 10 normally outputs the signal output from the call control memory 7, and the signal output from the test counter 9 for only one frame period after the trigger signal is supplied via the signal line c. Is output.

Therefore, normally, data is read only from the time slot designated by the address signal read from the call control memory 7, and the call control memory 7 requires path connection. Only the address signals are written. Therefore, as it is, the timeslots that are less frequently used are less frequently tested for normality as in the conventional case.

However, at the timing when the sequential counter 8 designates the test time slot TSn, the selector 10 disconnects the call memory read address signal output from the call control memory 7 and replaces it with the test counter 9.
From the call memory read address signal. As described above, the test counter 9 sends the call memory read address synchronized with the time slot of the call path 3 for at least one frame period, so that the information of all time slots is read from the call memory 2 and the parity is read. Tested on checker 5.

The test counter 9 outputs an address signal for one frame or more, then stops its operation, and the selector 10 disconnects the signal from the test counter 9 after the elapse of the period for one frame, and outputs the signal from the call control memory 7. Is sent, the normal operation is performed after the test is completed. Then, when the test time slot is reached again, the same test is performed.

FIG. 2 is a highway correspondence diagram. Control of the input highway time slot TS1 to the output highway HW0, the input highway time slot TS2 to the output highway HW1, and the input highway time slot TS3 to the output highway HW2 by processor control. The path is set, and thereafter, information is similarly assigned to the time slot. Further, the output highway HWn is subjected to the above-described operation for each frame by the time slot TS0 to T of the input highway.
Information up to Sn is automatically supplied.

[0018]

As described above, according to the inventions of claims 1 to 3, a specific time slot is determined as a test time slot, and when the time slot becomes a designated timing, all the time slots of the call memory are allocated. Since the data is read sequentially and a parity test is performed, 1
All time slots are tested for each frame, and all time slots are always tested, so that even if a failure occurs, it can be found immediately.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing time slot information of the device of FIG.

FIG. 3 is a diagram showing an example of a conventional device.

[Explanation of symbols]

1, 3 ... Call path, 2 ... Call memory, 4 ... Parity adder, 5 ... Parity checker, 6, 8 ... Sequential counter, 7
... call control memory, 9 ... test counter, 10 ... selector.

Claims (3)

[Claims] 1. In a time-division switch test method for testing a time-division switch for reading data stored in a call memory with data output from a call control memory, a specific time slot is determined as a test time slot, and the time is determined. A time-division switch test method in which data for all time slots of the call memory are sequentially read and tested when a slot is allocated. 2. A time-division switch test method for testing a time-division switch for reading out data of the call memory stored at an address determined by data output from the call control memory, wherein an address corresponding to a signal supplied is used. A call control memory for reading the stored data, a sequential counter for supplying sequentially changing address data to the call control memory, a test counter that operates in synchronization with the operation of the sequential counter, and a call control memory output Or a selector which selects and outputs one of the test counter outputs, and the selector outputs the test counter output signal from the call memory to all time slots when the output signal of the sequential counter selects a specific time slot. The test counter output until the data of Division switch testing system when and supplying a signal to the call memory. 3. The time division switch test method according to claim 1, wherein the call memory is tested by a parity check.