JPH03267897A - Memory switch monitoring system - Google Patents

Abstract

PURPOSE:To monitor a data memory area repetitively without connection by providing a time slot for exclusive use of parity check to a readout time slot of a memory switch and reading all areas of the data memory so as to apply the parity check. CONSTITUTION:An 8 time slot memory switch consists of a parity provision section 11, a data memory 12, a parity check section 13, a readout changeover selector 14, an address control memory 15, a sequential counter 16, a selector 17 and a check address counter 18. Then a check selector 17 is provided, which receives a parity check time slot signal setting one of time slots as an exclusive parity check use so as to replace the random readout address of an output signal with an output address of a check address counter 18 setting a same spatial address as a write address of the input signal. Thus, even a data memory area with no connection is monitored.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention monitors time-division multiplexing devices and time-division switching equipment that make up a telecommunications network, and which connect and exchange digital signals. This invention relates to a memory switch monitoring method.

[Conventional technology]

The conventional memory switch monitoring method assigns parity to the input signal on the input side and writes it as a parity bit to the same address as the input signal in the data memory, and on the output side reads it at a random read address (connection destination address) from the address control memory. The parity of the signal was checked, and this was used to monitor the memory switch.

The prior art will be explained with reference to FIGS. 1 and 3. FIG. 1 is a block diagram showing an embodiment of the present invention. Conventionally, in FIG. 1, the parity adding section 11. Data memory 12. Parity check section 13. Continuous switching selector 1
4. It has an address control 15 and a sequential counter 16, but does not have a check selector 17 and a check address counter 18. Therefore, the random read address output from the address control memory 15 is directly input to the read switching selector 14.

In FIG. 3, input time slot numbers 1 and 3 of the data memory 12 in FIG. 1 are respectively output time slot numbers 3 and 3.
The input time slot numbered 0 and 8 is a special time slot that outputs specific data when there is no connection to the output time slot, and the address control memory Since the address of this time slot is written in 15 as an initial value, the address as an initial value is output in an output time slot where there is no connection.

Time slot numbers 1 to 1 entered in the data memory 12
The input signals A-H of 8 are the address O of the data memory 12.
~7 are sequentially written. On the output side, signals A to C read from the data memory 12 at the corresponding address are output to time slot numbers 3 and 4 with connections, and signal H to address 7 is output to the remaining time slots with no connections. Read out. Therefore, the area of the data memory 12 where the parity check is performed is at addresses 0 and 2.
・For example, parity check is not performed for address 6.

The abnormality of address 6 is when address 6 is used,
Unless lines are added, there is almost no chance of it being used, and failures that occur when used for the first time often pose a serious hindrance to network operation.

[Problem to be solved by the invention]

The conventional memory switch monitoring method described above has a structure in which a parity check is performed on connected addresses, so there is a problem that unconnected data memory areas cannot be monitored.

An object of the present invention is to provide a memory switch monitoring method that solves the above problems.

[Means to solve the problem]

The basic configuration of the memory switch monitoring method of the present invention is to add parity to an input signal, write it sequentially to the same address as the input signal of the data memory as a parity bit, and read out the parity of the signal at a random successive address output from the address control memory. In the memory switch monitoring method that performs checking, a parity check time slot signal is input that sets one of the time slots exclusively for parity checking, and the output of a check address counter that sets an address in the same space as the write address of the input signal. It has a check selector that changes the random read address of the output signal depending on the address.

One of the specific means of the memory check monitoring method of the present invention is as follows.
The parity check time slot signal sets the 8th bit data address for the 8-bit data memory for parity check.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the 8 time slot memory switch is
Parity assigning unit 11. Data memory 12. Parity check section 13. Read switching selector 14, address control memory 15. Sequential counter 16. Selector 1
7. and a check address counter 18.

The parity adding section 11 adds parity to each input signal and sequentially writes it as a parity bit to the same address of the input signal in the data memory 12. The parity checking section 13 checks the parity bit output from the data memory 12 for each output signal. When an error is detected, an error signal is output. The successive output switching selector 14 switches between a write address and a read address and outputs the same to the data memory 12. The address control memory 15 receives the write address of the input signal at the output of the sequential counter 16 and outputs a random read address for extracting the output signal from the data memory 12. The check selector 17 inputs the parity check address output from the check address counter 18 and the random read address output from the address control memory 15, and selects the parity check address upon reception of the parity check time slot signal. Then, it is output to the continuous output switching selector 14.

FIG. 2 is a time chart showing an example of the time relationship between time slot replacement and parity check according to FIG. 1.

Next, a description will be given with reference to FIG. 2 and FIG. 1 together.

In FIG. 2, input signals A to H of time slot numbers 1 to 8 are given parity by a parity giving unit 11, outputted by a sequential counter 16, and sent to a data memory 1 by a write address via a successive changeover selector 14.
2 are sequentially written to addresses 0 to 7. On the output side, as shown in Figure 2, there is a time slot number 3 with connection.
Time slot numbers 1 and 3 are assigned to each output signal of 4.
Each input signal A-C is read out. For unconnected time slot numbers, the signal H at address 7 of the data memory 12 is sent to the data memory 12 for reading via the check selector 17 and the read switching selector 14 according to the random read address output from the address control memory 15. be done. The check address counter 18 increments by one step each time the sequential counter 16 completes one cycle and outputs the increment to the check selector 17. The check selector 17, which receives the time slot dedicated to parity check as a parity check time slot signal, supplies the sequentially changing address inputted from the check address counter 18 to the data memory 12 via the read switching selector 14, and sends a signal A to be stored. ~H are all detected sequentially. In other words, output signal A is sent to time slot number 8.
~H appear sequentially in each cycle.

Therefore, for example, when the input signal G of data memory address 6 is abnormal, the parity check unit 13 detects that the output signal G of time slot number 8 is faulty, even if there is no connection in and out of data memory address 6, the parity check is abnormal. can output an error signal.

The reason why the eighth bit is set for parity check in this embodiment is to utilize the bit position used for control signals in digital voice communication, and there is no particular limitation on the bit position in the system configuration.

〔Effect of the invention〕

As explained above, the present invention provides a time slot dedicated to parity check in the read time slot of a memory switch, sequentially gives addresses in the same space as the write address every cycle, reads out all areas of the data memory, By adopting a configuration that performs a parity check, it is possible to repeatedly monitor data memory areas that have no connection, and there is an effect that a highly reliable time division multiplexing device or the like can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing an example of the embodiment of the present invention, and FIG. 3 is a tom chart showing an example of the conventional technology. 11... Parity assigning unit, 12... Data memory,
13... Parity check unit, 14... Read switching selector, 15... Address control memory, 16...
- Sequential counter, 17...Check selector, 18...Check address counter.

Claims (1)

[Claims] 1. Adding parity to the input signal and sequentially writing it as a parity bit to the same address as the input signal of the data memory,
In a memory switch monitoring method that performs a parity check on a signal read at a random read address output from an address control memory, a parity check time slot signal that sets one of the time slots exclusively for parity check is input, and the input signal is 1. A memory switch monitoring system comprising a check selector that switches a random read address of an output signal with an output address of a check address counter that sets an address in the same space as a write address of the memory switch. 2. A memory switch monitoring system, wherein the parity check time slot signal according to claim 1 sets the data address of the 8th bit in an 8-bit data memory for parity check.