JP2693496B2 - Method for manufacturing dielectric isolation semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device having a dielectric isolation structure.

(Prior Art) When a device is formed using a dielectric isolation substrate, if a V groove is formed in the device isolation region during the insulating film etching process,
This affects the reliability and element characteristics of the semiconductor device.
This will be explained below by taking an example of using a dielectric substrate by a direct bonding technique of a Si wafer.

FIGS. 7A to 7C show the process up to the middle of the device forming process. The two Si wafers 1 and 2 are directly bonded and integrated with the oxide film 3 interposed therebetween. The element formation region side of the integrated substrate is adjusted to have a predetermined thickness by polishing or the like. Then, an element isolation groove for forming the island-shaped Si layer 6 (6 ₁ , 6 ₂ , ...) Is formed and an oxide film 4 is formed on the side surface thereof.
Then, the polycrystalline silicon layer 5 is embedded in the groove to obtain a dielectric isolation substrate. The separation groove is formed in a V shape by anisotropic etching using an alkaline etching solution.
P ⁺ type layers 7 and 8 are formed on the bottom and sides of each Si layer 6. This is for taking out the electrode on the p side. p ⁺
The mold layer 7 is formed in advance before the substrate is bonded, and the p ⁺ mold layer 8 is formed after forming the element isolation groove. First, a thick oxide film 9 of about 1 μm is formed on the entire surface of the dielectric isolation substrate.
Are formed (a). After that, the oxide film 9 is selectively etched, and impurities are ion-implanted using the remaining oxide film 9 as a mask to form a p ⁺ -type layer 11 to be a p-side electrode extraction region (b). In the step of etching the oxide film 9, since the oxide film 9 is thick and the etching time is long, the oxide film in the element isolation region is over-etched and a groove is formed in the element isolation region as shown in the figure. After that, thermal oxidation is performed with the oxide film 9 left. At this time, a step is formed on the surface of the part where the oxide film 9 was left and the part where the oxide film 9 was not left, and a trace is left at the boundary part between them. This acts as an alignment mark in the subsequent pattern formation. After that, the oxide film 9 on the entire surface is removed so as to prevent the impurities injected into the oxide film 9 from being diffused into the semiconductor layer in the subsequent thermal process.
Is formed (c). At this time, the oxidation also proceeds to the silicon layer 6 and the polycrystalline silicon film 5, and the trench 71 in the element isolation region further expands as shown in FIG. 7C. Then, when the wiring is formed on this, the wiring 13 causes a step break in the groove portion of this element isolation region as shown in FIG. Further, when the wiring 13 is, for example, a gate electrode wiring of a MOS type element made of a polycrystalline silicon film, even if the wiring is connected without causing a step break as shown in FIG. At this time, impurities are not introduced into the element isolation groove portion, and as a result, an anti-series circuit of the diode as shown in FIG. 9B is formed in this portion. If this enters in series with the gate terminal, there is a problem that the gate potential of the MOS type device is not fixed and the gate potential becomes unstable.

(Problems to be Solved by the Invention) As described above, in the element formation using the conventional dielectric isolation substrate, a groove is formed in the element isolation region, which causes deterioration of reliability and element characteristics. There was a problem.

It is an object of the present invention to provide a method for manufacturing a dielectric isolation semiconductor device that solves such problems.

[Configuration of the Invention] (Means for Solving the Problems) A method for manufacturing a dielectric isolation semiconductor device according to the present invention is
A step of forming a dielectric isolation substrate in which a plurality of island-shaped semiconductor layers for forming S-type elements are separated by an insulator; a step of forming an insulating film on the dielectric isolation substrate; A step of selectively etching the insulating film in a part of the element isolation region to form a V groove, and a non-oxidizing film is selectively formed on the insulating film. A step of selectively oxidizing, a step of selectively implanting impurities into a semiconductor layer to form a desired element diffusion layer, and a step of depositing a polycrystalline silicon film on the substrate and introducing impurities to form a gate electrode wiring At the same time, the method further includes the step of forming an anti-series circuit of the diode across the V groove continuously with the gate electrode wiring, and the step of forming a contact hole in the insulating film to form source and drain electrode wiring. Characterize.

(Operation) According to the present invention, in the element isolation region of the dielectric isolation substrate,
Unnecessary grooves are not formed, and therefore disconnection of the wiring crossing the element isolation region is prevented. Further, when the gate electrode wiring that crosses the element isolation region is formed, the series circuit of diodes does not enter the gate terminal, and stable element characteristics can be obtained.

Further, according to the present invention, by etching the insulating film formed first in a part of the element isolation region, MO
The protection diode required between the gate and source of the S-type element can be easily realized. That is, the polycrystalline silicon film of the gate electrode wiring material may be disposed across the grooved portion of the element isolation region so that one end is connected to the gate electrode and the other end is connected to the source electrode.

(Example) Hereinafter, an example of the present invention will be described.

FIGS. 1A to 1D show the element manufacturing process of one embodiment. In this embodiment, a case where a diode is made as an element is shown. The dielectric isolation substrate is formed by directly bonding Si wafers 1 and 2 in this embodiment, as in the conventional example described in FIG. Therefore, the portions corresponding to those in FIG. 7 are designated by the same reference numerals and detailed description thereof will be omitted. First, a silicon oxide film 9 is formed on the entire surface of the dielectric isolation substrate, and then a silicon nitride film 10 is further formed thereon (a).
Here, the oxide film 9 is thin, about 0.1 μm, unlike the conventional one. After that, the nitride film 10 is selectively etched using the oxide film 9 as an etching stopper. Then, a photoresist pattern covering the nitride film 10 is formed and boron is ion-implanted while leaving the oxide film 9 using the photoresist pattern as a mask to form the p ⁺ -type layer 11 (b). Next, the entire substrate is thermally oxidized with the nitride film 10 left. At this time, the nitride film 10
The oxide film is not formed underneath, and the oxide film 9 becomes thicker in the portion not covered with the nitride film 10. After that, the nitride film 10 is removed (c). Oxide film 9 remain thickened portion 9 ₁ of the boundary in the subsequent thermal oxidation and a thin portion 9 ₁ covered with the nitride film 10 becomes the trace. Then, next, using the trace of the difference in the film thickness of the oxide film 9 as an alignment mark, the n ⁺ -type layer 12 which becomes the cathode of the diode is formed in the island-shaped Si layer 6 by ion implantation through the oxide film 9. To form. Finally, a contact hole is formed, and the wiring 13 is formed of an Al film (d).

Thus, in this embodiment, the oxide film 9 initially formed on the isolation region of the dielectric isolation substrate is left without being removed in the element process. Therefore, unnecessary V-grooves are not formed in the element isolation region, and disconnection of the wiring is prevented.

FIGS. 2A to 2D show an embodiment applied to the lateral insulated gate bipolar transistor (IGBT) of the present invention. The parts corresponding to those in the previous embodiment are designated by the same reference numerals as those in the previous embodiment, and detailed description will be omitted. Also in this embodiment, the dielectric isolation substrate is formed by the direct bonding technique, the oxide film 9 is first formed on the entire surface, and then the nitride film 10 is formed thereon (a). Next, the photoresist pattern 21 (21 ₁ , 21 ₂ ,
...) is formed, and the nitride film 10 is selectively etched using this as a mask, and then boron ions are implanted with the photoresist pattern 21 left to form a boron / ion implantation layer 22 (b). The photoresist patterns 21 ₂ and 21 ₃ formed on the polycrystalline silicon layer 5 in the element isolation region are
It is for forming alignment marks. After that, the photoresist pattern 21 is removed, and the remaining nitride film 10 is used as an alignment mark for another photoresist pattern 23 (23
_{, 1} , ₂ , 3) are formed, and phosphorus is ion-implanted into the n-type layer formation planned region to form a phosphorus / ion-implanted layer 24 (c). After that, the photoresist pattern 23 is removed, and thermal oxidation is performed so that the oxide film 9 remains thin under the nitride film 10.
₁ and a thick oxide film 9 ₂ and simultaneously activate impurities to form p ⁺
A mold layer 25 and an n ⁻ type base layer 26 are formed (d). Then, a lateral IGBT is formed according to a normal process (e). That is, p
^A p-type base layer 25 is formed in contact with the ⁺ -type layer 25, and an n ⁺ -type source layer 29 is formed therein. A gate electrode 27 is formed of a polycrystalline silicon film on the n ⁺ type source layer 29 and the n type base layer 26. An n-type buffer layer 30 and a p ⁺ -type drain layer 31 are formed in the n-type base layer 26. Then, the entire surface is covered with a CVD oxide film, contact holes are opened, and a source electrode 33 and a drain electrode 34 are formed.

According to this embodiment, the same effect as the previous embodiment can be obtained. Although not shown in the figure, when the gate electrode 27 crosses the element isolation region, the diode series circuit as described above is not formed in that portion, and excellent element characteristics are obtained.

FIGS. 3A to 3E show an example in which a lateral IGBT similar to the above example is formed without using a nitride film. In this example, the same 0.1-μm layer was used on the surface of the dielectric isolation substrate as in the previous example.
After forming a thin oxide film 9 having a thickness of about μm, the oxide film 9 is selectively etched in the element isolation region, and the buried polycrystalline silicon layer 5 is etched using the remaining oxide film 9 as a mask.
An alignment mark 35 for the following element process is formed (a). Next, a photoresist pattern 36 is formed to form a boron ion implantation layer 22.
Photoresist pattern again by removing pattern 36
Then, 37 is formed to form the phosphorus ion-implanted layer 24 (c).
Then, the photoresist pattern 37 is removed, and thermal oxidation is performed to thicken the oxide film 9 and at the same time activate impurities to form the p ⁺ -type layer 25 and the n ⁻ -type base layer 26 (d).
A thin oxide film is formed on the alignment mark 35,
Mark 35 remains. After this, a lateral IGBT similar to that of the previous embodiment is formed according to a normal process (e). In the gate part,
The oxide film 9 is once selectively etched to form a thin gate insulating film.

According to this embodiment, the same effect as that of the previous embodiment can be obtained.

FIGS. 4A to 4C are lateral IGBTs according to other embodiments.
It is. This is an embodiment in which the diode series circuit described in FIG. 9 is partially formed in the element isolation region and is positively utilized. (A) is a plan view, (b) and (c) are 3A and 3B are cross sections taken along line AA ′ and BB ′ of FIG. The steps described in the embodiment of FIG. 2 or 3 above are used for the main steps of IGBT formation. The different point from the previous embodiment is that the polycrystalline silicon wiring 41 branched from the gate electrode 27 and arranged below the source electrode 34 is patterned, and the polycrystalline silicon wiring 41 crosses the element isolation region. In the portion, the V film is formed by removing the oxide film 9 formed first by selective etching in advance. By doing so, the polycrystalline silicon wiring 41 is connected to the V of the element isolation region.
When arsenic is ion-implanted into the groove and arsenic is ion-implanted into the groove, a series circuit of diodes is formed as described above. The other end of the polycrystalline silicon wiring 41 is brought into contact with the source electrode 33.

The IGBT thus obtained has a form in which a series circuit of diodes is inserted between the gate and the source as shown in the equivalent circuit of FIG. The series circuit of this diode works as an overvoltage protection circuit. That is, according to this embodiment, the overvoltage protection circuit is formed integrally with the device.

The same structure is applicable not only to IGBT but also to all MOS type semiconductor devices such as MOS transistors.

In the above embodiments, the dielectric isolation substrate based on the direct bonding technique has been mainly described, but the present invention is also effective when a dielectric isolation substrate based on another method is used. For example, in Figure 6,
A case where a diode is formed in the same manner as in the embodiment of FIG. 1 is shown by using a dielectric isolation substrate which is lined with a polycrystalline silicon layer 60 and in which a plurality of island-shaped Si layers 6 are separately formed.

As described above, according to the present invention, in the manufacturing process of the semiconductor device having the MOS type element using the dielectric isolation substrate, the insulating film formed on the substrate surface is left first. Thus, it is possible to prevent useless grooves from being formed in the element isolation region, and to obtain a highly reliable semiconductor device having excellent characteristics.

Further, according to the present invention, by selectively removing a part of the first insulating film in the element isolation region and positively utilizing the fact that the groove is formed in this part in the element forming process, the MOS type is formed. A protection circuit can be easily inserted between the gate and source of the device. The control of the overvoltage value of the overvoltage protection diode by the polycrystalline silicon film provided in the isolation region can be performed by controlling the concentration of p-type and n-type impurities with which the polycrystalline silicon film is doped.

[Brief description of the drawings]

1 (a) to (d) are cross-sectional views showing a diode manufacturing process of an embodiment of the present invention, and FIGS. 2 (a) to (e) are cross-sectional views showing an IGBT manufacturing process of another embodiment, Fig. 3 (a) ~
FIG. 4E is a sectional view showing an IGBT manufacturing process of another embodiment, FIG.
(A) to (c) are plan views showing the structure of an IGBT according to another embodiment and cross-sectional views AA 'and BB' thereof, FIG. 5 is an equivalent circuit diagram of the IGBT, and FIG. 7 is a cross-sectional view showing a diode of another embodiment, FIGS. 7A to 7C are cross-sectional views showing a manufacturing process of a conventional dielectric isolation semiconductor device, and FIG. 8 is a view for explaining a problem of the conventional process. Sectional view of Fig. 9 (a)
(B) is a sectional view and an equivalent circuit diagram for explaining other problems. 1,2 …… Si wafer, 3,4 ………… Silicon oxide film, 5 …… Polycrystalline silicon layer, 6 …… Insular Si layer, 7,8 …… P ⁺ type layer, 9 ……
Silicon oxide film, 10 …… Silicon nitride film, 11 …… P ⁺ type layer,
12 …… n ⁺ type layer, 13 …… electrode wiring, 21,23 ………… photoresist pattern, 25 …… p ⁺ type layer, 26 …… n ⁻ type base layer, 27 …… gate electrode, 28 ...... p type base layer, 29 ...... n ⁺ type source layer, 30 …… n type buffer layer, 31 …… p ⁺ type drain layer, 33 …… CVD oxide film, 33 …… source electrode, 34 …… drain Electrodes, 35 ... alignment marks, 36, 37 ... Photoresist pattern, 41 ... Polycrystalline silicon wiring, 60 ... Polycrystalline silicon layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shojiro Tanzawa 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research Institute, Inc. (72) Inventor Harunobu Akihiro 1-shi Toshiba-cho, Fuchu-shi, Tokyo Toshiba FA System Engineering Co., Ltd. (56) Reference JP 62-247534 (JP, A) JP 61-191042 (JP, A)

Claims (1)

(57) [Claims] 1. A step of forming a dielectric isolation substrate in which a plurality of island-shaped semiconductor layers to form a MOS type element are separated by an insulator, and a step of forming an insulating film on the dielectric isolation substrate. A step of selectively etching an insulating film in a part of the element isolation region of the dielectric isolation substrate to form a V-groove; and a non-oxidizing film is selectively formed on the insulating film. A step of selectively oxidizing the semiconductor layer with a mask; a step of selectively implanting an impurity into the semiconductor layer to form a desired element diffusion layer; a step of depositing a polycrystalline silicon film on the substrate and introducing an impurity into the gate; At the same time as forming the electrode wiring, a step of forming an anti-series circuit of the diode across the V groove continuously with the gate electrode wiring, and a step of forming a contact hole in the insulating film to form source and drain electrode wiring Characterized by having Method of manufacturing that the dielectric isolation semiconductor device.