JPS62247534A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a thick, uniform, flattened, high-quality thermal SiO2 film by a method wherein an element region is formed, the surface except an exposed dielectric film is etched by a prescribed depth, and then thermal oxidation is accomplished for the formation of a thick silicon oxide film on the surface. CONSTITUTION:A surface containing an element region T is subjected to etching in a liquid that is a mixture, for example, of hydrofluoric acid, nitric acid, and ammonium fluoride for the removal of a thickness of approximately 1mum from the surface of the element region T and a polycrystalline silicon layer S. Next, the surface is subjected to thermal oxidation for the formation of an SiO2 film 11. Phosphorus ions are selectively implanted into a collector contact forming region, after which a base forming region and the collector contact forming region are covered by an Si3N4 film 12. Next, the Si3N4 film 12 is removed, ions of an n-type impurity for example of boron are implanted into the base forming region, and then thermal treatment is accomplished for the formation of a base region 4. Further, an opening is provided in an emitter forming region, ions of a p-type impurity for example of phosphorus are implanted into the opening and then thermal treatment is accomplished for the formation of an emitter region 4.

Description

Detailed Description of the Invention [Summary] In a method for manufacturing a high voltage IC that uses a co-crystalline substrate (bulk) as an element region and is dielectrically isolated, after forming the element region, the surface is etched to a predetermined film thickness, and then thermal oxidation is performed. to form a silicon oxide film on the surface. Then, a silicon oxide film having a uniform thickness is formed with a flattened surface.

[Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a high breakdown voltage 1c by dielectric separation.

High-voltage ICs are known that are based on polycrystalline silicon, insulate and separate semiconductor elements with a dielectric film (commonly called the DI method), and use the crystal substrate as the element region. A high breakdown voltage element can be fabricated in the element region thus obtained, and an extremely excellent tC performance can be obtained.

Therefore, for example, LSIs for subscriber line circuits (SLICs) accompanying the electronicization of telephones require a high withstand voltage of several hundred volts, and ICs with extremely high reliability are required.
By applying the above-described manufacturing method, a high voltage IC with dielectric separation is formed.

However, when manufacturing such high voltage ICs,
There are problems specific to this manufacturing method, such as the difficulty in making the insulating film on the surface uniform and flat, and countermeasures are desired.

[Prior art] Figure 2 shows a cross-sectional structure diagram of a high voltage IC using dielectric isolation, where I is a silicon oxide (Si02) film (dielectric isolation film), S is a polycrystalline silicon layer, and T is an element. In the element region T, 1 is an n+ type buried layer, 2 is an n-type collector region, 23 is a p-type base region, 4 is an emitter region, 5 is a collector contact region, 4C and 5C are an emitter electrode and a collector electrode, respectively. It is.

Figure 3 (a
) to (d), and first, (a) shows the known D
I (Dielectric l5olation)
FIG. 3 is a diagram in which an element region T is formed by a method (also referred to as an EPLC method). The same symbols are attached to the same parts as in FIG. 2.

Next, as shown in FIG.
A window is opened in the 02 film, boron ions are implanted, and a base region 3 is defined by heat treatment. Next, as shown in FIG. 1C), windows for emitter and collector contacts are opened, and a phosphosilicate glass (PSC) film 7 is deposited and patterned.

Next, as shown in FIG. 3 (dl), phosphorus is diffused through the emitter window and heat treated to form the emitter region 4. At the same time, phosphorus is diffused from the PSGli 7 to define the collector contact region.

Thereafter, the 5LO2 film 6 and the PSG film 7 are opened to form electrodes, and a high voltage IC is completed.

[Problems to be Solved by the Invention] By the way, the reason why the PSG film is further deposited on the 5i02 film as described above is to use the PSG film as a diffusion source for the collector contact region. The purpose is to thicken the insulating film on the surface, and in this way, the dielectric strength is sufficiently maintained to prevent electric field concentration from occurring on the surface.

However, when the PSG film is deposited by chemical vapor deposition,
It is easy for dust and foreign matter to get into the G film, so PSG
Pinholes and pattern collapse may occur in the film. Furthermore, since the PSG film is easily etched, it is difficult to control the etching. Furthermore, since the PSG film 7 is selectively deposited on the 5LO2 film 6, the level difference on the surface increases. Therefore, adhering a PSG film to the surface of a high-voltage EC is not very desirable from the viewpoint of quality and reliability.

Therefore, 5i02 by thermal oxidation can be achieved without using a PSG film.
When trying to form the film 6 thickly, 5t0 for dielectric isolation
Since the 5i02 film 6 is not generated in the exposed portion of the 2 film I, the 5i02 film 6 becomes a recess and a step is formed there, and there is a fear that the wiring formed on the upper surface thereof may be disconnected.

The present invention solves these drawbacks and proposes a method for forming a high voltage IC with high quality and high reliability.

[Means for solving the problem] The purpose is to remove the surface including the dielectrically isolated element region by a predetermined thickness except for the silicon oxide film,
This is achieved by a method for manufacturing a semiconductor device that includes the steps of masking the base formation region and the collector contact formation region with an etching-resistant film (for example, a silicon nitride film), and thermally oxidizing the region to form a silicon oxide film on the surface. .

[Operation] That is, in the present invention, after forming an element region, the surface, excluding the exposed dielectric film, is etched to a predetermined thickness, and then thermally oxidized to form a thick silicon oxide film on the surface.

This results in high-quality heat generation that is uniform and flat on the surface.
A thick LO2 film is formed.

[Example] Examples will be described in detail below with reference to two drawings.

FIGS. 1(a) to 1(el) are sectional views in the order of forming steps of the forming method according to the present invention. First, FIGS.
Similarly to the figure, the element region T is formed by the known DI method.

Next, as shown in FIG. 1 (bl), the surface including the element region T is etched with, for example, a mixed solution of hydrofluoric acid, nitric acid, and ammonium fluoride to form the element region T and the polycrystalline silicon layer S.
The surface of the film is removed by steps of approximately 1 μm in thickness. At this time, the St○2 film I of the dielectric isolation film is difficult to be etched and remains protruding as shown in the figure.

Next, as shown in FIG. 1 (C1), the surface was thermally oxidized to form a 5i02 film 11 with a thickness of approximately 1000 nm, and phosphorus ions were selectively implanted into the collector contact formation region (
(indicated by black dots), the base formation region and collector contact formation region are made of silicon nitride (Si3 N4).
Cover with membrane 12.

Next, as shown in FIG. 1 (dl), thermal oxidation is performed to form a 5i02 film 13 with a thickness of about 2 μm including the 5i02 film described above. At this time, the base forming region and the collector covered with the 5L3N4 film 12 are 5i in the contact formation area
02 film 13 is not generated, and collector contact region 5 into which phosphorus ions are implanted is defined by heating.

Next, as shown in FIG. 1(e), the Si3N4 film 12
is removed, a photo process is applied to ion-implant an n-type impurity, such as boron, into the base formation region, heat treatment is performed to form the base region 4, and the emitter formation region is opened to form a p-type impurity. For example, phosphorus is ion-implanted and heat treated to form the emitter region 4. After that, each electrode is formed to complete the high voltage rc.

Now, if formed as described above, a thick 5i02 film 13 can be formed without using a PSG film. Moreover, on the exposed surface of the Si○2 film I, 5i02
Although the film 13 is not produced, the 5i02 film 2 has a protruding shape in that part, and the 5i02 film fills the conventional concave part. Therefore, the surface is flattened with a thick 5N)2 film.

Furthermore, in the above embodiments, the ion implantation for the collector contact region is performed in the initial process, but a method may be adopted in which this is performed simultaneously with the formation of the emitter region in the latter process. Furthermore, although ion implantation is used for impurity diffusion in this embodiment, thermal diffusion may also be used.

Therefore, according to the formation method according to the present invention, a thick film of 5.
By forming an i02 film, the surface can be made flat and uniform.

[Effects of the Invention] As is clear from the description of the embodiments above, the present invention has a remarkable effect on improving the quality and reliability of a high voltage RC due to dielectric separation.

[Brief explanation of drawings]

Figure 1 (al ~ (81 is a cross-sectional view of the formation process according to the present invention), Figure 2 is a cross-sectional structural diagram of a high voltage IC using dielectric separation, Figure 3 (al~ (di is a conventional formation method) 1 is a cross-sectional view of the formation process of the method. In the figure, T is an element region, S is a polycrystalline silicon layer, ■ is a Si[2 film (dielectric isolation film), 1 is an n+ type buried layer, 2 is a collector region, 3 is the base region, 4 is the emitter region, 5 is the collector contact region, 6, 11.13 is the 5i02 film, 12 is the Si3N4 film half-diamond F3 small ZppZ'FIJ, 49th month r; v・v・s 19 A /T>l
q＠l'x'工# 'J* h°imFigure 1 High voltage IC design Figure 2

Claims (1)

[Claims] In a method for manufacturing a high-voltage IC having an element region made of a silicon substrate separated by a dielectric film, the surface including the dielectric-separated element region is etched away by a predetermined film thickness except for the silicon oxide film, and then, 1. A method for manufacturing a semiconductor device, comprising the steps of masking a base formation region and a collector contact formation region with an etching-resistant film and thermally oxidizing them to form a silicon oxide film on the surface.