JP2768914B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of manufacturing a semiconductor integrated circuit device having a capacitor element.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device in which an integrated circuit such as a logic circuit is formed by combining a bipolar transistor element and a capacitor element is known. A conventional semiconductor integrated circuit device having a bipolar transistor element and a capacitor element will be described with reference to FIG.

As shown in FIG. 1, a semiconductor integrated circuit device has a P
The semiconductor device includes a semiconductor substrate 1 and an N-type epitaxial layer 2 provided on the semiconductor substrate 1. The bipolar transistor element 20 includes a P ⁺ type diffusion region 21 and an N ⁺ type diffusion region 22 formed in the epitaxial layer 2, and an N ⁺ type diffusion region 23 formed in the P ⁺ type diffusion region 21. I have. Electrodes 24, 25, and 26 are provided for forming contact holes in oxide film 10 formed on the surface of epitaxial layer 2 and electrically connecting to respective diffusion regions.

The capacitor element 40 includes an N ⁺ -type diffusion region 41 formed in the epitaxial layer 2, the oxide film 10 formed on the diffusion region 41, and an electrode 42 formed on the oxide film 10. It is configured.

[0005]

In the above-described semiconductor integrated circuit device, as shown in FIG. 3, the thickness of the oxide film 10 formed on the region to be the bipolar transistor element 20 is formed on the epitaxial layer 2. Diffusion regions 21 and
Depending on the depths of 2, 23, for example, w1 and w2, the thicknesses are different as a (= 5000 to 10000) and b (= 1000 to 5000).

As shown in FIG. 4A, in the case of a bipolar transistor element, impurities are implanted into the epitaxial layer 2 through the opening of the oxide film 10 and then heat treatment is performed as shown in FIG. The diffusion region 11 is formed. The time of the heat treatment at this time is longer in accordance with the depth of the diffusion region 11 at the time of driving in the impurity. However, this heat treatment is usually performed by using an oxide film for securing an inversion voltage and a dielectric strength of the oxide film. The thickness of the oxide film 10 'on the diffusion region 11 increases as the heat treatment time increases.

Therefore, in the semiconductor integrated circuit device shown in FIG. 3 where the thickness of the oxide film 10 in the region of the bipolar transistor element 20 is different, when an electrode is formed by providing an opening by anisotropic etching, the thickness is particularly small. In the electrode 24 formed in the thick region, a coverage failure occurred at the step portion 27, and the electrode was disconnected. In order to solve this, as shown in FIG. 5, a masking process is performed once before forming an electrode, isotropic etching is performed on the thick oxide film 10 on the bipolar transistor element 20 region, and a taper is formed. The part 12 is formed. Thereafter, openings are formed in the oxide film 10 on the bipolar transistor element 20 by anisotropic etching to form the electrodes 24, 25, and 26, and the electrode 42 is also formed on the oxide film 10 for the capacitor element 40. Was.

However, in this method, since the tapered portion 12 is formed in the thick oxide film 10 on the region of the bipolar transistor element 20 through the masking process again, the process is complicated and the cost is increased. Has occurred. The present invention has been made in view of the above-described problems, and provides a method of manufacturing a semiconductor integrated circuit device, particularly a method of manufacturing a semiconductor integrated circuit device including a capacitor element, capable of simplifying steps and reducing costs.

[0009]

The present invention has the following configuration to achieve the above object. That is, according to the method of manufacturing a semiconductor integrated circuit device of the first aspect, in the method of manufacturing a semiconductor integrated circuit device having a capacitor element, an insulating film for the capacitor element is formed on the oxide film on the diffusion region of the capacitor element region. Forming a tapered portion in a thick oxide film in another element region at the same time as forming an opening for forming a capacitor element, forming an insulating film for a capacitor element, and forming an opening in the oxide film in another element region. Forming a portion and forming an electrode in the capacitor element region and other element regions.

[0010]

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, an opening for forming an insulating film for a capacitor element, which has been conventionally performed using another mask, that is, using a different mask, and a bipolar process. By simultaneously forming the tapered portion of the thick oxide film in the transistor element region (= the same mask), the tapered portion can be formed without passing through the masking process again.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor integrated circuit device according to the present invention will be described with reference to FIG. Note that the same reference numerals are given to the same or corresponding parts as in the related art. First, FIG.
As shown in (1), an N-type epitaxial layer 2 is grown on the surface of a P-type semiconductor substrate 1. Then, P ⁺ is added to the epitaxial layer 2 serving as the region of the bipolar transistor element 20.
After forming the type diffusion region 21, an N ⁺ type diffusion region 22 and an N ⁺ type diffusion region 23 are formed in the bipolar transistor element 20. In the bipolar transistor element 20, N ⁺
The diffusion region 23 acts as an emitter, the P ⁺ diffusion region 21 acts as a base, and the epitaxial layer 2 acts as a collector.

Further, an N ⁺ type diffusion region 41 is formed in the epitaxial layer 2 to be a region of the capacitor element 40. On the surface of the epitaxial layer 2 of the semiconductor integrated circuit device, an oxide film 10 having a thickness corresponding to the depth of the diffusion region, that is, the heat treatment time for diffusion is formed. This is because the oxidation process is performed at the same time as the drive-in in order to secure the inversion voltage, the dielectric strength of the oxide film, and the like. The thickness of the oxide film 10 is particularly large in the diffusion region 21 (base) requiring deep diffusion.
The thickest is 5000-10000Å, and the diffusion area 2
On 2, 23, 41, it is 1000-5000 °.

Next, as shown in FIG.
The resist 13 is coated on the diffusion region 41 of the capacitor element 40 and the diffusion area 21 of the bipolar transistor element 20 by applying a resist 13 to the resist 13 and exposing and developing the resist.
An opening is formed in 3. Next, isotropic etching is performed by using an etching solution such as HF to form an opening in the oxide film 10 on the diffusion region 41 and to form an opening in the diffusion region 21.
A tapered portion 12 is formed on the upper oxide film 10.

As described above, the formation of the opening for forming the oxide film 10 for the capacitor element 40 and the formation of the tapered portion 12 of the thick oxide film 10 in the region of the bipolar transistor element 20 are performed simultaneously (= The same mask), the tapered portion 1 without passing through the masking process again
2 is realized. Next, as shown in FIG. 1C, after the resist on the oxide film 10 is removed, a heat treatment is performed (at a temperature of 800 to 1000 ° C. for 5 to 20 minutes), and the surface of the diffusion region 41 of the capacitor element 40 is exposed. 500 ~ 2000
酸化 An oxide film (= insulating film) is formed.

Next, as shown in FIG.
A resist 14 is applied on the top surface of the bipolar transistor element 20 and subjected to exposure and development processing.
An opening is formed in the resist 14 on 1, 22, 23.
Next, anisotropic etching is performed by a dry etching method such as RIE (reactive ion etching) or plasma etching to form an opening for forming an electrode in the oxide film 10 on the diffusion regions 21, 22, 23. .

Finally, as shown in FIG. 2E, after the resist on the oxide film 10 is removed, the diffusion region 2 of the bipolar transistor element 20 is formed by vapor deposition or sputtering.
Electrodes 24, 25, made of aluminum or the like
26 and the oxide film 1 of the capacitor element 40.
The electrode 42 is formed on 0. In this embodiment, a semiconductor integrated circuit device having a bipolar transistor element and a capacitor element has been described. However, other active elements such as a MOS transistor element other than the bipolar transistor element or a passive element such as a resistor may be used.

[0017]

As described above, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, an opening for forming an insulating film for a capacitor element and a thick oxide film for a bipolar transistor element region are formed. By simultaneously forming the tapered portion of the film (= the same mask), the tapered portion can be formed without passing through the masking process again, so that the cost can be reduced by simplifying the process.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a method of manufacturing a semiconductor integrated circuit device according to the present invention.

FIG. 2 is an explanatory view showing a method for manufacturing a semiconductor integrated circuit device of the present invention.

FIG. 3 is an explanatory view showing a semiconductor integrated circuit device.

FIG. 4 is an explanatory view showing a method for manufacturing a conventional semiconductor integrated circuit device.

FIG. 5 is an explanatory view showing a method for manufacturing a conventional semiconductor integrated circuit device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Epitaxial layer 10 Oxide film 12 Tapered part 13, 14 Resist 20 Bipolar transistor element 21 P ⁺ type diffusion region 22, 23 N ⁺ type diffusion region 24, 25, 26 Electrode 40 Capacitor element 41 N ⁺ type diffusion region 42 electrode

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor integrated circuit device having a capacitor element, an opening for forming an insulating film for a capacitor element is formed in an oxide film on a diffusion region of a capacitor element area, and at the same time, another opening is formed. Forming a tapered portion in a thick oxide film in the element region, forming an insulating film for a capacitor element, forming an opening in an oxide film in another element region, Forming an electrode in another element region.