JPH0563070A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device wherein diodes are completely isolated from other elements and a rectification circuit consisting of the diodes is integrated on the same substrate. CONSTITUTION:A Schottky barrier diode 31 and a capacitor 25 are formed on the same n-type SOI substrate 14 together with a MOS transistor 32, a bipolar transistor 33, etc. A periphery of the Schottky barrier diode 31 is enclosed with a V-groove 18 which attains a substrate insulating film 12 and is completely isolated from other MOS transistor 21, the bipolar transistor 33, etc. An rectification circuit is formed of the Schottky barrier diode 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a highly integrated device in which a rectifying circuit and a smoothing circuit are integrated on the same substrate and a manufacturing method thereof. As semiconductor devices have become highly integrated in recent years, there is an increasing need for one-chip integration of diodes and capacitors, which are conventionally provided as external rectifier circuits and smoothing circuits, on the same substrate.

[0002]

2. Description of the Related Art For example, when a full-wave rectifier circuit as shown in FIG. 5A is integrated on the same substrate, it is necessary to make the potential of each diode constituting the full-wave rectifier circuit a floating potential. Therefore, other MOS (Meta
l-Oxide-Semiconductor) Complete electrical isolation from transistors and bipolar transistors is required.

However, the conventional element isolation method using pn junction isolation cannot realize such complete electrical isolation. That is, since the pn junction isolation lowers the isolation region to the lowest potential and blocks the current flowing from the high potential region to the high potential region, when AC voltage is applied, the region having the lowest potential is determined. Since this is not possible, an unintended current path will be created.

Therefore, even if the rectifier circuit is constructed by the diodes separated by the conventional pn junction, the full-wave rectifier circuit cannot be formed on the same substrate because it cannot exhibit a sufficient rectifying action. It was

[0005]

Therefore, in order to realize a one-chip integration in which a rectifying circuit and a smoothing circuit are integrated on the same substrate, the potential of the diode forming the rectifying circuit is changed in place of the conventional pn junction separation. It has been a subject to perform complete separation that can be made into a floating potential. Therefore, an object of the present invention is to provide a semiconductor device in which a diode is completely separated from other elements, and a rectifying circuit composed of these diodes is integrated on the same substrate, and a manufacturing method thereof.

[0006]

Means for Solving the Problems The above-mentioned problems are solved by a substrate having an insulator surface, a semiconductor layer formed on the insulator surface of the substrate, and a plurality of diodes formed in the semiconductor layer and forming a rectifying circuit. And a transistor formed in the semiconductor layer, and at least the plurality of diodes are electrically isolated from each other.

Further, in the above semiconductor device, the diode is electrically completely separated by a trench formed in the semiconductor layer so as to reach the insulator surface. ..
Further, in the above semiconductor device, the transistor is electrically completely separated by a trench formed in the semiconductor layer so as to reach the insulator surface.

In the above semiconductor device, at least a part of the trench has a V-groove shape. Moreover, in the above semiconductor device, at least a part of the trench has a U-groove shape. Further, in the above semiconductor device, the trench formed around the diode has a V-shaped groove, and the trench formed around the transistor has a U-shaped groove. Achieved by semiconductor devices.

Further, in the above semiconductor device, the trench is filled with polysilicon via an insulating film. Moreover, in the above semiconductor device, the trench is filled with an insulating material. Also, in the above semiconductor device, the diode is electrically completely isolated by a LOCOS isolation film formed in the semiconductor layer so as to reach the insulator surface.

In the above semiconductor device, at least some of the plurality of diodes are Schottky barrier diodes. Further, in the above semiconductor device, at least a part of the plurality of diodes is a pn junction diode.

Further, the above object is to form a semiconductor layer on the insulator surface of a substrate having an insulator surface, and to form a trench reaching the insulator surface in the semiconductor layer,
A step of electrically completely isolating the element region, a step of forming a diode in each of the plurality of element regions completely separated by the trench, a step of forming a transistor in the semiconductor layer, and a wiring of the plurality of diodes. And a step of forming a rectifying circuit to obtain a semiconductor device.

The method of manufacturing a semiconductor device may further include forming a trench reaching the insulator surface in the semiconductor layer, and forming the transistor in an element region completely separated by the trench. It is achieved by the method for manufacturing a semiconductor device.

[0013]

As described above, the present invention is a so-called SOI (Seic
OnductorOn Insulator) structure, a semiconductor layer on a substrate having an insulator surface reaches the insulator surface, or a trench or L
An OCOS isolation film is formed, and this trench or LOCOS is formed.
By forming a diode in the element region completely separated by the separation film, the potential of the diode can be set to a floating potential, so that a semiconductor device in which a rectifier circuit including these diodes is integrated on the same substrate is realized. be able to.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on illustrated embodiments. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. For example, on a support substrate 11 made of a silicon substrate, an n-thickness of 2 to 4 μm is provided via an inter-substrate insulating film 12 made of a silicon oxide film having a thickness of 1 μm, for example.
A so-called n-type SOI substrate 14 provided with a type (100) silicon thin film 13 is formed.

Further, a V groove 18 reaching the inter-substrate insulating film 12 is formed on the n-type SOI substrate 14. Then, in the V-groove 18, a silicon oxide film 19 having a thickness of 300 to 500 nm formed on the side wall thereof is provided,
A polysilicon layer 20 is filled. A silicon oxide film 21 is formed on the surface of the polysilicon layer 20. Further, a LOCOS oxide film 22 is formed on the n-type silicon thin film 13 by selective oxidation.

Thus, the n-type silicon thin film 13 surrounded by the V-groove 18 filled with the polysilicon layer 20 through the silicon oxide film 19 is completely electrically separated from the other n-type silicon thin films 13. ing. In addition, the silicon oxide film 2 having a predetermined thickness is formed on the n-type silicon thin film 13.
Capacitor electrode 2 made of polysilicon or the like via 3
4 are formed. That is, the capacitor 25 including the n-type silicon thin film 13 and the capacitor electrode 24 sandwiching the silicon oxide film 23 is formed.

Further, n completely separated by the V groove 18
The n ⁺ -type contact region 2 is formed on the surface of the -type silicon thin film 13.
6 is formed. Then, through the opening of the interlayer insulating film 27 grown on the entire surface, the n ⁺ type contact region 26,
A metal electrode 2 made of, for example, Al (aluminum) is formed on the n-type silicon thin film 13 and the capacitor electrode 24.
8, 29 and 30 are formed respectively.

Here, the metal electrode 28 is in ohmic contact with the n ⁺ type contact region 26, and the metal electrode 29 is in Schottky contact with the n type silicon thin film 13. Thus, the Schottky barrier diode 31 is formed on the n-type silicon thin film 13 completely separated by the V groove 18. The same n-type SOI is used together with the Schottky barrier diode 31 and the capacitor 25.
A MOS transistor 32, a bipolar transistor 33, etc. are formed on the substrate 14.

Metal wiring layers 35 and 36 made of, for example, Al and connected to the metal electrodes 28, 29 and 30 are formed through the openings of the interlayer insulating film 34 grown on the entire surface. The layer 36 connects the Schottky barrier diode 31 and the capacitor 25. As described above, in the semiconductor device according to the first embodiment, the Schottky barrier diode 31 and the capacitor 25 are formed on the same n-type SOI substrate 14 together with the MOS transistor 32, the bipolar transistor 33, etc., and the Schottky barrier is formed. The diode 31 is V
The groove 18 completely separates the MOS transistor 32, the bipolar transistor 33, and the like.

Further, although the MOS transistor 32 and the bipolar transistor 33 are separated from each other by the LOCOS oxide film 22, a pn junction separation may be used (not shown). The V-groove 18 is formed only around the Schottky barrier diode 31 here because the V-groove 18 is limited to the minimum area where complete isolation is most strictly required. Further, the reason why the V groove 18 is used as the trench is that the stress applied to the n-type silicon thin film 13 is smaller than that in the case of the U groove, so that the generation of crystal defects due to the stress can be suppressed.

On the other hand, since the V groove 18 has a larger opening as the depth thereof becomes deeper, it requires a larger area than the U groove, which is not suitable for miniaturization. Since only four diodes are required, the influence on miniaturization by using the V groove 18 can be ignored. Further, although the V groove 18 is formed in a place different from the place where the LOCOS oxide film 22 is formed,
It may be formed directly under the LOCOS oxide film 22.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. For example, by using a bonding method or the like, a silicon thin film is formed on the support substrate 11 made of a silicon substrate via the inter-substrate insulating film 12 made of a silicon oxide film having a thickness of 1 μm, for example, and having a high concentration used for a bipolar transistor. After forming the n-type buried layer, an n-type (100) silicon thin film 13 having a thickness of 2 to 4 μm is epitaxially grown to form an n-type SOI substrate 14.

If it is not necessary to form a high-concentration n-type buried layer, a thickness of 2 can be obtained by a bonding method or the like.
It is sufficient to form the n-type (100) silicon thin film 13 having a thickness of up to 4 μm, and it is not necessary to perform the subsequent epitaxial growth. On the n-type SOI substrate 14, a thickness of 30n
m silicon oxide film 15 and 200 nm thick silicon nitride film 16 are sequentially grown. Then, the silicon nitride film 16 and the silicon oxide film 15 are selectively removed by a normal photolithography process and an etching process to form an opening 17. The etching at this time may be either dry or wet etching (see FIG. 2A).

Next, using the silicon nitride film 16 and the silicon oxide film 15 as a mask, the n-type (100) silicon thin film 13 is etched using a solution such as KOH (potassium hydroxide) until it reaches the inter-substrate insulating film 12. .. At this time, for alkaline etching such as KOH, (10
Since the (0) plane is fast and the (111) plane is very slow, the V-groove 18 reaching the inter-substrate insulating film 12 can be formed on the n-type SOI substrate 14 (FIG. 2 (b)).

Next, the n-type (10
0) After forming a silicon oxide film 19 having a thickness of 300 to 500 nm on the silicon thin film 13, a polysilicon layer 20 is deposited on the entire surface to fill the V groove 18. Then, the polysilicon layer 20 is etched back by polishing or dry etching using the silicon nitride film 16 as a stopper (see FIG. 2C).

Then, the etched back surface of the polysilicon layer 20 is oxidized to form a silicon oxide film 21. Thus, the polysilicon layer 20 is formed through the silicon oxide film 19.
The n-type silicon thin film 13 surrounded by the V groove 18 filled with is completely separated from other n-type silicon thin films 13. Then, the silicon nitride film 16 and the silicon oxide film 15 are selectively removed to form an opening at a predetermined location, and then the LOCOS oxide film 22 is formed by selective oxidation using the silicon nitride film 16 as a mask. The formation of the LOCOS oxide film 22 and the formation of the V groove 18 may be performed in reverse order.

After removing the silicon nitride film 16 and the silicon oxide film 15, the surface of the n-type SOI substrate 14 is thermally oxidized to form a silicon oxide film 23 having a predetermined thickness. Then, a capacitor electrode 24 made of polysilicon or the like is formed on the silicon oxide film 23, and the silicon oxide film 23 is formed.
N-type silicon thin film 13 and capacitor electrode 2 sandwiched between
2 is formed (see FIG. 2D).

Next, as shown in FIG. 3A, the V groove 1
N ⁺ -type contact region 2 by selectively adding impurities to the surface of the n-type silicon thin film 13 completely separated by 8
After forming 6, the interlayer insulating film 27 is grown on the entire surface. Then, after forming an opening in the interlayer insulating film 27 by a normal photolithography process and an etching process, a metal layer made of, for example, Al is deposited on the entire surface.

Subsequently, this metal layer is patterned into a predetermined shape to form a metal electrode 28 which makes ohmic contact with the n ⁺ type contact region 26, a metal electrode 29 which forms a Schottky junction with the n type silicon thin film 13, and a capacitor electrode 24. A metal electrode 30 connected to is formed. Thus V
A Schottky barrier diode 31 is formed on the n-type silicon thin film 13 completely separated by the groove 18.

Incidentally, in parallel with this, another element, for example, M
In order to form an OS transistor, a bipolar transistor and the like, FIG. 3A also shows the MOS transistor 32 and the bipolar transistor 33 formed on the n-type SOI substrate 14. Next, the interlayer insulating film 34 is formed on the entire surface.
After that, the metal wiring layers 35, 36, etc. connected to the metal electrodes 28, 29, 30 etc. are formed through the openings provided in the interlayer insulating film 32. Then, for example, the metal wiring layer 36 connects the Schottky barrier diode 31 and the capacitor 25 (see FIG. 3B).

In this way, the same n-type SOI substrate 1
4 together with the MOS transistor 32, the bipolar transistor 33, etc., together with the Schottky barrier diode 31.
Then, a semiconductor device in which the capacitor 25 is formed and the Schottky barrier diode 31 is completely separated from other MOS transistors 32, bipolar transistors 33, etc. by the V groove 18 is manufactured.

Next, a concrete example in which a rectifying circuit and a smoothing circuit are formed by using the Schottky barrier diode 31, the capacitor 25 and the like according to the first embodiment will be described with reference to FIG. FIG. 4A is a circuit diagram showing a full-wave rectifier circuit, and FIG. 4B is a plan view showing a semiconductor device having the circuit formed therein.

This full-wave rectifier circuit is composed of a rectifier circuit 41 composed of four Schottky barrier diodes D1, D2, D3, D4, a smoothing circuit 42 composed of a capacitor Cp, and an output section 43 composed of a power transistor Tr. There is. Here, four Schottky barrier diodes D1, D2, D3, and D4 that form the rectifier circuit 41 are provided.
Are completely separated by the V-grooves provided on the n-type SOI substrate like the Schottky barrier diode 31 shown in FIG. 1, the individual potentials are floating potentials.

The capacitor Cp forming the smoothing circuit 42 corresponds to the capacitor 25 shown in FIG. 1 and is composed of an n-type silicon thin film with a silicon oxide film of a predetermined thickness sandwiched between polysilicon and the like. Capacitor electrode 44
It consists of and. Further, each of these elements is connected by a multi-layer wiring of a first wiring layer and a second wiring layer made of, for example, Al, as shown by the hatched portion in the figure.

That is, the Schottky barrier diodes D1 and D2 and the Schottky barrier diodes D3 and D4 of the rectifier circuit 41 are connected in series in the same direction. In addition, Schottky barrier diodes D1 and D3
Is grounded, and the cathodes of the Schottky barrier diodes D2 and D4 are connected to the capacitor electrode 44 of the capacitor Cp of the smoothing circuit 42.

Further, the n-type silicon thin film forming the capacitor Cp is grounded, and the other capacitor electrode 44.
Is connected to the collector C of the power transistor Tr of the output section 43. Therefore, V provided on the n-type SOI substrate
The rectifying circuit 4 is formed by the Schottky barrier diodes D1, D2, D3 and D4 which are completely separated by the grooves.
1 is configured, the connection point X between the diodes D1 and D2 and the connection point Y between the diodes D3 and D4 are, for example, 2
Even when a high AC voltage of 0 to 100 V is applied from the AC power supply 45, it can be rectified by this full-wave rectification circuit, and a DC voltage of, for example, 5 V can be output from the emitter E of the power transistor Tr. 10
In the case of an extremely high AC voltage of 0 V, the thickness of the element substrate should be 2
It should be about 0 μm. Then, this output supplies the power supply voltage to another element formed on the same substrate, for example, the CMOS inverter 46.

As described above, according to the first embodiment, the Schottky barrier diode 31 and the capacitor 25 are formed on the same n-type SOI substrate 14 together with the MOS transistor 32, the bipolar transistor 33, etc., and this shot is performed. The key barrier diode 31 can be completely separated from other MOS transistors 32, bipolar transistors 33, etc. by the V groove 18.

As a result, the electric potential of the Schottky barrier diode 31 can be made to be a floating electric potential. Therefore, by constructing a full-wave rectification circuit using the Schottky barrier diode 31 and the capacitor 25, it is possible to obtain a very high voltage from the AC power supply. Rectify high AC voltage to obtain the same n-type SOI
The power supply voltage of other elements formed on the substrate 14 can be supplied.

Although the full-wave rectifier circuit is taken as an example in FIG. 4, the half-wave rectifier circuit is similarly constructed by using the Schottky barrier diode 31, the capacitor 25 and the like according to the first embodiment. You can also do it. Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. The same components as those of the semiconductor device shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

The second embodiment uses a U-groove to completely isolate the diode in the first embodiment, whereas U
It is characterized by using grooves. That is, the U groove 56 reaching the inter-substrate insulating film 12 is formed on the n-type SOI substrate 14. The U groove 56 is filled with the polysilicon layer 20 through the silicon oxide film 19 formed on the side wall thereof. Furthermore, on this U groove 56,
A LOCOS oxide film 22 is formed by selective oxidation.

Thus, the n-type silicon thin film 13 surrounded by the U-groove 56 filled with the polysilicon layer 20 through the silicon oxide film 19 is completely electrically separated from the other n-type silicon thin films 13. ing. In addition, the capacitor 2 including the n-type silicon thin film 13 and the capacitor electrode 24 sandwiching the silicon oxide film 23 having a predetermined thickness therebetween.
5 is formed.

In addition, n completely separated by the U groove 56
An n ⁺ type contact region 26 is formed in the type silicon thin film 13, and a metal electrode 28 that makes ohmic contact with the n ⁺ type contact region 26 and a metal electrode 29 that forms a Schottky junction with the n type silicon thin film 13. Thus, the n-type silicon thin film 13 completely separated by the U groove 56
The Schottky barrier diode 31 is formed in the.

Further, together with the Schottky barrier diode 31 and the capacitor 25, a MOS transistor 32 and a bipolar transistor 33 are formed on the same n-type SOI substrate 14. Thus, in the semiconductor device according to the second embodiment, the U groove 56 is used instead of the V groove in the first embodiment, so that the Schottky barrier diode formed on the same n-type SOI substrate 14 is used. 31 is completely separated from other MOS transistors 32, bipolar transistors 33, and the like.

Note that the U groove 56 is formed only around the Schottky barrier diode 31.
This is because the complete separation is limited to the minimum area that is most strictly required. The U groove 56 is used as the trench because it is more suitable for miniaturization than the V groove. On the other hand,
Since the U-groove 56 exerts a larger stress on the n-type silicon thin film 13 than the V-groove, by separating the Schottky junction portion of the Schottky barrier diode 31 and the U-groove 56, the influence of this stress on the element. Has been relaxed.

Further, the U groove 56 is formed by the LOCOS oxide film 22.
However, it may be formed in a place where the LOCOS oxide film 22 is not formed. Next, a method of manufacturing the semiconductor device shown in FIG. 5 will be described with reference to FIG. The same components as those of the semiconductor device shown in FIGS. 2 and 3 are designated by the same reference numerals and the description thereof will be omitted.

For example, a silicon thin film is formed on the supporting substrate 11 made of a silicon substrate through the inter-substrate insulating film 12 by using a bonding method or the like to form a high-concentration n-type buried layer, and then a thickness of 2 is obtained. ~ 4 μm n-type silicon thin film 13
Are epitaxially grown to form an n-type SOI substrate 14. Then, a silicon oxide film 51 and a silicon nitride film 52 are sequentially grown on the n-type SOI substrate 14, an opening is selectively formed at a predetermined position, and then LOCOS is performed by selective oxidation using the silicon nitride film 52 as a mask. The oxide film 22 is formed (see FIG. 6A).

Next, after removing the silicon nitride film 52 and the silicon oxide film 51, a silicon oxide film 53 is newly grown on the n-type SOI substrate 14, and a silicon nitride film 54 is further grown on the entire surface. At this time, the initially grown silicon oxide film 51 and silicon nitride film 52 may be used as they are. Then, PSG (Phospho-
After growing the Silicate Glass) film 55, PS is formed by using a normal photolithography process and anisotropic etching.
G film 55, silicon nitride film 54 and LOCOS oxide film 2
2 is selectively removed to form an opening reaching the surface of the n-type SOI substrate 14.

Then, after removing the resist (not shown), the PSG film 55 or the like is used as a mask and RIE (Reactive I
on etching, the n-type silicon thin film 13 is etched until it reaches the inter-substrate insulating film 12. In this way, the U groove 56 reaching the inter-substrate insulating film 12 is formed on the n-type SOI substrate 14 (see FIG. 6B). Then, in FIG.
Almost the same as the steps shown in FIGS.
The U groove 56 is filled with the polysilicon layer 20 via the silicon oxide film 19, and the n-type silicon thin film 13 surrounded by the U groove 56 is completely separated from the other n-type silicon thin films 13.

Subsequently, a capacitor electrode 24 is formed on the n-type silicon thin film 13 with a silicon oxide film 23 having a predetermined thickness interposed therebetween.
To form the capacitor 25. Also, U groove 5
The n ⁺ type contact region 26 is formed on the surface of the n type silicon thin film 13 completely separated by 6, and the metal electrode 2 is in ohmic contact with the n ⁺ type contact region 26.
8. Form a metal electrode 29 that makes a Schottky junction with the n-type silicon thin film 13. Thus, the Schottky barrier diode 31 is formed on the n-type silicon thin film 13 completely separated by the U groove 56.

Further, in parallel with this, the n-type SOI substrate 1
A MOS transistor 32, a bipolar transistor 33, etc. are formed on 4 (see FIG. 6C). In this way, the Schottky barrier diode 31 and the capacitor 25 are formed together with the MOS transistor 32, the bipolar transistor 33, etc. on the same n-type SOI substrate 14, and this Schottky barrier diode 31 is used for another MOS transistor 32. And bipolar transistor 3
A semiconductor device which is completely separated from the third component and the like by the U groove 56 is manufactured.

As described above, according to the second embodiment, the U groove 56 is used in place of the V groove 18 in the first embodiment, and the MOS transistor 32 formed on the same n-type SOI substrate 14 and By completely separating the Schottky barrier diode 31 from the bipolar transistor 33 and the like, the same effect as that of the first embodiment can be obtained. Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 7 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. The same components as those of the semiconductor device shown in FIG. 1 or 5 are designated by the same reference numerals and the description thereof will be omitted. In the third embodiment, not only the diode but also other MOS transistors, bipolar transistors, etc. are completely isolated by the trench, the trench separating the diode is the V groove, and the trench separating the other element is the U groove. It is characterized in that

That is, the V-shaped groove 18 and the U-shaped groove 56 reaching the inter-substrate insulating film 12 are formed on the n-type SOI substrate 14. The V-groove 18 and the U-groove 56 are filled with the polysilicon layer 20 through the silicon oxide film 19 formed on the sidewalls thereof. Further, the LOCOS oxide film 22 is formed on the V groove 18 and the U groove 56 by selective oxidation.
Are formed.

In this way, the poly
Due to the V-groove 18 and the U-groove 56 filled with the silicon layer 20,
The n-type silicon thin film 13 surrounded by the
It is completely electrically separated from the recon thin film 13. Well
Also, an n-type silicon thin film surrounded by a V groove 18
In 13, n ⁺Ohmic contact to the mold contact area 26
In contact with the metal electrode 28 and the n-type silicon thin film 13
A metal electrode 29 is formed to make a Jottky junction.
Thus, n-type silicon completely separated by the V groove 18
The Schottky barrier diode 31 is formed on the thin film 13.
Has been.

Further, the n-type silicon thin film 13 and the capacitor electrode 24 with the silicon oxide film 23 of a predetermined thickness sandwiched therebetween.
And a capacitor 25 is formed. Furthermore, V
A bipolar transistor 33 is formed on the n-type silicon thin film 13 surrounded by the groove 18 and the U groove 56.
Further, the MOS transistor 32 is formed in the n-type silicon thin film 13 surrounded by the U groove 56. Although not shown, the other elements are also formed on the n-type silicon thin film 13 completely separated by the U groove 56.

As described above, according to the third embodiment, the V groove 18 and the U groove 56 in the first and second embodiments are used in combination, and the MOS transistor 32, the bipolar transistor 33, etc. are formed by the U groove 56. By completely separating the Schottky barrier diode 31 by the V groove 18, all the elements formed on the same n-type SOI substrate 14 are completely separated, so that the characteristics of each element are improved, The effects more than those of the first or second embodiment can be obtained.

Here, the Schottky barrier diode 3
The V groove 18 is used as the trench for separating 1 and the U groove 56 is used as the trench for separating the other elements.
This is because with respect to the former, importance was attached to suppressing the occurrence of crystal defects due to stress, and with regard to the latter, importance was attached to high integration by miniaturization of each element. Therefore, the V groove 18
By appropriately combining the U groove 56 with the U groove 56, it is possible to achieve high performance and high integration of the semiconductor device as a whole.
Of course, with an emphasis on high integration, the U groove 56 may be used for all trenches that separate the Schottky barrier diode 31 and other elements.

In the first to third embodiments, the V groove 18 or the U groove 56 is provided with the silicon oxide film 19 as shown in the enlarged views of FIGS. 8A and 8B. The polysilicon layer 20 was filled therethrough. However, FIG.
As shown in (c) and (d), the V groove 18 or the U groove 5
The entire 6 may be filled with an insulator 61 such as a silicon oxide film.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. The same components as those of the semiconductor device shown in FIG. 1 or 5 are designated by the same reference numerals and the description thereof will be omitted. The fourth embodiment is characterized in that a LOCOS oxide film is used, whereas the first to third embodiments use a V-groove or a U-groove to completely separate the diode. There is.

That is, the inter-substrate insulating film 12 is formed on the supporting substrate 11.
The n-type SOI substrate 14 provided with the n-type silicon thin film 13 is formed in the same manner as in the first to third embodiments. By the way, as the degree of integration of semiconductor devices is improved, the n-type silicon thin film 13 of the n-type SOI substrate 14 is
The thickness tends to be thin. Therefore, when the thickness of the n-type silicon thin film 13 is sufficiently thin, the LOCOS oxide film 62 reaching the inter-substrate insulating film 12 can be formed.

The n-type silicon thin film 13 surrounded by the LOCOS oxide film 62 thus formed on the n-type SOI substrate 14 is electrically completely separated from the other n-type silicon thin films 13. And the LOCOS oxide film 62
The n-type silicon thin film 13 completely separated by the metal electrode 28 is formed on the n-type silicon thin film 13 in the same manner as in the first to third embodiments.
Is in ohmic contact with the n ⁺ type contact region 26, and the Schottky barrier diode 31 in which the metal electrode 29 is in Schottky contact with the n type silicon thin film 13 is formed.

Although not shown, other MOS transistors and bipolar transistors are also completely isolated by the LOCOS oxide film 62. As described above, according to the fourth embodiment, the V-groove 1 in the third embodiment is used.
8 and the U groove 56, a LOCOS oxide film 62 is used to completely separate not only the Schottky barrier diode 31 formed on the same n-type SOI substrate 14 but also other MOS transistors and bipolar transistors. Thereby, the same effect as that of the third embodiment can be obtained.

It should be noted that in the first to fourth embodiments described above, the diode forming the rectifying circuit is the n ⁺ type contact on the surface of the n type silicon thin film 13 as shown in the enlarged view of FIG. Region 26, metal electrode 28 in ohmic contact with n ⁺ type contact region 26, and metal electrode 29 in Schottky contact with n type silicon thin film 13.
It was a Schottky barrier diode 31 having.

However, for example, the AC voltage to be rectified is
If the voltage is not so high, the pn junction diode 63 is used.
You may. That is, as shown in FIG.
On the surface of the type silicon thin film 13, n⁺Mold contact area 2
6, a p-type impurity region 64 is formed, and n-type silicon is formed.
A pn junction is formed with the thin film 13. And these n ⁺
To the p-type contact region 26 and the p-type impurity region 64, respectively.
And the metal electrodes 28 and 65 that are in ohmic contact are formed.
ing.

Thus, the V groove 18, the U groove 56 or the LOCO
A pn junction diode 63 is formed on the n-type silicon thin film 13 completely separated by the S oxide film 62. Further, although the n-type SOI substrate 14 provided with the n-type silicon thin film 13 is used in the first to fourth embodiments, of course, a p-type SOI substrate may be used. In this case, an n-type well may be provided in the p-type silicon thin film to form a Schottky barrier diode.

[0066]

As described above, according to the present invention, by using the SOI substrate and forming the diode forming the rectifying circuit in the semiconductor thin film completely isolated by the trench or the LOCOS isolation film reaching the insulating substrate, the rectification is performed. It is possible to realize a semiconductor device in which circuits are integrated on the same substrate.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process diagram (1) for explaining the method of manufacturing the semiconductor device of FIG.

3A and 3B are process diagrams (No. 2) for explaining the method of manufacturing the semiconductor device of FIG.

FIG. 4 is a diagram for explaining a full-wave rectifier circuit formed based on the first embodiment.

FIG. 5 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a process drawing for explaining the manufacturing method of the semiconductor device in FIG.

FIG. 7 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a diagram for explaining a modification of the V groove or the U groove used in the first to third embodiments.

FIG. 9 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 10 is a diagram for explaining modified examples of the diodes used in the first to fourth examples.

[Explanation of symbols]

11 ... Support substrate 12 ... Inter-substrate insulating film 13 ... N-type silicon thin film 14 ... N-type SOI substrate 15 ... Silicon oxide film 16 ... Silicon nitride film 17 ... Opening 18 ... V groove 19 ... Silicon oxide film 20 ... Polysilicon layer 21 ... Silicon oxide film 22 ... LOCOS oxide film 23 ... Silicon oxide film 24 ... Capacitor electrode 25 ... Capacitor 26 ... N ⁺ type contact region 27 ... Interlayer insulating film 28, 29, 30 ... Metal electrode 31 ... Schottky barrier diode 32 ... MOS transistor 33 ... Bipolar transistor 34 ... Interlayer insulating film 35, 36 ... Metal wiring layer 41 ... Rectifier circuit 42 ... Smoothing circuit 43 ... Output part 44 ... Capacitor electrode 45 ... AC power supply 46 ... CMOS inverter 51 ... Silicon oxide film 52 ... Silicon Nitride film 53 ... Silicon oxide film 54 ... Silicon nitride Film 55 ... PSG film 56 ... U groove 61 ... Insulator 62 ... LOCOS oxide film 63 ... Pn junction diode 64 ... P-type impurity region 65 ... Metal electrode D1, D2, D3, D4 ... Schottky barrier diode Cp ... Capacitor Tr ... Power transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ryo Hiramatsu 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Takao Miura 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Nichizuka Koki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Keinori Yamauchi 1015 Kamedota, Nakahara-ku, Kawasaki, Kanagawa Fujitsu Limited (72) Inventor, Ishikawa Ho Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Japan

Claims (13)

[Claims] 1. A substrate having an insulating surface, a semiconductor layer formed on the insulating surface of the substrate, a plurality of diodes formed in the semiconductor layer to form a rectifying circuit, and formed in the semiconductor layer. A semiconductor device, wherein at least the plurality of diodes are electrically isolated from each other. 2. The semiconductor device according to claim 1, wherein the diode is electrically completely separated by a trench formed in the semiconductor layer so as to reach the insulator surface. 3. The semiconductor device according to claim 2, wherein the transistor is electrically completely separated by a trench formed in the semiconductor layer so as to reach the insulator surface. 4. The semiconductor device according to claim 2, wherein at least a part of the trench has a V-groove shape. 5. The semiconductor device according to claim 2, wherein at least a part of the trench has a U-groove shape. 6. The semiconductor device according to claim 3, wherein the trench formed around the diode is V
Forming a groove, the trench formed around the transistor,
A semiconductor device having a U-groove shape. 7. The semiconductor device according to claim 2, wherein the trench is filled with polysilicon via an insulating film. 8. The semiconductor device according to claim 2, wherein the trench is filled with an insulating material. 9. The semiconductor device according to claim 1, wherein the diode is completely electrically isolated by a LOCOS isolation film formed in the semiconductor layer so as to reach the insulator surface. apparatus. 10. The semiconductor device according to claim 1, wherein at least a part of the plurality of diodes is a Schottky barrier diode. 11. The semiconductor device according to claim 1, wherein at least a part of the plurality of diodes is a pn junction diode. 12. A step of forming a semiconductor layer on the insulator surface of a substrate having an insulator surface, and a step of forming a trench reaching the insulator surface in the semiconductor layer and electrically completely isolating an element region. A step of forming a diode in each of a plurality of element regions completely separated by the trench, a step of forming a transistor in the semiconductor layer, and a step of forming a rectifier circuit by wiring the plurality of diodes. A method of manufacturing a semiconductor device, comprising: 13. The method of manufacturing a semiconductor device according to claim 12, further comprising: forming a trench in the semiconductor layer, the trench reaching the insulator surface, and forming the transistor in an element region completely separated by the trench. A method for manufacturing a semiconductor device, comprising: