JPH0239565A - Dielectric isolated substrate and manufacture thereof - Google Patents

Abstract

PURPOSE:To form an isolating structure having no parasitic thyristor and a substrate having the structure by forming a single-crystal region which passes the substrate in a structure in which the region is surrounded by an insulating film which passes the substrate. CONSTITUTION:Vertical MOS elements 1, 2 of complementary configuration and a signal processor 3 of complementary MOS configuration are formed on a substrate of a dielectric isolated structure made of Si. The elements and the processor are isolated by oxide films 4, 5 from each other. The sections of support layers isolated by the oxide films are composed only of n-type or p-type layers 7, 8 or 9, 10. That is, there is no p-n junction for isolating them, and no parasitic thyristor composed of the elements. A latchup phenomenon due to it does not occur. Simultaneously, since the elements 1, 2 are composed of the complementary type, its power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a substrate for a monolithic IC, and in particular to a structure and manufacturing method of a dielectrically isolated substrate suitable for forming a large current and high withstand voltage element. .

[Conventional technology]

Currently, there is a strong demand for monolithic ICs, so-called power ICs, in which large current and high voltage elements are integrated for use in automobiles, motor drives, and the like.

Element isolation methods for monolithic ICs are broadly classified into dielectric isolation methods and junction isolation methods, but the dielectric isolation method has many advantages for power ICs. However, in this method, the power device fabricated in the semiconductor single crystal region has a dielectric material and a semiconductor polycrystal region between it and the heat sink on which the IC chip is mounted, so it has a higher heat dissipation than normal vertical individual devices. There was a problem that the current capacity was poor and it was difficult to increase the current capacity.

FIG. 2 shows an example in which a device is fabricated on a conventional substrate that has been improved to accommodate a large current. As an element, an MO3 element 11 with a vertical structure is mounted.

A drain electrode 12 is formed on the back surface of the substrate.

The train electrode 12 is directly connected to the heat sink via a brazing material. Thus, the dissipation of heat generated in the device was improved.

[Problem to be solved by the invention]

Problems with the above conventional technology will be explained below.

In Figure 2, 11 is two vertical nM mounted on the board.
It is an OS element. These elements must be electrically isolated. P-type semiconductor region 14 between vertical MO8 elements
There is a pn junction 15 and an insulating film 4 between the vertical MOS elements.
Separated by

If the P-type semiconductor region 14 is always biased at a potential lower than the potential of each part in the vertical nMOS device, the p-type semiconductor region 14
The n-junction 15 is reverse biased, and the vertical MO3 elements are electrically isolated. However, this structure has the following problems. The source n-soil layer 16, the well 2 layer 17, the n-type layer of the single crystal region 18, the n+ layer 19, and the p layer 14 constitute a parasitic thyristor with an npnp structure between the electrode 20 and the electrode 12. If forward bias is applied to the pn junction 15 due to noise entering the electrodes 12, 13 or incorrect connection of the polarity of the power supply, this parasitic thyristor may operate, a so-called latch-up phenomenon may occur. . As a result, if an excessive current continues to flow through the parasitic thyristor, not only will the circuit malfunction, but the device may also be destroyed. As described above, the conventional method has had problems regarding circuit reliability.

Next, in order to reduce the power consumption of the circuit, it is desired to configure the large current elements in a complementary circuit configuration.
! 2 shows a case where a conventional vertical MO5 element is configured in a complementary manner. By applying a reverse bias to the pn junction 21°22.23, the n-type MO5FET 24 and the p-type MO3
FET 25 is electrically isolated. However, in this case as well, as mentioned above, a parasitic thyristor exists and there is a problem regarding the reliability of the circuit. That is, the conventional method also has difficulty in reducing the power consumption of the circuit.

The latch-up phenomenon between the vertical MO8 elements has been described above. On the other hand, in a power IC, a circuit consisting of a small power element that processes an input signal to the large power element is usually integrated together with a large power element in the output stage. By conventional method,
Even when an input signal processing circuit is fabricated in a single-crystal Si region that penetrates the substrate, the reliability of the circuit is similarly impaired due to the parasitic thyristor caused by the pn junction formed in the support layer.

From the above, a power IC having a complementary MO8 element as an output stage and a complementary MO5 signal processing circuit as an input stage must have a structure as shown in FIG. 4. That is, only one vertical MO3 element 29 is formed in a single crystal region penetrating the substrate, and the remaining one output MO8 element 3
0, and a signal processing circuit 31. do not penetrate the substrate, but are formed in the single crystal regions 26 and 33 with the insulating film 4 interposed between them and the polycrystalline semiconductor region 32. This structure has the problem that it is difficult to increase the current capacity of the output MO3 element 30, as described above. Furthermore, the following problems arise. That is, the single crystal region penetrating the substrate carries a large current MO3.
It is limited to only the portion 19 at the bottom of the element. The other substrate support must then consist of polycrystalline semiconductor 32. By the way, the dielectric isolation substrate has a large curvature due to the fact that the element formation portion is made of a single crystal semiconductor and the substrate support is made of a polycrystalline semiconductor. For this reason, it is difficult to increase the diameter of the substrate and to microfabricate the devices to be manufactured. In order to reduce the curvature of the substrate, it is desirable to increase the proportion of the single crystal region of the support as much as possible. From this point of view as well, the conventional method that cannot increase this has a problem.

To summarize the above, in the conventional system, a parasitic thyristor is generated due to a pn junction formed for isolation between elements, and there is a problem in circuit reliability. Further, for this reason, it is difficult to reduce power consumption by making the large current capacity elements have a complementary configuration, and to reduce substrate curvature by increasing the proportion of the single crystal region of the support layer.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide an element isolation structure without a parasitic thyristor and a method of manufacturing a substrate having the same.

[Means to solve the problem]

The above object is achieved by forming a structure in which a single crystal region penetrating the substrate is surrounded by an insulating film penetrating the substrate.

Further, the manufacturing process for realizing such a structure is as follows. That is, a separation groove is formed in the east crystal substrate, an insulating film is formed, and a predetermined portion of the insulating film is removed as before, and then a first support layer is grown. Next, after removing the first support layer, an insulating film is formed on the exposed side wall portion of this layer. After removing a predetermined portion of the insulating film, a second support layer is grown. After that, a predetermined portion of the substrate is polished away.

[Effect]

The single crystal portions penetrating the substrate are surrounded by an insulating film penetrating the substrate and are insulated from each other. thus,
A pn junction for isolation is no longer necessary, and a parasitic thyristor that uses this as a component can also be eliminated. Therefore, the latch-up phenomenon does not occur.

Also, to describe the role of each manufacturing process, in the growth process of the first support layer, a single crystal region that penetrates the first substrate is formed from the part where the insulating film is removed, and a multi-crystal region that penetrates the first substrate is formed from the other parts. A crystal layer grows. By removing the first support layer and forming an insulating film on the sidewall thereof, an insulating film that penetrates the substrate is formed.

Next, in the growth step of the second support layer, a single crystal region penetrating the first substrate and a separated second single crystal region are formed from the part where the insulating film is removed, and a second single crystal region separated from the other part is formed. A support polycrystalline region is grown. Thereafter, by performing polishing, the substrate surface is planarized and a structure is created in which each single crystal region is separated by an insulating film.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Si
Vertical M of complementary configuration to the substrate of the structure according to the invention using
This is an example in which OS elements 1 and 2 and a signal processing circuit 3 having a complementary MO5 configuration are formed. The vertical MO3 element and the signal processing circuit are separated from each other by oxide films 4 and 5.

Each part of the support layer separated by an oxide film has an n-type layer 7.8,
Alternatively, it is composed of only P-type layers 9 and 10.

That is, there is no pn junction for separating these from each other, and therefore there is no parasitic thyristor using this as a component. The latch amplifier phenomenon caused by this does not occur. At the same time, power consumption was reduced because the vertical elements 1°2 could be of complementary configuration. Furthermore, since most of the support layer can be made of single crystal Si, the curvature of the substrate can be reduced compared to the conventional method.

Next, the manufacturing process of the substrate shown in this example will be sequentially explained with reference to FIG.

First, the P-type (100) substrate 34 is photo-etched to remove a predetermined portion to form a groove 35 (b).

Next, an n-type wheel crystal S i I 36 is grown in a vapor phase to fill the groove, and is polished down to the surface indicated by the - dotted chain line to flatten the substrate (c) and (d). Next, separation grooves 37 are formed by photoetching (e). Silicon nitride film 3
8 is formed on the surface on which the isolation groove is formed, and after removing the portions outside of the predetermined parts by photo-etching (f), an insulating oxide film 4 is formed by thermal oxidation (g). After removing a predetermined portion of the insulating oxide film by photoetching (h), a low-resistance P-type support Si layer is grown in a vapor phase (i). A single crystal Si layer 1o grows from the portion where the insulating oxide film has been removed, and a polycrystalline Si layer 9 grows from the other portion. next,
Removal of the support layer at a predetermined portion using a photoetching method (
j). Next, thermal oxidation is performed to form an oxide film 5 on the side wall portion of the portion where the support has been removed (k). After removing the silicon nitride film by etching with hot phosphoric acid (1), a low resistance n-type Si layer is grown in vapor phase (m). A single crystal Si layer 8 grows from the part not covered with the oxide film,
A polycrystalline Si layer 7 grows from other parts. After that, the substrate was polished down to the surface indicated by the dashed line, and
The substrate is completed by creating a structure in which an oxide film layer consisting of , penetrates through the substrate.

This example shows the case of forming P-type and n-type single crystal parts, but if steps a) to e) are omitted and a P-type low resistance Si layer is grown in m), the P-type It is easy to see that a single crystal layer of only

Furthermore, an n-type single crystal Si substrate can also be used. Furthermore, it can also be used in combination with a buried layer region, such as the one marked 31 in FIG.

〔Effect of the invention〕

According to the present invention, a parasitic thyristor formed by a pn junction separating single crystal Si regions penetrating the substrate can be removed. Therefore, latch-up caused by this can no longer occur. Moreover, this enables a complementary configuration of vertical elements with improved circuit reliability, and as a result, in the case of a capacitive load, power consumption other than during switching can be reduced to almost 0.

Furthermore, since most of the support layer can be made of single crystal, the amount of curvature of the substrate can be reduced to several tens of percent.

[Brief Description of the Drawings] Fig. 1 is a longitudinal cross-sectional view of an IC using a substrate according to an embodiment of the present invention, and Figs. 2 to 4 are longitudinal cross-sections of an example of an IC using a conventional substrate. FIG. 5 is a vertical cross-sectional view showing an example of the manufacturing process flow of the substrate of the present invention. 4... Oxide film, 5... Oxide film, 7... N-type high concentration polycrystalline layer, 8- N-type high concentration single crystal layer, 9... P-type high concentration polycrystalline layer, 10...・P-type high concentration single crystal layer. 1st mouth 3rd mouth 4ffJ 2nd mouth

Claims (1)

[Claims] 1. Extending from one main surface to the other main surface of the substrate,
at least two semiconductor single crystal regions whose main surfaces are exposed on both main surfaces, a semiconductor polycrystalline region that supports the semiconductor single crystal regions, and a dielectric film that insulates and separates the semiconductor single crystal regions from each other; A dielectric isolation substrate characterized in that a body film extends from one main surface to the other main surface of the substrate. 2. A step of forming an isolation trench on a single crystal substrate, a step of forming a first insulating film and removing a predetermined portion of the insulating film, a step of growing a semiconductor layer on the surface of the substrate on which the isolation trench has been formed, and forming the first insulating film. a step of forming a semiconductor single crystal region and a polycrystalline region, a step of removing a predetermined portion of the semiconductor layer until the insulating film is exposed, a step of forming a second insulating film on the sidewall of the semiconductor region exposed after removal, A step of removing the insulating film in a predetermined portion, a step of growing a semiconductor layer on the side of the substrate on which the semiconductor layer was grown, a step of growing a second single crystal semiconductor region and a polycrystalline region, and a step of growing the grown semiconductor layer, A method for manufacturing a dielectric isolation substrate, comprising the steps of polishing and removing the second insulating film until it is exposed, and polishing and removing the single crystal substrate until the single crystal region is separated.