JP2689969B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a window comparator which outputs a signal only when an input voltage is within a certain range. The present invention relates to a window comparator that determines whether or not they are substantially equal within the range of

[0002]

2. Description of the Related Art As a conventional window comparator,
FIG. 3 shows a circuit configuration thereof. With reference to FIG. 3, this window comparator circuit uses resistors 9 to 13 and diodes 14 and 15 in a comparator including transistors 1 to 6 and current sources 7 and 8 to detect positive and negative threshold voltages and windows. It is used by setting the width.

More specifically, the comparator has transistors 3 and 4 having emitters connected in common and connected to a constant current source 7 to form a differential pair, and a collector of the differential pair to form a current mirror circuit. Transistors 1 and 2 to
Transistor 5 connected to the collector of transistor 3
And a transistor 6 whose collector is connected to the output terminal 18 and which is connected to the emitter of the transistor 5. Then, the resistance values of the resistors 10 and 11 (the connection point of the resistors 10 and 11 is connected to the base of the transistor 4) connected between the reference voltage terminal 16 and the ground are R ₁₀ , R ₁₁ ,
When the connection resistance value of the resistor 9 and 12 between the bases of the input terminal 17 and the differential pair transistors 3 and 4 and R _9, R _12, the voltage of the reference voltage terminal 16 and the + V _P, the input terminal 17
The transistor 6 is turned on and the current flows to the output terminal 18 only when the input voltage V _IN applied to is within the range of the following equation (1).

-(R ₁₁ / R ₁₂ ) × V _P <V _IN <R ₁₀ × V _P / (R ₁₀ + R ₁₁ ) ... (1)

[0005]

However, in the conventional window comparator circuit described above, when the voltage V _P of the reference voltage terminal 16 is changed to change the threshold voltage as shown in the above equation (1), the threshold voltage is changed accordingly. Changing window width and input 1 connected to comparator
Since 7 (input signal path) and reference voltage 16 (reference voltage path) have asymmetrical circuit configurations, there is a problem that they are not suitable for comparison between two different fluctuating input signals.

Therefore, the present invention has been made in view of the above problems, and provides a window comparator in which the width of the window does not change due to the change of the threshold voltage and two different fluctuating inputs can be compared. The purpose is to

[0007]

In order to achieve the above object, the present invention provides a first and a second transistor each having an input signal voltage to be compared applied to the base, and a base having the first transistor. A third transistor connected to the emitter, the emitter connected to the emitter of the second transistor, the base connected to the emitter of the second transistor, and the emitter connected to the emitter of the first transistor. A fourth transistor, first to fourth resistors respectively connected to the collectors of the first to fourth transistors, and a common-connected emitter of the first transistor and the fourth transistor. And a second current source connected to the commonly connected emitters of the second transistor and the third transistor. A current source, a fifth transistor whose base is connected to the collector of the third transistor, a sixth transistor whose base is connected to the collector of the fourth transistor, and the fifth and sixth transistors And an output terminal connected to the commonly connected emitters, and determining whether the width of the voltage difference between the input signals to be compared is approximately included in the width of the voltage difference between the base and the emitter of the transistor. A window comparator is provided.

According to the present invention, the base-emitter voltage of the transistor having the second input signal voltage as the base input is calculated from the first input signal voltage (VA) and the second input signal voltage (VB). The voltage (VB-V) less VBE2)
BE2) and a first differential transistor pair for differentially amplifying the first and second differential transistor pairs, the first input signal voltage (VA) being the base input to the first input signal voltage (VA). A voltage (VA-VBE1) obtained by subtracting the base-emitter voltage (VBE1) of the one transistor that constitutes
A second differential transistor pair that differentially amplifies the second input signal voltage (VB), and a third differential transistor that differentially inputs the outputs of the first and second differential transistor pairs. A pair of transistors, and the first input signal voltage (VA) and the second input signal voltage (VB) from the output terminals connected to the commonly connected emitters of the third differential transistor pair. Is configured to output a signal indicating whether or not in the range of −VBE2 <VA−VB <VBE1, the window width is constant and fluctuates regardless of the change of the threshold voltage. A circuit is obtained which is capable of comparing two input signals.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. In FIG. 1, reference numerals 23 and 24 denote first and second transistors to which an input signal to be compared is applied from the input terminals 21 and 22 to the base, and 25 denotes the first transistor 2.
A third transistor whose base is connected to the emitter of 3; 26 is a fourth transistor whose base is connected to the emitter of the second transistor 24; 27 is connected to the emitters of the first and fourth transistors 23 and 26 A first current source 28, a second and a third transistor 2
A second current source connected to the emitters of 4, 25, 29,
32, 30, 31 are first, second, third, and fourth resistors connected to the collectors of the first, second, third, and fourth transistors 23, 24, 25, 26, and 33 is the third. A fifth transistor whose base is connected to the collector of the transistor 25, 34 is a sixth transistor whose base is connected to the collector of the fourth transistor 26, and 35 is a fifth transistor.
It is an output terminal connected to the emitters of the sixth transistors 33 and 34.

That is, referring to FIG. 1, the first transistor 23 and the fourth transistor 26 form a first differential pair in which their emitters are commonly connected and are connected to a first current source 27. Then, the second transistor 24 and the third transistor 25 form a second differential pair in which their emitters are commonly connected and are connected to the second current source 28. Paired output (fourth transistor 26 and third
The collector potential of the transistor 25) is differentially input to the bases of the third differential pair whose emitters are commonly connected and are connected to the output terminal 35.

Next, the operation of this embodiment will be described. When the voltages input to the input terminals 21 and 22 are V _A and V _B , respectively, the voltages applied to the bases of the third and fourth transistors 25 and 26 are calculated from the input signal voltages V _A and V _B , respectively. Base-emitter voltage V _{BE of} the first and second transistors 23 and 24 (provided that the base-emitter voltages of the first and second transistors are both equal)
Only drop the voltage, i.e. V _A -V _BE, the V _B -V _BE.

Here, when V _A -V _BE > V _B , no current flows through the second transistor 24 and all the current flowing through the second current source 28 flows through the third transistor 25. It comes to flow.

Therefore, no current flows through the fourth transistor 26, and a current (collector current) flows through the third transistor 25, so that the third transistor 25 is connected to the collector of the third transistor 25. The voltage drop across the resistor 30 increases, the base potential of the fifth transistor 33 decreases (the base potential of the sixth transistor increases), and the current flowing through the fifth transistor 33 changes to the sixth
Current flowing through the transistor 34 of the above.

The current flowing through the output terminal 35 is the sum of the currents flowing through the fifth and sixth transistors 33 and 34.

Similarly, if V _B −V _BE > V _A , the sixth
The current flowing through the transistor 34 is smaller than the current flowing through the fifth transistor 33.

Meanwhile, the conditions of the input signal voltage at the input terminal 21 and 22, | V _A -V _B | when a <V _BE, together no current flows through the third and fourth transistors 25 and 26 Therefore, the voltage drop in the third and fourth resistors 30 and 31 becomes small, which increases the base potentials of the fifth and sixth transistors 33 and 34, and the output terminal 35.
Current flowing in is larger than the output current flowing when the input signal voltage is a condition V _A -V _BE> V _B or V _B -V _BE> V _A.

Therefore, when the input signal voltage difference │V _A -V _B │ is included within the voltage V _BE between the base and emitter of the transistor, the current flowing through the output terminal 35 is increased, which is a window comparator. Take action.

The base-emitter voltage of each of the first transistor 23 and the second transistor 24 is V
_{Even when BE1} and V _BE2 are set, the output terminal 35 is -V _BE2
<When the V _A -V _B <V _BE1, current flows in both the fifth and sixth transistors 33 and 34, the output current is large. Then, when the input voltages V _A and V _B are in this range, for example, by inserting a resistance element between the output terminal 35 and the ground, a voltage signal (for example, a logic signal of “L” level) is taken out from the output terminal 35. be able to.

FIG. 2 is a diagram showing the configuration of the window comparator according to the second embodiment of the present invention. With reference to FIG. 2, the fifth embodiment includes a fifth transistor 6 and a sixth transistor 4.
The bases of 9, 50 are the first and second transistors 39, 4,
It is different from the first embodiment in that it is connected to a collector of 0.

In the present embodiment, the input terminals 37, 3
The input signal voltage of 8 is V _A , V _B , the base-emitter voltage of the first and second transistors 39, 40 is V _BE (however,
It is assumed that the base-emitter voltages of the first and second transistors are both equal), and V _A (base potential of the first transistor 39) is greater than V _B -V _BE (base potential of the fourth transistor 42). also a large _{(V a> V B -V bE} ), and V _B (second base potential of the transistor 40) is V _a -V _bE larger than (base potential of the third transistor 41) (V _B > V _a -V _BE) when, ie | V _a
When −V _B | <V _BE , the first and second transistors 3
The current flowing through the transistors 9 and 40 increases (the current flowing through the third or fourth transistors 41 and 42 does not decrease or does not flow), and the voltage drop across the resistors 45 and 48 increases accordingly.
And the base potential of the sixth transistor falls, and no current flows through the output terminal 51, while │V _A -V _B │> V
_At the time of _BE , the current flowing through the third or fourth transistor 41, 42 increases, and the first or second transistor 49, 5
The current flowing to 0 decreases, and the resistance 45 or 48
Of the fifth or sixth transistor is increased and the current flowing to the output terminal 51 is | V _A −
It increases more than when V _B | <V _BE . As described above, in this embodiment, a signal having a complementary relationship with the first embodiment is output. Then, by connecting a resistance element between the output terminal 51 and the ground, a voltage signal (logic signal of "H" level) can be taken out from the output terminal 51.

[0022]

As described above, the window comparator of the present invention uses two different input signals and a voltage having a difference between the voltage of the input signal and the voltage between the base and the emitter of the transistor, so that the window width is always maintained. A constant and also a comparison of two fluctuating input signals can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 3 is a diagram showing an example of a conventional window comparator.

[Explanation of symbols]

23-26, 33, 34, 39-42, 49, 50 Transistor 27, 28, 43, 44 Constant current source 28-32, 45-48 Resistor 21, 22, 37, 38 Input terminal 35, 51 Output terminal 36, 52 Power supply terminal (VCC)

Claims (5)

(57) [Claims] 1. A first and a second transistor having respective bases to which input signal voltages to be compared are applied, a base connected to an emitter of the first transistor, and an emitter connected to an emitter of the second transistor. A third transistor connected to the second transistor; a fourth transistor having a base connected to the emitter of the second transistor and an emitter connected to the emitter of the first transistor; First to fourth resistors respectively connected to collectors, a first current source connected to commonly connected emitters of the first transistor and the fourth transistor, the second transistor and the A second current source connected to the commonly connected emitter of the third transistor and a base of the third transistor A fifth transistor connected to the first transistor, a sixth transistor whose base is connected to the collector of the fourth transistor, and an output terminal connected to the commonly connected emitters of the fifth and sixth transistors. And a window comparator for determining whether or not the width of the voltage difference between the input signals to be compared is substantially included in the width of the voltage difference between the base and the emitter of the transistor. 2. A first and a second transistor having respective bases to which input signal voltages to be compared are applied, the base being connected to the emitter of the first transistor, the emitter being connected to the emitter of the second transistor. A third transistor connected to the second transistor; a fourth transistor having a base connected to the emitter of the second transistor and an emitter connected to the emitter of the first transistor; First to fourth resistors respectively connected to collectors, a first current source connected to commonly connected emitters of the first transistor and the fourth transistor, the second transistor and the A second current source connected to the commonly connected emitter of the third transistor and a base of the first transistor. A fifth transistor connected to the second transistor, a sixth transistor whose base is connected to the collector of the second transistor, and an output terminal connected to the commonly connected emitters of the fifth and sixth transistors. And a window comparator for determining whether or not the width of the voltage difference between the input signals to be compared is substantially included in the width of the voltage difference between the base and the emitter of the transistor. 3. A base-emitter voltage (VBE2) of a transistor having the second input signal voltage as a base input from a first input signal voltage (VA) and a second input signal voltage (VB). A first differential transistor pair that differentially amplifies the subtracted voltage (VB-VBE2); and the first input signal voltage (VA) from which the first input signal voltage is used as a base input. A differential amplification of a voltage (VA-VBE1) obtained by subtracting the base-emitter voltage (VBE1) of one transistor constituting one differential transistor pair and the second input signal voltage (VB); A second differential transistor pair, and a third differential transistor pair having outputs of the first and second differential transistor pairs as a differential input, wherein the third differential transistor pair is commonly connected. From the output terminal connected to the emitter The first input signal voltage (VA) and the second input signal voltage (VB) but, -VBE
A window comparator which outputs a signal indicating whether or not it is within a range of 2 <VA-VB <VBE1. 4. A collector potential of a transistor having the voltage (VB-VBE2) as a base input among the transistors forming the first differential transistor pair, as a base input of the third differential transistor pair, Of the transistors forming the second differential transistor pair, the collector potential of the transistor having the voltage (VA-VBE2) as a base input is used as an input, and the first input signal voltage (VA) is used.
4. The window comparator according to claim 3, wherein a current flowing through the output terminal increases when the second input signal voltage (VB) is within the range. 5. A collector potential of a transistor having the input voltage (VA) as a base input among the transistors forming the first differential transistor pair, as a base input of the third differential transistor pair, and Of the transistors forming the second differential transistor pair, the collector potential of the transistor having the voltage (VB) as a base input is used as an input, and the first input signal voltage (VA) and the second input signal voltage ( 4. The window comparator according to claim 3, wherein a current flowing through the output terminal increases when VB) is outside the range.