JP2900688B2 - Limiter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a limiter circuit,
In particular, it relates to a limiter circuit for arbitrarily setting a limiter voltage.

[0002]

2. Description of the Related Art As a conventional limiter circuit, a circuit as shown in FIG. 3 is widely used. The limiter circuit shown in FIG. 3 includes transistors Q20 and Q2 forming a differential pair.
1 are input terminals VIN, respectively, and the transistors Q2
Two diodes D7 and D8 are connected between the collectors of 0 and Q21 so that the polarities are opposite to each other. The load resistors RL are connected to the collectors of the transistors Q20 and Q21, respectively.

In the limiter circuit shown in FIG.
The potentials at the points are Vx and Vy, respectively. Input terminal VIN
When there is no input signal ein, since the same current I flows through the transistors Q20 and Q21 forming the differential pair, Vx = Vy, and the potentials at both ends of the diodes D7 and D8 are equal. It does not conduct and is in an equilibrium state.

Assume that the input signal ein is applied to the input terminal VIN, and the current flowing through the transistor Q20 increases to I + i, and the current flowing through the transistor Q21 decreases to I-i. Here, i is an AC current component changed by the input signal ein. Therefore, the potentials Vx and Vy at the X and Y points
Is represented by the following Expressions 1 and 2.

[0005]

Vx = Vcc-RL (I + i)

[0006]

## EQU2 ## Vy = Vcc-RL (Ii)

Further, the junction voltage of the diode D8 is set to VD
Assuming that (D8), the condition that the diode D8 starts conducting and starts the limiting action is expressed by the following equation (3).

[0008]

## EQU3 ## Vy-Vx = VD (D8)

Since the limiter voltage eo obtained from the output terminal Vout is Vy-Vx, it is expressed by the following equation (4).

[0010]

Eo = Vy-Vx = 2iRL = VD (D8)

Next, it is assumed that the polarity of the input signal ein is inverted, the current flowing through the transistor Q20 decreases to I-i, and the current flowing through the transistor Q21 increases to I + i.
Assuming that the junction voltage of the diode D7 is VD (D7), the limiter voltage eo obtained from the output terminal Vout is expressed by the following equation 5 as in the case described above.

[0012]

Eo = −2iRL = −VD (D7)

Therefore, VD (D7) = VD (D8) = VD
If the diodes D7 and D8 are selected so as to obtain the limiter voltage eo at the double output obtained from the output terminal Vout,
pp is represented by Equation 6 below.

[0014]

[Equation 6] eop-p = | 2iRL | = VD

As described above, in the limiter circuit shown in FIG. 3, the limiter voltage eo is equal to the junction voltage VD of the diode.
Therefore, the limiter voltage cannot be set arbitrarily.

Generally, since the junction voltage VD of the diode is about 0.8 V, the limiter voltage eo is 0.8 V
About. Here, the junction voltage VD of the diode is represented by the following equation (7).

[0017]

VD = kT / q.ln (IK / IS)

Here, q is the elementary charge of electrons, k is Boltzmann's constant, T is the junction temperature, IK is the cathode current of the diode, and IS is the saturation current of the diode. Therefore, the junction voltage VD of the diode has a characteristic proportional to a change in temperature, and is usually about 1.5 mV / ° C. Therefore, there is a disadvantage that the limiter voltage eo in the limiter circuit shown in FIG. Several methods have been proposed to improve the above-mentioned disadvantage that the limiter voltage cannot be arbitrarily set and the disadvantage that the limiter voltage fluctuates due to the temperature characteristics (for example, Japanese Patent Publication No. Hei.
No. 16803).

Conventionally, a limiter circuit as shown in, for example, FIG. 4 described in Japanese Patent Publication No. Hei 3-16803 has been proposed. The conventional limiter circuit shown in FIG. 4 has transistors Q17 and Q18 each having a base connected to an input terminal VIN and an emitter commonly connected to form a differential pair.
A constant current source S6 connected to the emitters of the transistors Q17 and Q18 and allowing a constant current of 2I to flow, and resistors RL1 and RL2
And a switching transistor Q16, Q19 and a resistor RB.

In the limiter circuit shown in FIG. 4, the base-emitter voltages of the transistors Q16 and Q19 are VBE (Q16) and VBE (Q19), respectively.
= VBE (Q19) so that the transistor Q1
If 6, 19 is selected, the limiter voltage eo obtained from the output terminal Vout and the limiter voltage eop-p in the double output obtained from the output terminal Vout are expressed by the following equations (8) and (9).

[0021]

Eo = 2RL1 (VBE-RBI) / (2RL1 + 2RL2 + RB)

[0022]

[Mathematical formula-see original document] eop-p = 4RL1 (VBE-RBI) / (2RL1 + 2RL2 + RB)

As described above, the limiter voltage is determined by the resistances RL1 and RL.
2, RB and the current value 2I of the constant current source S6 can be set arbitrarily. In addition, the deviation of the relative ratio of the same type of resistor formed on the IC substrate is usually about several percent, and if the constant current source S6 is configured by a constant voltage source such as a band gap regulator and a resistor, the resistance ratio or The temperature characteristic of the term of the product of the resistance value and the current can be almost neglected, and the effect of the temperature characteristic remains in the term of the limiter voltage eo, ie, 2RL1 · VBE of the term related to the base-emitter voltage VBE. / (2RL1 + 2RL2 + RB).

As described above, the base-emitter voltage VBE has a temperature characteristic, and a comparison between the conventional limiter circuit shown in FIG. 4 and the conventional limiter circuit shown in FIG. 3 shows that the limiter circuit shown in FIG. , The temperature fluctuation of the limiter voltage is small. For example, RL1 = RL2 = 2KΩ, RB
Assuming that = 500Ω, the temperature fluctuation value of the limiter voltage in the limiter circuit shown in FIG.

[0025]

## EQU10 ## 2RL1 / (2RL1 + 2RL2 + RB) = 0.47

Therefore, the influence of the temperature characteristic of the base-emitter voltage VBE can be reduced to about one half compared with the limiter circuit shown in FIG. However, the influence of the temperature characteristics of the base-emitter voltage VBE still remains.
Further, the limiter voltage eo is represented by the above equation 8, and 2RL1 / (2RL1 + 2RL2 + RB) <1, so that it is represented by the following equation 11.

[0027]

Eo = 2RL1 (VBE-RBI) / (2RL1 + 2RL2 + RB) <VBE

Therefore, the limiter voltage eo is equal to the junction voltage VB
The value cannot exceed E.

Another conventional example is disclosed in Japanese Patent Publication No. Hei 3-1680.
For example, a limiter circuit described in Japanese Patent Publication No. 3 as shown in FIG. 5 has been proposed. In the conventional limiter circuit shown in FIG. 5, a base is connected to an input terminal VIN, and an emitter is connected in common to form a transistor Q which forms a differential pair.
12, Q13, a constant current source S5 connected to the emitters of the transistors Q12, Q13 and flowing a constant current of 2I, a differential amplifier composed of transistors Q9, Q10, and a resistor RL. Transistor Q
11, Q14 and a resistor RB.

In the limiter circuit shown in FIG.
The potentials at points S, T, and U are Vp, Vs, Vt, and V, respectively.
u. When there is no input signal ein at the input terminal VIN,
Since the same current I flows through the transistors Q12 and Q13 forming the differential pair, Vp = Vt and Vs = Vu, so that a balanced state is established. Next, the input signal e is input to the input terminal VIN.
Assume that in is applied, the current flowing through the transistors Q12 and Q9 increases to I + i, and the current flowing through the transistors Q13 and Q10 decreases to I-i. Here, i is an AC current component changed by the input signal ein. The base-emitter voltages of the transistors Q9 and Q14 are
(Q9) and VBE (Q14), the potentials Vp, Vt, and Vu at points P, T, and U are represented by the following equations (12) to (14).
Is represented by

[0031]

Vp = Vcc- (I + i) RL

[0032]

Vt = Vcc- (Ii) RL

[0033]

Vu = Vcc- (Ii) (RL + RB)

Also, the transistor Q14 starts conducting,
The condition under which the limiting action starts is expressed by the following equation (15).

[0035]

Vu−Vp + VBE (Q9) = VBE (Q14)

If the transistors Q9 and Q14 are selected so that VBE (Q9) = VBE (Q14), the AC current component i changed by the input signal ein is expressed by the following equation (16).

[0037]

## EQU16 ## i = I · RB / (2RL + RB)

The limiter voltage eo obtained from the output terminal Vout is expressed by the following equation (17).

[0039]

Eo = Vt−Vp = 2iRL = 2I · RB · RL / (2RL + RB)

Assuming that the polarity of the input signal ein is inverted and the current flowing in the transistors Q12 and Q9 decreases to I-i and the current flowing in the transistors Q13 and Q10 increases to I + i, the transistor Q10 , Q
11, the base-emitter voltages are VBE (Q10),
Assuming that VBE (Q11), the condition that the transistor Q11 starts conducting and the limiting action starts is as follows:
It is represented by 8.

[0041]

Vs−Vt + VBE (Q10) = VBE (Q11)

Then, VBE (Q10) = VBE (Q11)
If the transistors Q10 and Q11 are selected so that the following equation is obtained, the limiter voltage eo obtained from the output terminal Vout is expressed by the following equation (19).

[0043]

Eo = −2iRL = −2I · RB · RL / (2RL + RB)

Accordingly, the limiter voltage eop-p at the double output obtained from the output terminal Vout is expressed by the following equation (20).

[0045]

[Equation 20] eop-p = | 2iRL | × 2 = 4I · RB · RL / (2RL + RB)

Since the limiter voltage eo is determined by RB, RL and I, an arbitrary limiter voltage can be set by a combination of these values. Also, the deviation of the relative ratio between the same type of resistors formed on the IC substrate is usually about several percent, and the constant current source S5 for supplying the current 2I may be composed of a constant voltage source such as a band gap regulator and a resistor. If this is the case, a limiter voltage can be obtained in which temperature characteristics can be almost ignored.

As described above, in the conventional limiter circuit shown in FIG. 5, the input voltage and the limiter voltage at which the limiting action starts can be arbitrarily selected by the combination of the resistors RB and RL, and the temperature of the junction voltage A limiter voltage independent of characteristics can be obtained.

[0048]

However, in the above-described conventional limiter circuit, the transistors Q12, Q9
The current flowing to the transistor Q13 increases to I + i.
The current flowing through Q10 decreases to Ii,
When the transistor 14 is turned on, the collector-emitter voltage VCE (Q9) of the transistor Q9 is expressed by the following equation (21).

[0049]

VCE (Q9) = Vs-Vu + VBE (Q14) =-2RLi-2RBI / (2RL + RB) + VBE (Q14)

Here, since 2RLi is the limiter voltage eo, the above equation (21) is represented by the following equation (22).

[0051]

Eo = VBE (Q14) -VCE (Q9) -2RBI / (2RL + RB)

Since the limiter voltage eo is determined by the values of the resistors RL and RB and the current I as expressed by the above equation (19), the value of the resistor RL must be changed to the value of the resistor RB to increase the limiter voltage eo. It is necessary to choose a bigger than. Resistance RL
Is larger than the value of the resistor RB, the term of 2RBI / (2RL + RB) in Equation 22 can be ignored, and the limiter voltage eo is expressed by Equation 23 below.

[0053]

EoｅVBE (Q14) -VCE (Q9)

Similarly, when the current flowing through the transistors Q12 and Q9 decreases to I-i, the current flowing through the transistors Q13 and Q10 increases to I + i, and the transistor Q11 is turned on, the limiter voltage eo is similarly expressed by the following equation (24). Is represented by

[0055]

[Equation 24] eo ≒ VBE (Q11) −VCE (Q10)

Generally, the base-emitter voltage of a transistor is about 0.8 V, and the minimum collector-emitter voltage at which the transistor is not saturated is about 0.3 V. Therefore, the limiter voltage eo is about 0.5 V at the maximum. Become.
Therefore, the conventional limiter circuit as shown in FIG. 5 has a disadvantage that a large limiter voltage cannot be obtained.

The present invention has been made in view of the above-mentioned problems, and provides a limiter circuit which can set a limiter voltage arbitrarily and can obtain a large limiter voltage exceeding 2 V with double output. The purpose is to provide.

[0058]

SUMMARY OF THE INVENTION A limiter circuit according to the present invention comprises a differential pair composed of first and second transistors whose input signals are supplied to respective bases and whose emitters are connected in common. A first constant current source connected to the common emitter of the differential pair, a third transistor having an emitter connected to the collector of the second transistor, and an emitter connected to the collector of the first transistor No.
And a first transistor having one end connected to the collector of the third transistor and the other end connected to the first power supply .
A second resistor having one end connected to the collector of the fourth transistor and the other end connected to the first power supply; and a collector of the first transistor and a collector of the third transistor. One or more first diodes connected between the first and second transistors, and one or more second diodes connected between the collector of the second transistor and the collector of the fourth transistor ; before Symbol third and fourth is connected to the base of the transistor and the third and
Bias set the base potential of the fourth transistor to the third and the potential to cut off the fourth transistor and the third and a constant voltage potential lower than the bias potential of the collector of the fourth transistor during bias
And a circuit .

[0059]

In the limiter circuit according to the present invention, the first and second transistors are respectively connected between the respective collectors of the first and second transistors constituting the differential pair and the first and second resistors which are load resistors. And the base potential of the third and fourth transistors, which are switching transistors, is a potential that cuts off the third and fourth transistors in a steady state, and is the potential of the third and fourth transistors. By setting the potential lower than the bias potential of the collector by a fixed voltage, the limiter voltage can be set arbitrarily and a limiter voltage independent of the temperature characteristics of the base-emitter voltage VBE of the transistor can be obtained. The degree of freedom in setting the limiter voltage is increased, and a larger limiter voltage can be obtained. Further, the limiter voltage in the limiter circuit according to the present invention is determined by the resistance and the current value in the bias circuit of the third and fourth transistors, that is, the value of the voltage drop in the resistance in the bias circuit of the switching transistor. The bias and the limiter voltage at the output terminal can be set separately, and a limiter circuit that can be easily designed when integrated with other functional circuits can be provided.

[0060]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a limiter circuit according to a first embodiment of the present invention. As shown in FIG. 1, the limiter circuit according to the first embodiment includes transistors Q1 and Q2 each having a base connected to an input terminal VIN and an emitter connected in common to form a differential pair;
1, a constant current source S1 connected to the emitters of Q2 and flowing a constant current of 2I, a diode D2 having a cathode connected to the collector of the transistor Q1, a diode D1 having a cathode connected to the anode of the diode D2, and a transistor Q2. A diode D4 having a cathode connected to the collector of the diode D3, a diode D3 having a cathode connected to the anode of the diode D4, and a load resistor having one end connected to the anodes of the diodes D1 and D3 and the other end connected to the power supply Vcc. And a switching transistor Q3 whose collector is connected to the anode of the diode D1 and whose emitter is connected to the collector of the transistor Q2, and whose collector is connected to the anode of the diode D3 and whose emitter is Is the collector of transistor Q1 And a switching transistor Q4 connected to the
, A transistor Q5 having a base connected to the resistor RA and a collector connected to the power supply Vcc, and one end connected to the emitter of the transistor Q5 and the other end common to the bases of the transistors Q3 and Q4. And a constant current source S2 connected to the bases of the transistors Q3 and Q4 and flowing a constant current of I0.

Next, the operation of the limiter circuit according to the first embodiment configured as described above will be described. The potentials at points A, B, C, D, E, and F in the limiter circuit shown in FIG. 1 are denoted by Va, Vb, Vc, Vd, Ve, and Vf, respectively.
When there is no input signal ein at the input terminal VIN, the currents flowing through the transistors Q1 and Q2 forming the differential pair are equal,
Since the currents flowing through the two load resistors RL are also equal, Va =
Vc and Vb = Vd. Since Va = Vc, no current flows through the resistor RA, and Va = Vc = Ve.
The junction voltage of the diodes D1, D2, D3, and D4 is set to V
D1, VD2, VD3, and VD4, and transistors Q3, Q4,
The base-emitter voltages of Q5 are VBE (Q3) and VBE
Assuming that BE (Q4) and VBE (Q5), the potentials Vb and Vf
Is represented by the following Expressions 25 and 26, respectively.

[0063]

Vb = Va−VD1−VD2

[0064]

Vf = Ve-VBE (Q5) -RI0

Here, VBE (Q5) = VD1 = VD2 = VD
If the diodes D1 and D2 are selected so that the following equation is satisfied, the difference between the potential Vf and the potential Vb is represented by the following equation (27).

[0066]

Vf-Vb = Vd-RI0 <Vd

Therefore, transistor Q4 does not conduct.
Similarly, the transistor Q3 does not conduct and is in an equilibrium state.

Next, it is assumed that the input signal ein is applied to the input terminal VIN, the current flowing through the transistor Q1 increases to I + i, and the current flowing through the transistor Q21 decreases to I-i. Here, i is an alternating current component changed by the input signal ein. The potentials Va, Vb, Vc, Vf are
These are expressed by the following equations 28 to 31, respectively.

[0069]

## EQU28 ## Va = Vcc-RL (I + i)

[0070]

Vb = Vcc-RL (I + i) -VD1-VD2

[0071]

Vc = Vcc-RL (Ii)

[0072]

Vf = Ve-VBE (Q5) -RI0

The condition under which the transistor Q4 starts conducting and the limiting action starts is expressed by the following equation (32).

[0074]

Vf-Vb = VBE (Q4)

VBE (Q5) = VBE (Q4) = VD1 = VD2
= VD, the transistors Q5, Q4 and the diodes D1, D2 are selected, i = RI0 / RL,
The limiter voltage eo obtained from the output terminal Vout is represented by the following equation (33).

[0076]

Eo = Vc-Va = 2iRL = 2RI0

Next, it is assumed that the polarity of the input signal ein is inverted, the current flowing through the transistor Q1 decreases to I-i, and the current flowing through the transistor Q2 increases to I + i. The condition under which the transistor Q3 starts conducting and the limiting operation starts is expressed by the following equation (34).

[0078]

Vf-Vb = VBE (Q3)

VBE (Q5) = VBE (Q3) = VD3 = VD4
If the transistors Q5 and Q3 and the diodes D3 and D4 are selected so that = VD, the limiter voltage eo obtained from the output terminal Vout is expressed by the following equation (35).

[0080]

Eo = −2iRL = −2IRBRL / (2RL + RB)

Accordingly, the limiter voltage eop-p at the double output obtained from the output terminal Vout is represented by the following equation (36).

[0082]

[Equation 36] eop-p = | 2iRL | × 2 = 4RI0

From these, it can be seen that the limiter voltage eo can be set arbitrarily by a combination of the resistance R and the current value I0 supplied by the constant current source S2, and does not depend on the temperature characteristics of the junction voltage. Since the deviation of the relative ratio of the same type of resistor formed on the IC substrate is usually about several percent, if the constant current source S2 for supplying the current I0 is constituted by a constant voltage source such as a band gap regulator and a resistor, for example. As a result, a limiter voltage eo whose temperature characteristics can be almost ignored is obtained. Further, the limiter voltage eo can have a large value within a range where the transistors Q1 and Q2 constituting the differential pair are not saturated, and a large amplitude limiter voltage can be obtained.

As an example, in the limiter circuit according to the first embodiment shown in FIG. 1, the power supply voltage Vcc is 9 V, the load resistance RL is 1.5 KΩ, the resistance RA is 30 KΩ, and the resistance R is 1
Assuming that 0 KΩ, the current value I supplied from the constant current source S1 is 2 mA, the current value I0 supplied from the constant current source S2 is 50 μA, and the bias voltage of the input signal ein applied to the input terminal VIN is 3 V, the limiter voltage eo is , And is represented by the following Expression 37.

[0085]

Eo = 2RI0 = 1 (V)

The limiter voltage eop-p at the double output
Becomes 2V.

FIG. 2 is a circuit diagram showing a limiter circuit according to a second embodiment of the present invention. In the limiter circuit according to the second embodiment, the components different from the limiter circuit shown in FIG.
7 and 8 constitute a base voltage bias circuit for Q8. In the limiter circuit shown in FIG. 1, a resistor RA, a transistor Q5, a resistor R, and a constant current source S2 constitute a base voltage bias circuit. However, the limiter circuit according to the second embodiment includes resistors RL3, R A base voltage bias circuit is constituted by the constant current source S4 for supplying the constant current I1.

The operation of the limiter circuit according to the second embodiment is the same as the operation of the limiter circuit according to the first embodiment. The current value I1 supplied by the constant current source S4 is expressed by the following equation (3).
Set as shown at 8.

[0089]

[Formula 38] I1 = (RL1 + RL2) I / RL3

Thus, the limiter voltage eo obtained from the output terminal Vout and the limiter voltage eop-
p is represented by the following Expression 39 and Expression 40.

[0091]

Eo = 2RI1 RL1 / (RL1 + RL2)

[0092]

[Mathematical formula-see original document] eop-p = 4RI1 RL1 / (RL1 + RL2)

[0093]

As described above, according to the limiter circuit of the present invention, a diode is provided between the collector of the transistor forming the differential pair and the load resistance, and the base of the switching transistor is provided with a constant bias. The limiter voltage can be set arbitrarily, a limiter voltage independent of the temperature characteristics of the base-emitter voltage VBE can be obtained, and the degree of freedom of the limiter voltage setting is increased. In addition, a larger limiter voltage can be obtained. Further, the limiter voltage is determined by the resistance and the current value in the bias circuit of the switching transistor, that is, the value of the voltage drop at the resistor R in the bias circuit of the switching transistor. Therefore, the bias at the output terminal and the limiter voltage are separately determined. It is possible to provide a limiter circuit which can be set and is easily designed when integrated with other functional circuits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a limiter circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a limiter circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a first example of a conventional limiter circuit.

FIG. 4 is a circuit diagram showing a second example of a conventional limiter circuit.

FIG. 5 is a circuit diagram showing a third example of a conventional limiter circuit.

[Explanation of symbols]

 Q1, Q2, Q3, Q4; transistor RL; load resistance RA, R; resistance D1, D2, D3, D4; diode S1, S2;

Claims (1)

(57) [Claims] An input signal is supplied to respective bases, and a differential pair composed of first and second transistors whose emitters are connected in common, and a first pair connected to a common emitter of the differential pair. of a constant current source, a third transistor whose emitter is connected to the collector of the second transistor, a fourth transistor whose emitter is connected to the collector of said first transistor, said third transistor A first resistor having one end connected to the collector and the other end connected to the first power source; and a second resistor having one end connected to the collector of the fourth transistor and the other end connected to the first power source . A resistor connected between a collector of the first transistor and a collector of the third transistor;
One or more first diodes, one or more second diodes connected between the collector of the second transistor and the collector of the fourth transistor ,
Before being connected to the base of the front Symbol third and fourth transistors
The base potential of the third and fourth transistors is biased.
And a bias circuit for setting the potential at a time to cut off the third and fourth transistors and at a fixed voltage lower than the bias potential of the collectors of the third and fourth transistors. circuit.