JP3074888B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a differential type current switching circuit composed of bipolar transistors.

[0002]

2. Description of the Related Art As a conventional semiconductor integrated circuit, a differential current switching circuit as shown in FIG. 4 is known. FIG.
, Terminal 1 is an input terminal, terminals 2 and 3 are first and second output terminals, respectively, and terminals 4 and 5 are first and second control signal input terminals, respectively. As shown in FIG. 4, the first NPN transistor 6 has a collector connected to the terminal 2, a base connected to the terminal 4, and an emitter connected to the terminal 1 in common with the emitter of the second NPN transistor 7.
It is connected to the. The second NPN transistor 7 has a collector connected to the terminal 3 and a base connected to the terminal 5.

Next, the operation of the conventional semiconductor integrated circuit shown in FIG. 4 configured as described above will be described. Terminal 4,
5 are applied with first and second control signals having opposite polarities, respectively, and these control signals are applied to the bases of the first and second NPN transistors 6 and 7 which are differentially connected. Is entered. A current I1 is supplied to the terminal 1 in a direction from the terminal 1 to the outside. Currents I2 and I3 output from terminals 2 and 3 to the outside are
Assuming that the potentials of the second control signals are ΔV and −ΔV, respectively, and that the grounded emitter current amplification factors (hereinafter, referred to as hFE) of the first and second NPN transistors 6 and 7 are equal, It is represented by 2.

[0004]

I1 = (hFE / (hFE + 1)) × (I1 / 2) × {1 + tanh (ΔV / VT)}

[0005]

I3 = (hFE / (hFE + 1)) × (I1 / 2) × {1-tanh (ΔV / VT)}

VT in Equations 1 and 2 is VT = KT
/ Q. Where K is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, and VT at room temperature (27 ° C.).
Is about 26 mV.

When ΔV, which is the potential of the first control signal, is set to be 5 to 10 times VT, tanh (10) ≒
Since tanh (5) ≒ 1, the value of the current I3 is almost 0 according to Expression 2, and the value of the current I2 is approximately (hFE / (h
FE + 1)) × I1. Further, when the polarity of the potential of the first and second control signals is inverted, that is, when the polarity of the control signal applied to the terminals 4 and 5 is inverted, the value of the current I2 becomes substantially 0, and The value is approximately (hFE / (hFE +
1)) × I1 That is, when the amplitude of the control signal applied to the terminals 4 and 5 is 2ΔV (about 260 mV to 520 mV) and the potential of the terminal 4 is higher than the potential of the terminal 5,
The current input to terminal 1 is multiplied by hFE / (hFE + 1) and output from terminal 2. When the potential of terminal 5 is higher than the potential of terminal 4, the current input to terminal 1 is hFE / (hFE +
1) Multiplied and output from terminal 3.

Therefore, the conventional semiconductor integrated circuit shown in FIG. 4 determines whether the current flows to the terminal 2 or the terminal 3 by the first and second control signals applied to the terminals 4 and 5. It operates as a switching current switching circuit.

[0009]

However, in the above-described conventional semiconductor integrated circuit, not all of the input current is output from the respective output terminals, but the amount of the base current of the transistor for switching the output. It is output with only loss. Therefore, the output current has a value obtained by multiplying the input current by a coefficient of hFE / (hFE + 1) depending on the hFE of the transistor. Therefore, the above-described conventional semiconductor integrated circuit has a problem that if the hFE fluctuates due to variations in semiconductor manufacturing, the output current also fluctuates, and hFE itself has a dependency on temperature. Therefore, there is a problem that the output current fluctuates in accordance with a change in temperature, so that it cannot be used particularly in applications requiring high accuracy and high stability.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and in a current switching circuit using a differential circuit in a semiconductor integrated circuit, it is possible to compensate for a loss due to a base current of a transistor constituting the current switching circuit. It is an object of the present invention to provide a semiconductor integrated circuit that can be used.

[0011]

A semiconductor integrated circuit according to the present invention has first and second transistors, the emitters of which are commonly connected to form a differential switching circuit, and the first and second transistors.
First and second current output terminals connected to the collectors of the first and second transistors, respectively, and first and second current input terminals respectively inputting the first and second control signals to the bases of the first and second transistors, respectively. A third and fourth transistor having a control signal input terminal, a power supply terminal, a base connected to the first and second control terminals, a collector connected to the power supply terminal, and an emitter commonly connected, A fifth transistor having a base and a collector connected to the emitters of the first and second transistors, and a collector connected to the third transistor;
And a sixth transistor connected to the emitter of the fourth transistor and having a base connected to the base of the fifth transistor, and a current supplied from the outside commonly connected to the emitters of the fifth and sixth transistors. And a current input terminal for inputting. Further, another semiconductor integrated circuit according to the present invention includes first and second transistors having emitters commonly connected to form a differential switching circuit, and respective transistors connected to collectors of the first and second transistors. First and second current output terminals and first and second current output terminals are respectively connected to the bases of the first and second transistors.
First and second control signal input terminals for inputting the control signals of the first and second transistors, a fifth transistor having a base and a collector connected to the emitters of the first and second transistors, and a base having the fifth transistor. A sixth transistor connected to the base of the fifth transistor, a current input terminal commonly connected to the emitters of the fifth and sixth transistors for inputting a current supplied from the outside, a power supply terminal, and a collector connected to the power supply terminal. A seventh transistor connected and having an emitter connected to the collector of the sixth transistor; and a base connected to the base of the seventh transistor and having the base equalize the collector-emitter voltage of the fifth and sixth transistors. And a bias input terminal for applying a bias voltage to be applied.

[0012]

In the semiconductor integrated circuit according to the present invention, in the differential switching circuit in the semiconductor integrated circuit, the differential switching circuit for compensating for the loss of the output current due to the base current of the plurality of transistors constituting the differential switching circuit. A compensation circuit is provided by a current mirror circuit which receives a control signal from a common connection point of the emitters of the switching circuit and uses a current input source as a ground point. The compensating circuit reduces the influence of the transistor hFE on the output current of the semiconductor integrated circuit by supplying a current having a value corresponding to the potential of the emitter of the differential switching circuit to the differential switching circuit. be able to.

[0013]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. Descriptions of parts having the same reference numerals and functions as those of the conventional semiconductor integrated circuit shown in FIG. 4 are omitted. Terminal 12 is a power supply terminal. In the third and fourth NPN transistors 8 and 9, the bases are connected to the terminals 4 and 5, respectively, the emitters are commonly connected to the sixth NPN transistor 11, and the collectors are commonly connected to the terminal 12. The base and the collector of the fifth NPN transistor 10 are connected to the common connection point of the emitters of the first and second NPN transistors 6 and 7 together with the base of the sixth NPN transistor 11. The emitters of the fifth and sixth NPN transistors 10 and 11 are commonly connected to the terminal 1.

All the transistors used in the semiconductor integrated circuit according to the first embodiment are configured as integrated circuits on one semiconductor substrate and have the same shape, and therefore have almost no characteristics. They are complete and can be considered the same. Therefore, hFE as a parameter can be regarded as the same for all the transistors.

Next, the operation of the semiconductor integrated circuit according to the first embodiment configured as described above will be described. The current I1 supplied from the outside to the terminal 1 is the fifth and sixth N
It is equally distributed to the emitters of the PN transistors 10 and 11. As a result, the current I67 flowing to the common emitter connection point of the first and second NPN transistors 6 and 7 and the current I89 flowing to the common emitter connection point of the third and fourth NPN transistors 8 and 9 are as follows. Equation 3,
It is represented by Equation 4.

[0017]

## EQU3 ## I67 = ((hFE + 2) / (hFE + 1)). Times. (I1 / 2)

[0018]

## EQU4 ## I89 = (hFE / (hFE + 1)). Times. (I1 / 2)

When the potentials of the first and second control signals applied to the terminals 4 and 5 are ΔV and −ΔV, respectively, the currents I 2 and I 3 output to the outside from the terminals 2 and 3
Is given by I67, which represents I1 in Expressions 1 and 2 in Expression 3.
By replacing the following equations (5) and (6), respectively.
Is represented by

[0020]

## EQU5 ## I2 = ｛((hFE + 1) ² -1) / ((hFE + 1) ² )) × (I1 / 4) ×
｛1 + tanh (ΔV × VT)｝

[0021]

## EQU6 ## I3 = ｛((hFE + 1) ² -1) / ((hFE + 1) ² ) ｝ × (I1 / 4) ×
{1-tanh (ΔV × VT)}

Comparing Equation 1 with Equation 5, the coefficient hFE / (hFE + 1) in Equation 1 is calculated by the coefficient に お い て ((hFE + 1) ² -1) /
It can be seen that ((hFE + 1) ² ) has been replaced by｝ × (1/2). Usually, since hFE is about 100, hFE / (hFE + 1)
≒ 0.9910, ｛((hFE + 1) ² -1) / ((hFE + 1) ² )｝ ≒ 0.999
It becomes 9 . Therefore, the output current of the conventional semiconductor integrated circuit suffers a loss of about 0.9% of the output current due to the base current of the transistor, but the output current of the semiconductor integrated circuit according to the first embodiment is 0.0 of its output current
It only loses about 1 %.

As a result, in the semiconductor integrated circuit according to the first embodiment, since the loss of the output current caused by the finite hFE is reduced, the influence on the output current by the fluctuation of the hFE due to the temperature change is also reduced. Become smaller.

Third and fourth NPN transistors 8, 9
Is designed to equalize the collector-emitter voltages of the fifth NPN transistor 10 and the sixth NPN transistor 11 and eliminate the influence of the Early voltage of the fifth and sixth NPN transistors 10 and 11, thereby reducing the fifth and fifth NPN transistors 10 and 11. Sixth NPN
This is a compensating transistor constituting a current mirror circuit for making the hFE of the transistors 10 and 11 substantially equal.

In equation (5), the output current is １ ／ of the input current, because the coefficient is multiplied by 1/2 compared to equation (1). Since it is mainly required that the ratio between the input current and the output current is always constant, the attenuation of the output current does not matter.

Next, a second embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention. Descriptions of parts having the same reference numerals and functions as those of the semiconductor integrated circuit according to the first embodiment of the present invention shown in FIG. 1 are omitted. Terminal 13 is a bias input terminal, and the third NP
It is connected to the base of N transistor 8. Also, the bias applied to the terminal 13 is such that the fifth NPN transistor 10 and the sixth NPN transistor 11 are in a state where either the first NPN transistor 6 or the second NPN transistor 7 is conducting. This is a bias for equalizing the collector-emitter voltage, and has a value equal to the high-level potential of the control signal applied to the terminals 4 and 5.

With the above configuration, in the second embodiment, the number of the transistors for early voltage compensation in the first embodiment can be reduced by one.

Next, a third embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention. Descriptions of parts having the same reference numerals and functions as those of the semiconductor integrated circuits according to the first and second embodiments of the present invention shown in FIGS. 1 and 2 are omitted. The terminal 14 is a third output terminal, and the terminal 15 is a third control signal input terminal. Terminal 1
4 is connected to the collector of the seventh NPN transistor 16, and the terminal 15 is connected to the base of the seventh NPN transistor 16. The emitter of the seventh NPN transistor 16 is commonly connected to the emitters of the first and second NPN transistors 6, 7. Terminals 4, 5, and 15 are control signal input terminals. One of these terminals is set to a high potential, and the remaining two terminals are set to the same low potential. Current can be output from one of the terminals. The potential difference between the high potential and the low potential applied to the terminals 4, 5, and 15 may be about 260 mV to 520 mV, as in the first and second embodiments.

As described above, the semiconductor integrated circuit according to the third embodiment can easily increase the number of outputs that can be switched by adding a transistor to the differential transistor used in the current switching circuit. be able to.

[0030]

As described above, according to the semiconductor integrated circuit of the present invention, in the current switching circuit using the differential circuit in the semiconductor integrated circuit, the loss due to the base current of the transistor constituting the differential circuit is compensated. In addition, since a compensation circuit based on a current mirror circuit is provided, the effect of the transistor hFE on the output current can be extremely reduced. As a result, the semiconductor integrated circuit according to the present invention can obtain an output current having high stability even with respect to hFE variation and temperature fluctuation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1, 2, 3, 4, 5, 12; terminal 6, 7, 8, 9, 10, 11; NPN transistor

Claims (2)

(57) [Claims] 1. A first and a second transistor having emitters connected in common to form a differential switching circuit, and a first and a second transistor respectively connected to collectors of the first and second transistors.
And a second current output terminal, a first and second control signal input terminal for inputting first and second control signals to the bases of the first and second transistors, respectively, a power supply terminal, and a base. Are connected to the first and second control terminals, respectively, are collectors connected to the power supply terminal, and emitters are commonly connected to the third and fourth transistors. The base and the collector are the first and second transistors, respectively. A fifth transistor connected to the emitter of the transistor, a sixth transistor having a collector connected to the emitters of the third and fourth transistors, and a base connected to the base of the fifth transistor; And a current input terminal commonly connected to the emitter of the sixth transistor and receiving a current supplied from the outside. 2. A first and second transistor having emitters connected in common to form a differential switching circuit, and a first and second transistor respectively connected to collectors of the first and second transistors.
And a second current output terminal; first and second control signal input terminals for inputting first and second control signals to the bases of the first and second transistors, respectively; A fifth transistor connected to the emitters of the first and second transistors, and a base connected to the fifth transistor.
A sixth transistor connected to the base of the third transistor, a current input terminal commonly connected to the emitters of the fifth and sixth transistors for inputting a current supplied from the outside, a power terminal, and a collector connected to the power source. A seventh transistor connected to a terminal and having an emitter connected to the collector of the sixth transistor; and a collector-emitter voltage of the fifth and sixth transistors connected to the base of the seventh transistor and connected to the base. And a bias input terminal for applying a bias voltage for making the same.