JPH05243864A - Differential amplifying circuit - Google Patents

Abstract

PURPOSE:To adjust the fluctuation of an offset voltage with the smaller number of elements, and also, to reduce the power consumption by cascading a correction voltage generating part and a bias voltage generating part, and sharing a part of each circuit. CONSTITUTION:The control voltage DELTAV0 of a gain control means 32 is set to negative, and the base potential of a transistor(TR) Q13 is set lower than that of a TR Q14. The base potential of a TR Q31 becomes a higher value than that of a TR Q32. Thus, the correction voltage V11 of a connecting middle point P13 of an output stage 33 becomes higher by an offset voltage DELTAV portion against the correction voltage V12 of a connecting middle point P14 of an output stage 34. Consequently, the corrector current of TRs Q3, Q4 becomes large, a generated voltage DELTAV has a reverse voltage -DELTAV, and the offset value DELTAV generated in the TRs TRs Q3, Q4 is canceled. Also, as for the output stages 33, 34 constituted of TRs Q18, Q20, Q22 and Q24, an idling current for flowing to the TRs Q15, Q31 and Q16 and Q32 is given, and a Gilbert amplifier 30 can reduce the power consumption.

Description

Detailed Description of the Invention

The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 4 and 5) Problems to be Solved by the Invention (FIGS. 6 and 7) Means for Solving Problems (FIGS. 1 to 3) Working Example (FIGS. 1 to 1) Figure 3) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit, and is particularly suitable for application to a Gilbert type differential amplifier circuit.

[0003]

2. Description of the Related Art Conventionally, a differential amplifier circuit is generally used in the input stage and output stage of an integrated circuit. As one of such differential amplifier circuits, a Gilbert amplifier 1 as shown in FIG. There is.

The Gilbert amplifier 1 is composed of a differential input stage 2 and a differential output stage 3, and the differential input stage 2 is composed of a pair of NPN type transistors Q1 and Q2.

Here, the differential input stage 2 includes a transistor Q1.
And the current sources 4 and 5 are connected to the emitter of Q2,
Connection midpoints P1 and P2 between each emitter and the current sources 4 and 5
_Are connected via an input resistor R _IN .

Further, the differential input stage 2 outputs the inverted output V1 and the in-phase output V2 of the input signal V _in from the connection midpoints P3 and P4 of the collectors of the transistors Q1 and Q2 and the diodes D1 and D2, respectively. It is designed to output to 3.

The differential output stage 3 is composed of a pair of NPN type transistors Q3 and Q4, inputs an inverting output V1 and an in-phase output V2 to the bases of the transistors Q3 and Q4, respectively, and outputs a difference between the inverting output V1 and the in-phase output V2. The dynamic output is inverted and amplified and output from the output resistor R _L as an output signal V _out .

[0008]

By the way, the gain G (= R _L · I ₁ / R _IN ·
In order to increase I ₀ ), the emitter current I of the current source 6
Increasing ₁ is generally considered.

In this case, however, the collector currents of the transistors Q3 and Q4 increase as the emitter current I ₁ increases. However, in the NPN transistor, when the collector current exceeds or falls below a predetermined value, the base-emitter voltage is increased. There is a characteristic that the offset voltage ΔV of V _BE3 and V _BE4 suddenly becomes large, and the output dynamic range is narrowed due to the variation in the DC level of the output signal V _out (FIG. 5).

On the other hand, it is conceivable to reduce the emitter current I ₀ drawn from the current sources 4 and 5 or the input resistance R _IN , but in this case, there is a drawback that the input dynamic range is narrowed and the load is reduced. There is a drawback that the frequency characteristic is deteriorated when the resistance _RL is increased, and it is difficult to obtain a large gain G depending on the configuration of the Gilbert amplifier 1.

Therefore, it has been considered to correct the offset voltage ΔV caused by the increase of the collector current (FIG. 6). Here, the Gilbert amplifier 10 connects the emitters of NPN type transistors Q11 and Q12 to the collectors of the transistors Q1 and Q2 instead of the diodes D1 and D2, and outputs the difference between the correction voltages V3 and V4 generated by the correction voltage generator 11. It is designed to be applied to the dynamic output stage 3.

The correction voltage generation circuit 11 includes a gain control stage 12 for generating correction voltages V3 and V4 and an output stage 13 composed of a complementary push-pull circuit.
It is composed of A and 13B.

Here, the gain control stage 12 is similar to the differential input stage 2 in that a pair of NPN-type transistors Q13 and Q is used.
It has a configuration in which 14 emitters are connected via an input resistor R1 and current sources 14A and 14B are connected to each emitter.

The gain control stage 12 is adapted to generate the correction voltages V3 and V4 having a voltage difference corresponding to the offset voltage ΔV by adjusting the offset adjustment voltage ΔV ₀ input to the base of the transistor Q13. There is.

Incidentally, transistors Q15 and Q16 are cascode-connected to the collectors of the transistors Q13 and Q14, and the correction voltages V3 and V16 are connected from the midpoint of the connection.
4 is supplied to the output stages 13A and 13B.

On the other hand, the output stage 13A (13B) constitutes a complementary output stage by the NPN type transistor Q18 (Q22) and the PNP type transistor Q20 (Q24), and the respective transistors Q18 (Q22) and Q2.
The correction voltage V3 (V4) is output to the differential input stage 2 from the connection midpoint P13 (P14) of 0 (Q24).

The NPN transistor Q17 (Q2
1) and the PNP transistor Q19 (Q23), the idling current I1 flowing into the current source 15A (15B).
1A (I11B) allows the transistor Q18 (Q2
2) and Q20 (Q24) are supplied with a bias voltage so that the output stages 13A and 13B perform a push-pull operation.

As a result, the output stages 13A and 13B provide offset voltages having inverse characteristics to the offset voltage ΔV of the base-emitter voltage V _BE of the transistors Q3 and Q4 as correction voltages V3 and V4, and the output signal V _out of the DC Level variations can be canceled out.

Further, since the output stages of the output stages 13A and 13B are complementary output stages, the impedance can be made low, and the transistor Q1 becomes larger as the emitter current I ₀ becomes larger.
The electric charge stored in the parasitic capacitance between the base and the emitter of Q1 and Q12 can be discharged, and the frequency characteristic can be extended to a wide band.

However, the Gilbert amplifier 10 has a drawback that the number of elements increases to correct the offset voltage ΔV and the power consumption increases.
_{When CC} is small, there is a problem that the dynamic range is narrowed.

Similarly, as a Gilbert amplifier for correcting the offset voltage .DELTA.V, a base-grounded Gilbert amplifier 20 as shown in FIG. 7 in which parts corresponding to those in FIG.

The Gilbert amplifier 20 inputs the input signal V _in amplified through the operational amplifier 21 to the common emitter of the NPN transistors Q3 and Q4 forming a differential pair, and outputs the differential output V _in of the input signal V _{in. out} is output resistance R
It is designed to output via _L.

However, in this case as well, the correction voltage generator 11
However, if the power supply voltage V _CC is small, the dynamic range is narrowed.

Further, when the dynamic range of the output signal V _out is widened, the reference voltage E0 of the gain control stage 12 is set to three stages so that the temperature dependence characteristic does not occur at the connection midpoint P5 with the transistors Q3 and Q4. It was necessary to set the voltage including the voltage dependence of the base-emitter voltage of 3 V _BE so that it would be canceled.

The present invention has been made in consideration of the above points, and a conventional differential amplifier circuit with a correction means for correcting the offset voltage ΔV of the output stage, which is generated in order to increase the dynamic range of the output signal, has been used. The number of elements can be reduced. This makes it possible to easily obtain a wide-band amplifier circuit with low power consumption and low-voltage power supply and a wide bandwidth.

[0026]

In order to solve such a problem, in the first invention, the first and second differential input terminals P are provided.
In the differential amplifier circuit 30 which outputs the differential output of the in-phase input signal and the inverted input signal input to P4 and P3 from the differential output end P7, the first differential input end P4 is provided for the first offset voltage adjustment. 1st complementary output stage 34 for supplying the offset adjustment voltage V12 and second complementary output stage 33 for supplying the second offset adjustment voltage V11 for offset voltage adjustment to the second differential input terminal P3.
And the first and second complementary output stages 34
The first bias voltage / offset adjustment voltage (E1, V14) is supplied from the output end of the second bias output / offset adjustment voltage (E1 and V14) to the second complementary output stage 34 from the third and fourth output ends. , V13) for adjusting voltage generation output stage 32, and adjusting voltage generation output stage 3
2 generates the first and second offset correction voltages V14 and V13 based on the potential difference ΔV ₀ of the offset voltages supplied to the third and fourth differential input terminals, and the second and fourth offset correction voltages V14 and V13, respectively.
From the output terminal of the first and second offset correction voltages V
14 and V13 output correction voltage generator (Q13, Q13
14, R1, 33A and 33B) and a correction voltage generator (Q13, Q14, R1, 33A and 33B) connected in cascade, and a bias voltage generator (1) that outputs the reference voltage E1 from the first and third output terminals ( Q16, Q32 and Q15,
Q31) and a bias voltage generator (Q16, Q3
2 and Q15, Q31) are the reference voltage E1 supplied from the first and third output terminals and the first and second offset correction voltages V14 and V output from the second and fourth output terminals.
The potential difference (E1-V14 and E1-V13) from the first and second complementary output stages 34 and 33.
Are supplied with the first and second bias voltages.

Further, in the second invention, the first and second
In the base-grounded differential amplifier circuit 40 that adjusts and outputs the gain G of the output signal V _out based on the bias voltage input to the differential input terminals P4 and P3 of the first differential input terminal P14. A first complementary output stage 34 for supplying a first offset adjustment voltage V12 for offset voltage adjustment, and a second complementary output stage 34 for supplying a second offset adjustment voltage V11 for offset voltage adjustment to a second differential input terminal P13.
The first complementary output stage 33 and the first complementary output stage 34 are supplied with the first bias voltage / offset adjustment voltage (E1, V14) from the first and second output terminals, and are supplied to the second complementary output stage 34. Third and fourth
And an adjustment voltage generation output stage 32 for supplying a second bias voltage / offset adjustment voltage (E1, V13) from the output end of the adjustment voltage generation output stage 32 to the third and fourth differential input ends. First and second offset correction voltages V14 and V12 are generated based on the potential difference ΔV ₀ of the supplied offset voltage, and the first and second offset correction voltages V12 and V11 are generated from the second and fourth output terminals. Of the correction voltage generators (Q13, Q14, R1, 33A and 33B) and the correction voltage generators (Q13, Q14, R1,
33A and 33B) and a bias voltage generator (Q16, Q32 and Q15, Q31) that outputs the reference voltage E1 from the first and third output terminals, and the bias voltage generator (Q16, Q32). And Q15, Q31)
Is a potential difference (E1−E1) between the reference voltage E1 supplied from the first and third output terminals and the first and second offset correction voltages V14 and V13 output from the second and fourth output terminals.
V14 and E1-V13) are used to supply the first and second bias voltages to the first and second complementary output stages 34 and 33.

Further, in the third aspect of the invention, the adjustment voltage generation output stage 32 includes the first or second offset correction voltage V.
14 and V13 with the input signal V _in superimposed thereon to generate the first and second bias voltage / offset adjustment voltages (E1, V14).
And E1, V13), the in-phase output signal V2 and the inverted output signal V1 are superimposed.

[0029]

[Function] The first and second differential input terminals P4 and P3 have the first
And first and second complementary output stages 34 and 3 for supplying the second offset regulation voltages V12 and V11.
3 to the first and second offset correction voltages V14 and V1
3 and the first and second bias voltages (E1-V14 and E
By partially sharing the generator circuit for supplying 1-V13), it is possible to easily obtain a differential amplifier circuit having a much smaller number of elements and a smaller variation in offset voltage than the conventional one.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 6 are designated by the same reference numerals, numeral 30 indicates a Gilbert amplifier with an offset voltage correction circuit as a whole, and a part of the circuit of the gain control stage 12 and the output stages 13A and 13B. It has the same configuration except that it has a correction voltage generating section 31 which is shared.

Here, the correction voltage generator 31 includes a transistor Q13 which constitutes a differential pair of the gain control stage 32.
PNP type transistors Q31 and Q32 are diode-connected to the collectors of Q14 and Q14, respectively.

That is, the correction voltage generator 31 includes a circuit for generating the correction voltages V13 and V14 and an idling current I11.
The generation circuits for A and I11 are shared. As a result, the correction voltage generator 31 causes the transistor Q
The current I20 flowing through 15, Q31, Q16, and Q32 is set as an idling current, and a reverse offset voltage for canceling the offset voltage ΔV is supplied to the complementary output stages of the output stages 33 and 34.

In the above configuration, when the collector current flowing in the differential output stage 3 is increased for use as the output circuit of the wide band amplifier circuit, for example, the base-emitter voltage V _{BE of the} transistor Q3 is the base of the other transistor Q4. -The voltage is lower than the voltage V _BE between the emitters, and even if the offset voltage ΔV expands, the Gilbert amplifier 30
Can correct the offset voltage ΔV, and can extend the frequency characteristic to a high frequency range.

In the case of this embodiment, when the control voltage ΔV ₀ of the gain control stage 32 is made negative and the base potential of the transistor Q13 is set lower than the base potential of the other transistor Q14, the base potential of the transistor Q31 becomes the other. It has a high value with respect to the base potential of the transistor Q32.

As a result, the correction voltage V11 at the connection midpoint P13 of the output stage 33 becomes higher than the correction voltage V12 at the connection midpoint P14 of the other output stage 34 by the offset voltage ΔV.

As a result, the offset voltage .DELTA.V generated by increasing the collector currents flowing through the transistors Q3 and Q4 has an offset voltage (-.DELTA.V) opposite to the offset voltage .DELTA.V, and the offset voltage generated in the transistors Q3 and Q4. ΔV will be canceled.

At this time, a pair of transistors Q18,
Complementary output stages 33 and 34 formed by Q20, Q22 and Q24 include transistors Q15 and Q24.
A bias voltage is given by the idling currents flowing through 31 and Q16 and Q32, and the output impedance becomes small because it operates as a push-pull circuit, and it is possible to effectively avoid the possibility that the frequency characteristics of the Gilbert amplifier 30 deteriorate.

As described above, the Gilbert amplifier 30 can constitute a differential amplifier circuit with the number of elements smaller than those of the conventional emitter-grounded Gilbert amplifier 10 by the transistors Q17 and Q21 and the current sources 15A and 15B. As a result, the power consumption of the Gilbert amplifier 30 can be further reduced as compared with the conventional case.

In order to maximize the output dynamic range of the Gilbert amplifier 30, the potential of the common emitter P5 of the differential output stage 3 is corrected within the operating range of the current source 6 so that it has no temperature characteristic. Although necessary, in the case of the conventional Gilbert amplifier 10 (transistors Q3, Q11, Q18
And the base-emitter voltage 4V _BE of four transistors Q15 (Q12, Q22, Q16) is corrected, and the base-emitter voltage 3V _{BE of} three transistors Q15 (Q16) is less than that of the transistor Q15 (Q16). Therefore, the correction accuracy of the output DC level can be further improved.

According to the above configuration, a part of the gain control stage 32 composed of the resistor and the differential amplifier circuit is shared with the current source circuit for supplying the idling current to the complementary output stage, so that it can be compared with the conventional one. Thus, it is possible to easily obtain a wideband Gilbert amplifier that consumes less power and has less variation in the output DC level at the final stage.

In the embodiment described above, the four current sources 14A and 14B in the conventional correction voltage generator 31 are controlled by the current sources 33A and 33B of the gain controller 32.
And the case where 15A and 15B are shared,
The present invention is not limited to this, and the transistors Q13 and Q31
From the midpoint of connection between Q14 and Q32 and current sources 33A, 33
The current sources 35A and 35B are connected in parallel to B (not shown), and the present invention can be widely applied to a case where an idling current is separately supplied.

Thus, it is possible to effectively avoid the possibility that the current flowing through the transistors Q15, Q31 or Q16, Q32 will almost disappear when the correction voltage ΔV ₀ is varied.

In the above-described embodiment, the case where the present invention is applied to the emitter-grounded Gilbert amplifier 30 has been described. However, the present invention is not limited to this, and may be applied to the base-grounded Gilbert amplifier 40. good.

That is, in FIG. 2 in which parts corresponding to those in FIG. 1 and FIG.
In comparison with the conventional grounded base type Gilbert amplifier 20, the transistors Q17 and Q21 for supplying the idling currents I11A and I11B and the current sources 15A and 15B can be eliminated.

The push-pull output stages 33 and 34 of the Gilbert amplifier 40 discharge the electric charges accumulated in the parasitic capacitance between the bases and the emitters of the differential transistors Q3 and Q4 of the differential output stage 3. ..

As a result, the Gilbert amplifier 40 can be made to consume much less power than the conventional one, and the frequency characteristics can be extended.

At this time, the temperature characteristic of the base-emitter voltage corrected by the reference voltage E1 of the Gilbert amplifier 40 is sufficient for two transistors Q3 and Q18 (Q4 and Q22), which is one base compared to the conventional one. The correction amount is reduced by the voltage between the emitters, and the variation in the DC level in the final stage can be adjusted with higher accuracy.

Further, in the above embodiment, the differential outputs V1 and V2 of the input signal V _in input to the differential input stage 2 are used.
Is supplied to the differential output stage 3 and the offset voltage ΔV of the base-emitter voltage of the differential transistors Q3 and Q4 of the differential output stage 3 is corrected by the correction voltage generating section 31. However, the correction voltage generator 31 is not limited to
Can also be widely applied to the case of sharing the same with the differential input stage 2.

That is, in FIG. 3 in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, the Gilbert amplifier 50 uses the input signal V as the correction voltage ΔV ₀ of the gain control stage 32.
_In is supplied, so that the differential input stage 2 and the gain control stage 32 can be shared.

Further, in the above-mentioned embodiment, the Gilbert amplifiers 30 and 40 according to the present invention shown in FIGS.
However, the present invention is not limited to this and can be widely applied to the case where the number of circuit elements of the offset voltage adjusting circuit is reduced.

[0052]

As described above, according to the present invention, the correction voltage generator for supplying the first and second offset correction voltages to the first and second complementary output stages, and the first and second correction voltage generators.
The bias voltage generators that supply the bias voltage are connected in cascade, and by sharing a part of each circuit, it is possible to adjust the offset voltage variation with a much smaller number of elements than before and to reduce power consumption. Can be made even smaller.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing an embodiment of a differential amplifier circuit according to the present invention.

FIG. 2 is an equivalent circuit diagram for explaining another embodiment.

FIG. 3 is an equivalent circuit diagram for explaining another embodiment.

FIG. 4 is an equivalent circuit diagram for explaining a Gilbert amplifier.

FIG. 5 is a characteristic curve diagram showing a collector current characteristic of an offset voltage generated in the final differential output stage.

FIG. 6 is an equivalent circuit diagram provided for explaining a conventional differential amplifier circuit.

FIG. 7 is an equivalent circuit diagram for explaining a conventional differential amplifier circuit.

[Explanation of symbols]

1, 10, 20, 30, 40, 50 ... Gilbert amplifier, 31, 41, 51 ... Correction voltage generator, 32 ... Gain control stage, 33, 34 ... Complementary output stage.

Claims (3)

[Claims] 1. A differential amplifier circuit for outputting differential outputs of an in-phase input signal and an inverted input signal input to first and second differential input terminals from a differential output terminal, wherein the first differential A first complementary output stage for supplying a first offset adjustment voltage for adjusting the offset voltage to an input terminal, and a second complementary output stage for supplying a second offset adjustment voltage for adjusting the offset voltage to the second differential input terminal. The first complementary output stage and the first complementary output stage are supplied with the first bias voltage and offset adjustment voltage from the first and second output terminals, and the second and third complementary output stages are supplied with the third and fourth outputs. An adjustment voltage generation output stage for supplying a second bias voltage / offset adjustment voltage from the end, wherein the adjustment voltage generation output stage is provided for the offset voltage supply to the third and fourth differential input ends. A correction voltage generating section for generating first and second offset correction voltages on the basis of a potential difference between the first and second output terminals, and outputting the first and second offset correction voltages from the second and fourth output terminals; The first and the third are connected in series to the generator.
A bias voltage generator for outputting a reference voltage from the output terminal of the reference voltage supplied from the first and third output terminals and a bias voltage generator from the second and fourth output terminals. A differential amplifier circuit, characterized in that the first and second bias voltages are supplied to the first and second complementary output stages by the potential difference between the first and second offset correction voltages that are output. 2. A grounded-base differential amplifier circuit which adjusts the gain of an output signal based on a bias voltage input to first and second differential input terminals and outputs the adjusted signal. A first complementary output stage for supplying a first offset adjustment voltage for adjusting the offset voltage to an input terminal, and a second complementary output stage for supplying a second offset adjustment voltage for adjusting the offset voltage to the second differential input terminal. The first complementary output stage and the first complementary output stage are supplied with the first bias voltage and offset adjustment voltage from the first and second output terminals, and the second and third complementary output stages are supplied with the third and fourth outputs. An adjustment voltage generation output stage for supplying a second bias voltage / offset adjustment voltage from the end, wherein the adjustment voltage generation output stage is provided for the offset voltage supplied to the third and fourth differential input ends. A first and a second offset correction voltage based on the potential difference of the source voltage, and a correction voltage generator for outputting the first and second offset correction voltages from the second and fourth output terminals; The correction voltage generators are connected in cascade, and the first and third
A bias voltage generator for outputting a reference voltage from the output terminal of the reference voltage supplied from the first and third output terminals A differential amplifier circuit, characterized in that the first and second bias voltages are supplied to the first and second complementary output stages by the potential difference between the first and second offset correction voltages that are output. 3. The adjusting voltage generating / outputting stage superimposes an input signal on the first or second offset correction voltage, and outputs the common-mode input signal and the in-phase input signal to the first and second bias voltage / offset adjusting voltages. The differential amplifier circuit according to claim 1, wherein an inverted input signal is superimposed.